xue/kicad/xue-rnc/xue-rnc.net

# EESchema Netlist Version 1.1 created  Sun 17 Oct 2010 08:51:07 AM COT
(
 ( /4CB0D95D/4CBAFE50 header25x2_smd_2mm  P1 CONN_25X2 {Lib=CONN_25X2}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 )
  (    2 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 )
  (    3 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_16 )
  (    4 /FPGA_GPIOS/FPGA_BANK0_IO_9 )
  (    5 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 )
  (    6 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 )
  (    7 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10 )
  (    8 /FPGA_GPIOS/FPGA_BANK0_IO_15 )
  (    9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 )
  (   10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_3 )
  (   11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5 )
  (   12 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18 )
  (   13 /FPGA_GPIOS/FPGA_BANK0_IO_17 )
  (   14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 )
  (   15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 )
  (   16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24 )
  (   17 /FPGA_GPIOS/FPGA_BANK0_IO_28 )
  (   18 /FPGA_GPIOS/FPGA_BANK0_IO_29 )
  (   19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 )
  (   20 /FPGA_GPIOS/FPGA_BANK0_IO_30 )
  (   21 /FPGA_GPIOS/FPGA_BANK0_IO_27 )
  (   22 /FPGA_GPIOS/FPGA_BANK0_IO_25 )
  (   23 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 )
  (   24 /FPGA_GPIOS/FPGA_BANK0_IO_33 )
  (   25 /FPGA_GPIOS/FPGA_BANK0_IO_2 )
  (   26 /FPGA_GPIOS/FPGA_BANK0_IO_32 )
  (   27 /FPGA_GPIOS/FPGA_BANK0_IO_7 )
  (   28 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 )
  (   29 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 )
  (   30 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 )
  (   31 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 )
  (   32 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 )
  (   33 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 )
  (   34 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 )
  (   35 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 )
  (   36 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 )
  (   37 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 )
  (   38 /FPGA_GPIOS/FPGA_BANK0_IO_50 )
  (   39 /FPGA_GPIOS/FPGA_BANK0_IO_56 )
  (   40 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 ? )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
  (   49 ? )
  (   50 ? )
 )
 ( /4C9E2AF4/4CAF29D5 $noname  MP1 M12-TU400A {Lib=M12-TU400A}
  (    1 ? )
  (    2 ? )
 )
 ( /4C9E2AF4/4C9E3C76 $noname  C140 100nF {Lib=C}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C71 $noname  C142 100nF {Lib=C}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C70 $noname  C144 10uF {Lib=CAPAPOL}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C6F $noname  C143 100nF {Lib=C}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C6E $noname  C141 100nF {Lib=C}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C65 $noname  C136 100nF {Lib=C}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C5F $noname  C138 100nF {Lib=C}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C5E $noname  C139 10uF {Lib=CAPAPOL}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C5D $noname  C137 100nF {Lib=C}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C32 $noname  C133 100nF {Lib=C}
  (    1 +2.8_VAA )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C2E $noname  C135 10uF {Lib=CAPAPOL}
  (    1 +2.8_VAA )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C2D $noname  C134 100nF {Lib=C}
  (    1 +2.8_VAA )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C27 $noname  C131 100nF {Lib=C}
  (    1 +2.8_VAAPIX )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C26 $noname  C132 10uF {Lib=CAPAPOL}
  (    1 +2.8_VAAPIX )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C04 $noname  C130 10uF {Lib=CAPAPOL}
  (    1 +2.8_VDDPLL )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3C00 $noname  C129 100nF {Lib=C}
  (    1 +2.8_VDDPLL )
  (    2 GND )
 )
 ( /4C9E2AF4/4C9E3B7C $noname  U24 MT9M033 {Lib=MT9M033}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 )
  (    2 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 )
  (    3 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT6 )
  (    4 +2.8_VDDPLL )
  (    5 /Image_Sensor/IS_EXTCLK )
  (    6 GND )
  (    7 /Image_Sensor/IS_DOUT7 )
  (    8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 )
  (    9 /Image_Sensor/IS_DOUT9 )
  (   10 /Image_Sensor/IS_DOUT10 )
  (   11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 )
  (   12 +2.8_VDDIO )
  (   13 /Image_Sensor/IS_PIXEL )
  (   14 /Image_Sensor/+1.8_VDD )
  (   15 /Image_Sensor/IS_SCL )
  (   16 /FPGA,_Port0,_Port2,_PROG_IF/IS_SDA )
  (   17 /FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N )
  (   18 +2.8_VDDIO )
  (   19 /Image_Sensor/+1.8_VDD )
  (   20 ? )
  (   21 ? )
  (   22 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY )
  (   23 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
  (   24 /FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR )
  (   25 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST )
  (   26 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH )
  (   27 /Image_Sensor/IS_TRIGGER )
  (   28 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
  (   29 /Image_Sensor/IS_LINE )
  (   30 GND )
  (   31 ? )
  (   32 ? )
  (   33 ? )
  (   34 +2.8_VAA )
  (   35 GND )
  (   36 +2.8_VAA )
  (   37 +2.8_VAAPIX )
  (   38 +2.8_VAAPIX )
  (   39 GND )
  (   40 +2.8_VAA )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 /Image_Sensor/IS_DOUT0 )
  (   46 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1 )
  (   47 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
  (   48 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 )
 )
 ( /4C9E2B0F/4C9E2BAA $noname  C107 10uF {Lib=CAPAPOL}
  (    1 N-000467 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2BA9 $noname  C110 10nF {Lib=C}
  (    1 N-000469 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2BA8 $noname  R64 R {Lib=R}
  (    1 N-000470 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2BA7 $noname  R63 R {Lib=R}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 N-000470 )
 )
 ( /4C9E2B0F/4C9E2BA6 $noname  C116 10uF {Lib=CAPAPOL}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2BA5 $noname  C113 22pF {Lib=C}
  (    1 /Image_Sensor/+1.8_VDD )
  (    2 N-000470 )
 )
 ( /4C9E2B0F/4C9E2BA4 $noname  U20 TPS793XX {Lib=TPS793XX}
  (    1 N-000467 )
  (    2 GND )
  (    3 N-000467 )
  (    4 N-000469 )
  (    5 N-000470 )
  (    6 /Image_Sensor/+1.8_VDD )
 )
 ( /4C9E2B0F/4C9E2B96 $noname  U23 TPS793XX {Lib=TPS793XX}
  (    1 N-000462 )
  (    2 GND )
  (    3 N-000462 )
  (    4 N-000468 )
  (    5 N-000463 )
  (    6 +2.8_VDDPLL )
 )
 ( /4C9E2B0F/4C9E2B95 $noname  C125 22pF {Lib=C}
  (    1 +2.8_VDDPLL )
  (    2 N-000463 )
 )
 ( /4C9E2B0F/4C9E2B94 $noname  C128 10uF {Lib=CAPAPOL}
  (    1 +2.8_VDDPLL )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B93 $noname  R67 R {Lib=R}
  (    1 +2.8_VDDPLL )
  (    2 N-000463 )
 )
 ( /4C9E2B0F/4C9E2B92 $noname  R68 R {Lib=R}
  (    1 N-000463 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B91 $noname  C121 10nF {Lib=C}
  (    1 N-000468 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B90 $noname  C118 10uF {Lib=CAPAPOL}
  (    1 N-000462 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B86 $noname  C117 10uF {Lib=CAPAPOL}
  (    1 N-000461 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B85 $noname  C120 10nF {Lib=C}
  (    1 N-000465 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B84 $noname  R66 R {Lib=R}
  (    1 N-000466 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B83 $noname  R65 R {Lib=R}
  (    1 +2.8_VDDIO )
  (    2 N-000466 )
 )
 ( /4C9E2B0F/4C9E2B82 $noname  C127 10uF {Lib=CAPAPOL}
  (    1 +2.8_VDDIO )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B81 $noname  C124 22pF {Lib=C}
  (    1 +2.8_VDDIO )
  (    2 N-000466 )
 )
 ( /4C9E2B0F/4C9E2B80 $noname  U22 TPS793XX {Lib=TPS793XX}
  (    1 N-000461 )
  (    2 GND )
  (    3 N-000461 )
  (    4 N-000465 )
  (    5 N-000466 )
  (    6 +2.8_VDDIO )
 )
 ( /4C9E2B0F/4C9E2B72 $noname  U19 TPS793XX {Lib=TPS793XX}
  (    1 N-000473 )
  (    2 GND )
  (    3 N-000473 )
  (    4 N-000464 )
  (    5 N-000474 )
  (    6 +2.8_VAAPIX )
 )
 ( /4C9E2B0F/4C9E2B71 $noname  C112 22pF {Lib=C}
  (    1 +2.8_VAAPIX )
  (    2 N-000474 )
 )
 ( /4C9E2B0F/4C9E2B70 $noname  C115 10uF {Lib=CAPAPOL}
  (    1 +2.8_VAAPIX )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B6F $noname  R61 R {Lib=R}
  (    1 +2.8_VAAPIX )
  (    2 N-000474 )
 )
 ( /4C9E2B0F/4C9E2B6E $noname  R62 R {Lib=R}
  (    1 N-000474 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B6D $noname  C109 10nF {Lib=C}
  (    1 N-000464 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2B6C $noname  C106 10uF {Lib=CAPAPOL}
  (    1 N-000473 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E28CB $noname  C105 10uF {Lib=CAPAPOL}
  (    1 N-000471 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E28C1 $noname  C108 10nF {Lib=C}
  (    1 N-000472 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E289D $noname  R60 R {Lib=R}
  (    1 N-000475 )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E287F $noname  R59 R {Lib=R}
  (    1 +2.8_VAA )
  (    2 N-000475 )
 )
 ( /4C9E2B0F/4C9E286D $noname  C114 10uF {Lib=CAPAPOL}
  (    1 +2.8_VAA )
  (    2 GND )
 )
 ( /4C9E2B0F/4C9E2857 $noname  C111 22pF {Lib=C}
  (    1 +2.8_VAA )
  (    2 N-000475 )
 )
 ( /4C9E2B0F/4C9E2848 $noname  U18 TPS793XX {Lib=TPS793XX}
  (    1 N-000471 )
  (    2 GND )
  (    3 N-000471 )
  (    4 N-000472 )
  (    5 N-000475 )
  (    6 +2.8_VAA )
 )
 ( /4C7BC2B2/4C749A0C 0402  C94 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C748EDB 0402  C92 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C748EDA 0402  C93 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C73D252 0402  C91 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C73D074 0402  C90 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C7168DD 0402  R30 330 {Lib=R}
  (    1 +3.3V )
  (    2 N-000415 )
 )
 ( /4C7BC2B2/4C716877 0402  R29 4.7k {Lib=R}
  (    1 +3.3V )
  (    2 N-000418 )
 )
 ( /4C7BC2B2/4C6B29DA 0402  C77 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C6B29A3 0402  C76 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D9D $noname  C66 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D9A $noname  C63 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D99 $noname  C60 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D98 $noname  C57 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D97 $noname  C54 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D53 $noname  C69 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D49 $noname  C67 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D46 $noname  C64 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D45 $noname  C61 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D44 $noname  C58 4.7uF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D43 $noname  C55 100uF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656D08 $noname  C68 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CFC $noname  C65 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CFB $noname  C62 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CFA $noname  C59 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CF9 $noname  C56 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CBB $noname  C50 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CBA $noname  C47 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CB9 $noname  C44 4.7uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656CB7 $noname  C41 100uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656C49 $noname  C53 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656C27 $noname  C51 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656C24 $noname  C49 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656C16 $noname  C46 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656BFA $noname  C52 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656BF9 $noname  C43 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656BF8 $noname  C40 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656AC2 $noname  C48 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656AC0 $noname  C45 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656ABD $noname  C42 4.7uF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C656A80 $noname  C39 100uF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C7BC2B2/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   A1 GND )
  (   A2 ? )
  (   A3 ? )
  (   A4 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK )
  (   A5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 )
  (   A6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV )
  (   A7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC )
  (   A8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 )
  (   A9 /Ethernet_Phy/ETH_COL )
  (  A10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT )
  (  A11 /Non_volatile_memories/NF_D6 )
  (  A12 /Non_volatile_memories/NF_D4 )
  (  A13 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 )
  (  A14 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
  (  A15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
  (  A16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 )
  (  A17 /Non_volatile_memories/SD_CLK )
  (  A18 /Non_volatile_memories/SD_DAT0 )
  (  A19 /DBG_PRG/FPGA_TDO )
  (  A20 /USB/USBD_RCV )
  (  A21 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
  (  A22 GND )
  (  AA1 N-000418 )
  (  AA2 /Image_Sensor/IS_LINE )
  (  AA3 VCCO2 )
  (  AA4 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST )
  (  AA5 GND )
  (  AA6 /FPGA,_Port0,_Port2,_PROG_IF/IS_SDA )
  (  AA7 VCCO2 )
  (  AA8 /Image_Sensor/IS_DOUT7 )
  (  AA9 GND )
  ( AA10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 )
  ( AA11 VCCO2 )
  ( AA12 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1 )
  ( AA13 GND )
  ( AA14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 )
  ( AA15 VCCO2 )
  ( AA16 /FPGA_GPIOS/FPGA_BANK0_IO_28 )
  ( AA17 GND )
  ( AA18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18 )
  ( AA19 VCCO2 )
  ( AA20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
  ( AA21 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
  ( AA22 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 )
  (  AB1 GND )
  (  AB2 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
  (  AB3 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH )
  (  AB4 /FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR )
  (  AB5 /FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N )
  (  AB6 /Image_Sensor/IS_PIXEL )
  (  AB7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 )
  (  AB8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 )
  (  AB9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 )
  ( AB10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 )
  ( AB11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
  ( AB12 /Image_Sensor/IS_DOUT0 )
  ( AB13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 )
  ( AB14 ? )
  ( AB15 /FPGA_GPIOS/FPGA_BANK0_IO_33 )
  ( AB16 /FPGA_GPIOS/FPGA_BANK0_IO_29 )
  ( AB17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 )
  ( AB18 ? )
  ( AB19 ? )
  ( AB20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
  ( AB21 ? )
  ( AB22 GND )
  (   B1 ? )
  (   B2 ? )
  (   B3 ? )
  (   B4 +3.3V )
  (   B5 GND )
  (   B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
  (   B7 +3.3V )
  (   B8 /Ethernet_Phy/ETH_RXER )
  (   B9 GND )
  (  B10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
  (  B11 +3.3V )
  (  B12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 )
  (  B13 GND )
  (  B14 /Non_volatile_memories/NF_CLE )
  (  B15 +3.3V )
  (  B16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 )
  (  B17 GND )
  (  B18 /Non_volatile_memories/SD_DAT1 )
  (  B19 +3.3V )
  (  B20 /USB/USBD_SPD )
  (  B21 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP )
  (  B22 /USB/USBD_VM )
  (   C1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
  (   C2 +2.5V )
  (   C3 ? )
  (   C4 ? )
  (   C5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 )
  (   C6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD2 )
  (   C7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N )
  (   C8 /Ethernet_Phy/ETH_TXC )
  (   C9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 )
  (  C10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 )
  (  C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
  (  C12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
  (  C13 ? )
  (  C14 /Non_volatile_memories/NF_WE_N )
  (  C15 /Non_volatile_memories/NF_RE_N )
  (  C16 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD )
  (  C17 ? )
  (  C18 /DBG_PRG/FPGA_TMS )
  (  C19 /USB/USBA_OE_N )
  (  C20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
  (  C21 +2.5V )
  (  C22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
  (   D1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
  (   D2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
  (   D3 ? )
  (   D4 GND )
  (   D5 ? )
  (   D6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO )
  (   D7 /Ethernet_Phy/ETH_MDC )
  (   D8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
  (   D9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN )
  (  D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
  (  D11 /Non_volatile_memories/NF_D7 )
  (  D12 ? )
  (  D13 ? )
  (  D14 /Non_volatile_memories/NF_D1 )
  (  D15 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N )
  (  D16 +2.5V )
  (  D17 ? )
  (  D18 GND )
  (  D19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP )
  (  D20 /USB/USBA_VM )
  (  D21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
  (  D22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
  (   E1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
  (   E2 GND )
  (   E3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
  (   E4 ? )
  (   E5 ? )
  (   E6 ? )
  (   E7 GND )
  (   E8 ? )
  (   E9 +3.3V )
  (  E10 ? )
  (  E11 GND )
  (  E12 ? )
  (  E13 +3.3V )
  (  E14 ? )
  (  E15 GND )
  (  E16 ? )
  (  E17 +3.3V )
  (  E18 /DBG_PRG/FPGA_TDI )
  (  E19 +2.5V )
  (  E20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
  (  E21 GND )
  (  E22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
  (   F1 ? )
  (   F2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
  (   F3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
  (   F4 +2.5V )
  (   F5 ? )
  (   F6 +2.5V )
  (   F7 ? )
  (   F8 ? )
  (   F9 ? )
  (  F10 ? )
  (  F11 +2.5V )
  (  F12 ? )
  (  F13 ? )
  (  F14 ? )
  (  F15 ? )
  (  F16 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD )
  (  F17 /USB/USBA_RCV )
  (  F18 ? )
  (  F19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
  (  F20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
  (  F21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
  (  F22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
  (   G1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
  (   G2 +2.5V )
  (   G3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
  (   G4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
  (   G5 GND )
  (   G6 ? )
  (   G7 ? )
  (   G8 ? )
  (   G9 ? )
  (  G10 +3.3V )
  (  G11 ? )
  (  G12 +2.5V )
  (  G13 ? )
  (  G14 +3.3V )
  (  G15 /DBG_PRG/FPGA_TCK )
  (  G16 ? )
  (  G17 ? )
  (  G18 GND )
  (  G19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
  (  G20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
  (  G21 +2.5V )
  (  G22 ? )
  (   H1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
  (   H2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
  (   H3 /DDR_Banks/M0_CLK# )
  (   H4 /DDR_Banks/M0_CLK )
  (   H5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
  (   H6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
  (   H7 GND )
  (   H8 ? )
  (   H9 +2.5V )
  (  H10 ? )
  (  H11 ? )
  (  H12 ? )
  (  H13 ? )
  (  H14 ? )
  (  H15 +2.5V )
  (  H16 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
  (  H17 ? )
  (  H18 ? )
  (  H19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
  (  H20 /DDR_Banks/M1_CLK )
  (  H21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
  (  H22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
  (   J1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
  (   J2 GND )
  (   J3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
  (   J4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
  (   J5 +2.5V )
  (   J6 ? )
  (   J7 ? )
  (   J8 +1.2V )
  (   J9 GND )
  (  J10 +1.2V )
  (  J11 GND )
  (  J12 +1.2V )
  (  J13 GND )
  (  J14 +1.2V )
  (  J15 GND )
  (  J16 ? )
  (  J17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
  (  J18 +2.5V )
  (  J19 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# )
  (  J20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
  (  J21 GND )
  (  J22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
  (   K1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
  (   K2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
  (   K3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
  (   K4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
  (   K5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
  (   K6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
  (   K7 ? )
  (   K8 ? )
  (   K9 +1.2V )
  (  K10 GND )
  (  K11 +1.2V )
  (  K12 GND )
  (  K13 +1.2V )
  (  K14 GND )
  (  K15 +2.5V )
  (  K16 ? )
  (  K17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
  (  K18 ? )
  (  K19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
  (  K20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
  (  K21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
  (  K22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
  (   L1 ? )
  (   L2 +2.5V )
  (   L3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
  (   L4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
  (   L5 GND )
  (   L6 ? )
  (   L7 +2.5V )
  (   L8 +2.5V )
  (   L9 GND )
  (  L10 +1.2V )
  (  L11 GND )
  (  L12 +1.2V )
  (  L13 GND )
  (  L14 +1.2V )
  (  L15 ? )
  (  L16 +2.5V )
  (  L17 ? )
  (  L18 GND )
  (  L19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
  (  L20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
  (  L21 +2.5V )
  (  L22 ? )
  (   M1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
  (   M2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
  (   M3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
  (   M4 ? )
  (   M5 ? )
  (   M6 ? )
  (   M7 ? )
  (   M8 ? )
  (   M9 +1.2V )
  (  M10 GND )
  (  M11 +1.2V )
  (  M12 GND )
  (  M13 +1.2V )
  (  M14 GND )
  (  M15 +2.5V )
  (  M16 ? )
  (  M17 ? )
  (  M18 ? )
  (  M19 ? )
  (  M20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
  (  M21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
  (  M22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
  (   N1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
  (   N2 GND )
  (   N3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
  (   N4 ? )
  (   N5 +2.5V )
  (   N6 ? )
  (   N7 ? )
  (   N8 +2.5V )
  (   N9 GND )
  (  N10 +1.2V )
  (  N11 GND )
  (  N12 +1.2V )
  (  N13 GND )
  (  N14 +1.2V )
  (  N15 GND )
  (  N16 ? )
  (  N17 GND )
  (  N18 +2.5V )
  (  N19 ? )
  (  N20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
  (  N21 GND )
  (  N22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
  (   P1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
  (   P2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
  (   P3 ? )
  (   P4 ? )
  (   P5 ? )
  (   P6 ? )
  (   P7 ? )
  (   P8 ? )
  (   P9 +1.2V )
  (  P10 GND )
  (  P11 +1.2V )
  (  P12 GND )
  (  P13 +1.2V )
  (  P14 GND )
  (  P15 ? )
  (  P16 ? )
  (  P17 ? )
  (  P18 ? )
  (  P19 ? )
  (  P20 ? )
  (  P21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
  (  P22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
  (   R1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
  (   R2 +2.5V )
  (   R3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
  (   R4 ? )
  (   R5 GND )
  (   R6 +2.5V )
  (   R7 ? )
  (   R8 ? )
  (   R9 ? )
  (  R10 +2.5V )
  (  R11 ? )
  (  R12 +2.5V )
  (  R13 ? )
  (  R14 +1.2V )
  (  R15 ? )
  (  R16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 )
  (  R17 ? )
  (  R18 GND )
  (  R19 ? )
  (  R20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
  (  R21 +2.5V )
  (  R22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
  (   T1 ? )
  (   T2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
  (   T3 ? )
  (   T4 ? )
  (   T5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO )
  (   T6 ? )
  (   T7 ? )
  (   T8 ? )
  (   T9 VCCO2 )
  (  T10 ? )
  (  T11 ? )
  (  T12 ? )
  (  T13 VCCO2 )
  (  T14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 )
  (  T15 /FPGA_GPIOS/FPGA_BANK0_IO_7 )
  (  T16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 )
  (  T17 /FPGA_GPIOS/FPGA_BANK0_IO_2 )
  (  T18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 )
  (  T19 ? )
  (  T20 ? )
  (  T21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
  (  T22 ? )
  (   U1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
  (   U2 GND )
  (   U3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
  (   U4 ? )
  (   U5 +2.5V )
  (   U6 ? )
  (   U7 GND )
  (   U8 ? )
  (   U9 ? )
  (  U10 /FPGA_GPIOS/FPGA_BANK0_IO_56 )
  (  U11 +2.5V )
  (  U12 ? )
  (  U13 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 )
  (  U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
  (  U15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_16 )
  (  U16 /FPGA_GPIOS/FPGA_BANK0_IO_9 )
  (  U17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 )
  (  U18 +2.5V )
  (  U19 ? )
  (  U20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
  (  U21 GND )
  (  U22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
  (   V1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
  (   V2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
  (   V3 ? )
  (   V4 GND )
  (   V5 ? )
  (   V6 +2.5V )
  (   V7 ? )
  (   V8 VCCO2 )
  (   V9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 )
  (  V10 GND )
  (  V11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 )
  (  V12 VCCO2 )
  (  V13 ? )
  (  V14 GND )
  (  V15 /FPGA_GPIOS/FPGA_BANK0_IO_17 )
  (  V16 VCCO2 )
  (  V17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 )
  (  V18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 )
  (  V19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10 )
  (  V20 ? )
  (  V21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
  (  V22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
  (   W1 ? )
  (   W2 +2.5V )
  (   W3 ? )
  (   W4 ? )
  (   W5 VCCO2 )
  (   W6 ? )
  (   W7 GND )
  (   W8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 )
  (   W9 /FPGA_GPIOS/FPGA_BANK0_IO_50 )
  (  W10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 )
  (  W11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 )
  (  W12 /Image_Sensor/IS_EXTCLK )
  (  W13 /FPGA_GPIOS/FPGA_BANK0_IO_27 )
  (  W14 /FPGA_GPIOS/FPGA_BANK0_IO_30 )
  (  W15 /FPGA_GPIOS/FPGA_BANK0_IO_25 )
  (  W16 GND )
  (  W17 /FPGA_GPIOS/FPGA_BANK0_IO_15 )
  (  W18 ? )
  (  W19 GND )
  (  W20 ? )
  (  W21 +2.5V )
  (  W22 ? )
  (   Y1 ? )
  (   Y2 ? )
  (   Y3 /Image_Sensor/IS_TRIGGER )
  (   Y4 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
  (   Y5 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY )
  (   Y6 /Image_Sensor/IS_DOUT10 )
  (   Y7 /Image_Sensor/IS_DOUT9 )
  (   Y8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT6 )
  (   Y9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 )
  (  Y10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 )
  (  Y11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 )
  (  Y12 /Image_Sensor/IS_SCL )
  (  Y13 ? )
  (  Y14 ? )
  (  Y15 /FPGA_GPIOS/FPGA_BANK0_IO_32 )
  (  Y16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24 )
  (  Y17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 )
  (  Y18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5 )
  (  Y19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_3 )
  (  Y20 +3.3V )
  (  Y21 ? )
  (  Y22 N-000415 )
 )
 ( /4C7BC2A2/4C6B216E 0402  R23 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
  (    2 /DDR_Banks/M0_UDM )
 )
 ( /4C7BC2A2/4C6B216D 0402  R22 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS )
 )
 ( /4C7BC2A2/4C6B216B 0402  R24 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE )
 )
 ( /4C7BC2A2/4C6B1B90 0402  R21 120 {Lib=R}
  (    1 /DDR_Banks/M0_CLK )
  (    2 /DDR_Banks/M0_CLK# )
 )
 ( /4C7BC2A2/4C6A0D58 R_PACK4-0402  RP14 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
  (    5 /DDR_Banks/M0_A3 )
  (    6 /DDR_Banks/M0_A2 )
  (    7 /DDR_Banks/M0_A1 )
  (    8 /DDR_Banks/M0_A0 )
 )
 ( /4C7BC2A2/4C6A0D57 R_PACK4-0402  RP15 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
  (    5 /DDR_Banks/M0_A10 )
  (    6 /DDR_Banks/M0_BA1 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
 )
 ( /4C7BC2A2/4C6A0D56 R_PACK4-0402  RP16 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
  (    6 /DDR_Banks/M0_WE# )
  (    7 /DDR_Banks/M0_LDM )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
 )
 ( /4C7BC2A2/4C6A0D55 R_PACK4-0402  RP17 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
  (    7 /DDR_Banks/M0_A6 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 )
 )
 ( /4C7BC2A2/4C6A0D54 R_PACK4-0402  RP18 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A11 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 )
 )
 ( /4C7BC2A2/4C69FCE8 R_PACK4-0402  RP12 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 )
 )
 ( /4C7BC2A2/4C69FCE7 R_PACK4-0402  RP13 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
  (    6 /DDR_Banks/M0_DQ2 )
  (    7 /DDR_Banks/M0_DQ1 )
  (    8 /DDR_Banks/M0_DQ0 )
 )
 ( /4C7BC2A2/4C69FCE6 R_PACK4-0402  RP11 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
  (    5 /DDR_Banks/M0_DQ11 )
  (    6 /DDR_Banks/M0_DQ10 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
  (    8 /DDR_Banks/M0_DQ8 )
 )
 ( /4C7BC2A2/4C69FC19 R_PACK4-0402  RP10 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 )
 )
 ( /4C7BC2A2/4C69E7DD 0402  R19 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS )
 )
 ( /4C7BC2A2/4C69E92D 0402  R20 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# )
 )
 ( /4C7BC2A2/4C69E7F8 0402  R17 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE )
 )
 ( /4C7BC2A2/4C69E7C2 0402  R18 33 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM )
 )
 ( /4C7BC2A2/4C69E3A6 $noname  RP9 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
  (    2 /DDR_Banks/M1_DQ10 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
 )
 ( /4C7BC2A2/4C69E299 $noname  RP8 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
  (    3 /DDR_Banks/M1_DQ13 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
 )
 ( /4C7BC2A2/4C69DF7A 0402  R16 120 {Lib=R}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# )
  (    2 /DDR_Banks/M1_CLK )
 )
 ( /4C7BC2A2/4C69DC05 $noname  RP7 R_PACK4 {Lib=R_PACK4}
  (    1 /DDR_Banks/M1_A12 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
 )
 ( /4C7BC2A2/4C69DA8A $noname  RP6 R_PACK4 {Lib=R_PACK4}
  (    1 /DDR_Banks/M1_A7 )
  (    2 /DDR_Banks/M1_A6 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A5 )
  (    4 /DDR_Banks/M1_A4 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
 )
 ( /4C7BC2A2/4C69D3A9 $noname  RP5 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
  (    5 /DDR_Banks/M1_DQ3 )
  (    6 /DDR_Banks/M1_DQ2 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0 )
 )
 ( /4C7BC2A2/4C69D3A4 $noname  RP3 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
  (    5 /DDR_Banks/M1_CAS# )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# )
  (    7 /DDR_Banks/M1_LDM )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS )
 )
 ( /4C7BC2A2/4C69D3A3 $noname  RP4 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
  (    8 /DDR_Banks/M1_DQ4 )
 )
 ( /4C7BC2A2/4C69CEE8 $noname  RP2 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 )
  (    6 /DDR_Banks/M1_BA1 )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 )
  (    8 /DDR_Banks/M1_RAS# )
 )
 ( /4C7BC2A2/4C69C6B2 $noname  RP1 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
  (    5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 )
  (    6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
  (    7 /DDR_Banks/M1_A1 )
  (    8 /DDR_Banks/M1_A0 )
 )
 ( /4C716A4D/4CB9E17F $noname  FB2 FILTER {Lib=FILTER}
  (    1 /DBG_PRG/5V_USB )
  (    2 /DBG_PRG/VCC_USB )
 )
 ( /4C716A4D/4CB9DE29 $noname  C146 47pF {Lib=C}
  (    1 N-000226 )
  (    2 GND )
 )
 ( /4C716A4D/4CB9DE25 $noname  C147 47pF {Lib=C}
  (    1 N-000208 )
  (    2 GND )
 )
 ( /4C716A4D/4CB9DDF8 $noname  X1 6MHz {Lib=CRYSTAL}
  (    1 N-000226 )
  (    2 N-000208 )
 )
 ( /4C716A4D/4CB9DDA3 $noname  TP13 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DDA2 $noname  TP14 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DDA1 $noname  TP16 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DDA0 $noname  TP15 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD9C $noname  TP7 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD9B $noname  TP8 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD9A $noname  TP6 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD99 $noname  TP5 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD95 $noname  TP1 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD94 $noname  TP2 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD93 $noname  TP4 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD92 $noname  TP3 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD7D $noname  TP11 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD7C $noname  TP12 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD67 $noname  TP10 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9DD5B $noname  TP9 CONN_1 {Lib=CONN_1}
  (    1 ? )
 )
 ( /4C716A4D/4CB9D9A7 $noname  C150 10uF {Lib=CAPAPOL}
  (    1 /DBG_PRG/VCC_USB )
  (    2 GND )
 )
 ( /4C716A4D/4CB9D313 $noname  R69 1M {Lib=R}
  (    1 /DBG_PRG/USB_CASE_FTDI )
  (    2 GND )
 )
 ( /4C716A4D/4CB9D312 $noname  C145 4.7nF {Lib=C}
  (    1 /DBG_PRG/USB_CASE_FTDI )
  (    2 GND )
 )
 ( /4C716A4D/4CB9D311 ZX62D-B-5P8  J8 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
  (    1 /DBG_PRG/5V_USB )
  (    2 /DBG_PRG/FTDI_USB_DM )
  (    3 /DBG_PRG/FTDI_USB_DP )
  (    4 N-000229 )
  (    5 N-000229 )
  (    6 /DBG_PRG/USB_CASE_FTDI )
  (    7 /DBG_PRG/USB_CASE_FTDI )
  (    8 /DBG_PRG/USB_CASE_FTDI )
  (    9 /DBG_PRG/USB_CASE_FTDI )
 )
 ( /4C716A4D/4CB9CA50 $noname  FB1 FILTER {Lib=FILTER}
  (    1 N-000229 )
  (    2 GND )
 )
 ( /4C716A4D/4CB9C9AD $noname  C148 100nF {Lib=C}
  (    1 /DBG_PRG/5V_USB )
  (    2 GND )
 )
 ( /4C716A4D/4CB9C9A3 $noname  R74 470 {Lib=R}
  (    1 /DBG_PRG/VCC_USB )
  (    2 N-000231 )
 )
 ( /4C716A4D/4CB9C996 $noname  C151 100nF {Lib=C}
  (    1 N-000231 )
  (    2 GND )
 )
 ( /4C716A4D/4CB9C965 $noname  C149 33nF {Lib=C}
  (    1 GND )
  (    2 /DBG_PRG/3.3V_USB )
 )
 ( /4C716A4D/4CB9C8F8 $noname  R71 27 {Lib=R}
  (    1 N-000236 )
  (    2 /DBG_PRG/FTDI_USB_DP )
 )
 ( /4C716A4D/4CB9C8F1 $noname  R70 27 {Lib=R}
  (    1 N-000235 )
  (    2 /DBG_PRG/FTDI_USB_DM )
 )
 ( /4C716A4D/4CB9C8E1 $noname  R73 10K {Lib=R}
  (    1 N-000233 )
  (    2 /DBG_PRG/VCC_USB )
 )
 ( /4C716A4D/4CB9C8D7 $noname  R72 1.5K {Lib=R}
  (    1 N-000234 )
  (    2 N-000236 )
 )
 ( /4C716A4D/4CB9C8AC $noname  R76 10K {Lib=R}
  (    1 +3.3V )
  (    2 N-000237 )
 )
 ( /4C716A4D/4CB9C8A1 $noname  R75 10K {Lib=R}
  (    1 +3.3V )
  (    2 N-000232 )
 )
 ( /4C716A4D/4CB9C4D7 ft2232c-LQFP  IC1 FT2232D {Lib=FT2232C}
  (    1 ? )
  (    2 N-000233 )
  (    3 /DBG_PRG/VCC_USB )
  (    4 /DBG_PRG/VCC_USB )
  (    5 N-000234 )
  (    6 /DBG_PRG/3.3V_USB )
  (    7 N-000236 )
  (    8 N-000235 )
  (    9 GND )
  (   10 N-000232 )
  (   11 ? )
  (   12 ? )
  (   13 ? )
  (   14 /DBG_PRG/3.3V_USB )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 GND )
  (   19 ? )
  (   20 ? )
  (   21 /DBG_PRG/FPGA_TMS )
  (   22 /DBG_PRG/FPGA_TDO )
  (   23 /DBG_PRG/FPGA_TDI )
  (   24 /DBG_PRG/FPGA_TCK )
  (   25 GND )
  (   26 N-000237 )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /DBG_PRG/3.3V_USB )
  (   32 ? )
  (   33 ? )
  (   34 GND )
  (   35 ? )
  (   36 ? )
  (   37 /DBG_PRG/AVR_RST )
  (   38 /PSU/AVR_MISO )
  (   39 /PSU/AVR_MOSI )
  (   40 /DBG_PRG/AVR_SCK )
  (   41 ? )
  (   42 /DBG_PRG/VCC_USB )
  (   43 N-000226 )
  (   44 N-000208 )
  (   45 GND )
  (   46 N-000231 )
  (   47 GND )
  (   48 ? )
 )
 ( /4C69ED5F/4C7FD266 0402  C104 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C69ED5F/4C7FD244 $noname  R57 15K {Lib=R}
  (    1 /DBG_PRG/AVR_RST )
  (    2 +3.3V )
 )
 ( /4C69ED5F/4C7FC13A $noname  R56 R {Lib=R}
  (    1 /PSU/3.3V_EN )
  (    2 /PSU/VIN_DC-DC-3.3 )
 )
 ( /4C69ED5F/4C7FC041 $noname  R58 1M {Lib=R}
  (    1 /PSU/1.2V_EN )
  (    2 /PSU/VIN_DC-DC-1.2 )
 )
 ( /4C69ED5F/4C7D02E3 MLP6  U17 FAN4010 {Lib=FAN4010}
  (    1 +BATT )
  (    2 ? )
  (    3 /PSU/lout_2.5 )
  (    5 GND )
  (    6 ? )
 )
 ( /4C69ED5F/4C7D02E2 1206  R45 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-2.5 )
  (    2 +BATT )
 )
 ( /4C69ED5F/4C7D02E1 0402  R44 R {Lib=R}
  (    1 /PSU/lout_2.5 )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4DAA $noname  R41 160K {Lib=R}
  (    1 /PSU/2.5V_EN )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4D9E $noname  R40 47K {Lib=R}
  (    1 N-000180 )
  (    2 N-000175 )
 )
 ( /4C69ED5F/4C7C4D94 $noname  C100 220pF {Lib=C}
  (    1 N-000175 )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4D8E $noname  C99 22uF {Lib=C}
  (    1 /PSU/VIN_DC-DC-2.5 )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4CF1 0402  C103 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4CF0 1210  L11 2.2uH {Lib=INDUCTOR}
  (    1 +2.5V )
  (    2 /PSU/SW_2.5 )
 )
 ( /4C69ED5F/4C7C4CEF 0402  R43 51K {Lib=R}
  (    1 +2.5V )
  (    2 /PSU/VFB2.5 )
 )
 ( /4C69ED5F/4C7C4CEE 0402  R42 24K {Lib=R}
  (    1 /PSU/VFB2.5 )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4CED 1206  C102 10uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C7C4CEC 0402  C101 22pF {Lib=CAP}
  (    1 +2.5V )
  (    2 /PSU/VFB2.5 )
 )
 ( /4C69ED5F/4C79C99E 0805  C95 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-5.0 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C99C 0402  R35 R {Lib=R}
  (    1 /PSU/lout_5.0 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C99B 1206  R36 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-5.0 )
  (    2 +BATT )
 )
 ( /4C69ED5F/4C79C99A MLP6  U16 FAN4010 {Lib=FAN4010}
  (    1 +BATT )
  (    2 ? )
  (    3 /PSU/lout_5.0 )
  (    5 GND )
  (    6 ? )
 )
 ( /4C69ED5F/4C79C8B2 0402  C98 100nF {Lib=CAP}
  (    1 +5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8B1 0402  R39 1.02M {Lib=R}
  (    1 +5V )
  (    2 /PSU/VFB5.0 )
 )
 ( /4C69ED5F/4C79C8B0 0402  R38 332K {Lib=R}
  (    1 /PSU/VFB5.0 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8AF 1206  C97 10uF {Lib=CAP}
  (    1 +5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8AE 0402  C96 22pF {Lib=CAP}
  (    1 +5V )
  (    2 /PSU/VFB5.0 )
 )
 ( /4C69ED5F/4C79C828 1210  L10 4.7uH {Lib=INDUCTOR}
  (    1 N-000168 )
  (    2 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C79C7C0 0402  R37 1M {Lib=R}
  (    1 /PSU/5V_EN )
  (    2 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C79C65B SOT23_6  U15 A7117 {Lib=A7117}
  (    1 N-000168 )
  (    2 GND )
  (    3 /PSU/VFB5.0 )
  (    4 /PSU/5V_EN )
  (    5 +5V )
  (    6 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C770714 MLP6  U14 FAN4010 {Lib=FAN4010}
  (    1 +BATT )
  (    2 ? )
  (    3 /PSU/Iout_1.2 )
  (    5 GND )
  (    6 /PSU/VIN_DC-DC-1.2 )
 )
 ( /4C69ED5F/4C770713 1206  R34 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-1.2 )
  (    2 +BATT )
 )
 ( /4C69ED5F/4C770712 0402  R33 R {Lib=R}
  (    1 /PSU/Iout_1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C77067B 0402  R31 R {Lib=R}
  (    1 /PSU/lout_3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C77060E 1206  R32 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-3.3 )
  (    2 +BATT )
 )
 ( /4C69ED5F/4C7705B0 MLP6  U13 FAN4010 {Lib=FAN4010}
  (    1 +BATT )
  (    2 ? )
  (    3 /PSU/lout_3.3 )
  (    5 GND )
  (    6 /PSU/VIN_DC-DC-3.3 )
 )
 ( /4C69ED5F/4C6D2FD7 0805  C82 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD6 0402  C83 22pF {Lib=CAP}
  (    1 +1.2V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2FD5 1206  C84 10uF {Lib=CAP}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD3 0402  R27 200K {Lib=R}
  (    1 /PSU/VFB1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD2 0402  R28 200K {Lib=R}
  (    1 +1.2V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2FD1 1210  L9 2.2uH {Lib=INDUCTOR}
  (    1 +1.2V )
  (    2 /PSU/SW_1.2 )
 )
 ( /4C69ED5F/4C6D2FD0 0402  C85 100nF {Lib=CAP}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2F0B 0402  C81 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2E6A 1210  L8 2.2uH {Lib=INDUCTOR}
  (    1 +3.3V )
  (    2 /PSU/SW_3.3 )
 )
 ( /4C69ED5F/4C6D2DDD 0402  R26 900K {Lib=R}
  (    1 +3.3V )
  (    2 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6D2DBC 0402  R25 200K {Lib=R}
  (    1 /PSU/VFB3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2C83 1206  C80 10uF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2C7F 0402  C79 22pF {Lib=CAP}
  (    1 +3.3V )
  (    2 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6D2C7C 0805  C78 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2AE0 SOT23-5  U12 A7108 {Lib=A7108}
  (    1 /PSU/1.2V_EN )
  (    2 GND )
  (    3 /PSU/SW_1.2 )
  (    4 /PSU/VIN_DC-DC-1.2 )
  (    5 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2AA5 SOT23-5  U11 A7108 {Lib=A7108}
  (    1 /PSU/3.3V_EN )
  (    2 GND )
  (    3 /PSU/SW_3.3 )
  (    4 /PSU/VIN_DC-DC-3.3 )
  (    5 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6C9DB9 DFN10  U10 A7130 {Lib=A7130}
  (    1 /PSU/2.5V_EN )
  (    2 GND )
  (    3 /PSU/SW_2.5 )
  (    4 /PSU/SW_2.5 )
  (    5 GND )
  (    6 /PSU/VIN_DC-DC-2.5 )
  (    7 /PSU/VIN_DC-DC-2.5 )
  (    8 /PSU/VIN_DC-DC-2.5 )
  (    9 /PSU/VFB2.5 )
  (   10 N-000180 )
  (  PAD GND )
 )
 ( /4C69ED5F/4C69EE11 MLF20m1  U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF}
  (    1 /DBG_PRG/AVR_SCK )
  (    2 /PSU/Iout_1.2 )
  (    3 /PSU/1.2V_EN )
  (    4 /PSU/lout_3.3 )
  (    5 /PSU/3.3V_EN )
  (    6 ? )
  (    7 ? )
  (    8 GND )
  (    9 +3.3V )
  (   10 ? )
  (   11 /PSU/lout_2.5 )
  (   12 /PSU/2.5V_EN )
  (   13 /DBG_PRG/AVR_RST )
  (   14 /PSU/lout_5.0 )
  (   15 /PSU/5V_EN )
  (   16 /PSU/AVR_MOSI )
  (   17 ? )
  (   18 ? )
  (   19 ? )
  (   20 /PSU/AVR_MISO )
  (  PAD GND )
 )
 ( /4C4227FE/4C6969AB $noname  C75 100nF {Lib=C}
  (    1 GND )
  (    2 +3.3V )
 )
 ( /4C4227FE/4C65D681 0603  C74 1uF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65D67C 0402  C73 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65D661 0402  C72 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65A75D $noname  U8 X25X64MB {Lib=X25X64MB}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO )
  (    2 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
  (    3 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
  (    4 GND )
  (    5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
  (    6 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
  (    7 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 )
  (    8 VCCO2 )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 )
  (    2 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 )
  (    3 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD )
  (    4 +3.3V )
  (    5 /Non_volatile_memories/SD_CLK )
  (    6 GND )
  (    7 /Non_volatile_memories/SD_DAT0 )
  (    8 /Non_volatile_memories/SD_DAT1 )
  ( CASE GND )
  (   CD ? )
  (  COM GND )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
  (    7 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
  (    8 /Non_volatile_memories/NF_RE_N )
  (    9 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N )
  (   10 ? )
  (   11 ? )
  (   12 +3.3V )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 /Non_volatile_memories/NF_CLE )
  (   17 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
  (   18 /Non_volatile_memories/NF_WE_N )
  (   19 +3.3V )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
  (   30 /Non_volatile_memories/NF_D1 )
  (   31 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 )
  (   32 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 +3.3V )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 /Non_volatile_memories/NF_D4 )
  (   42 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
  (   43 /Non_volatile_memories/NF_D6 )
  (   44 /Non_volatile_memories/NF_D7 )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C5F1EDC/4C7D3661 $noname  R53 15k {Lib=R}
  (    1 GND )
  (    2 /USB/USBD_D+ )
 )
 ( /4C5F1EDC/4C7D3660 $noname  R54 15k {Lib=R}
  (    1 GND )
  (    2 /USB/USBD_D- )
 )
 ( /4C5F1EDC/4C7D365F $noname  R55 15k {Lib=R}
  (    1 +3.3V )
  (    2 /USB/USBD_D+ )
 )
 ( /4C5F1EDC/4C7D354D $noname  R49 24 {Lib=R}
  (    1 /USB/USBD_D+ )
  (    2 N-000155 )
 )
 ( /4C5F1EDC/4C7D354C $noname  R50 24 {Lib=R}
  (    1 /USB/USBD_D- )
  (    2 N-000152 )
 )
 ( /4C5F1EDC/4C7D350E $noname  R52 24 {Lib=R}
  (    1 /USB/USBA_D- )
  (    2 N-000154 )
 )
 ( /4C5F1EDC/4C7D3508 $noname  R51 24 {Lib=R}
  (    1 /USB/USBA_D+ )
  (    2 N-000153 )
 )
 ( /4C5F1EDC/4C7D32A3 $noname  R48 15k {Lib=R}
  (    1 +3.3V )
  (    2 /USB/USBA_D+ )
 )
 ( /4C5F1EDC/4C7D3098 $noname  R47 15k {Lib=R}
  (    1 GND )
  (    2 /USB/USBA_D+ )
 )
 ( /4C5F1EDC/4C7D3075 $noname  R46 15k {Lib=R}
  (    1 GND )
  (    2 /USB/USBA_D- )
 )
 ( /4C5F1EDC/4C75F027 ZX62D-B-5P8  J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
  (    1 N-000162 )
  (    2 /USB/USBD_D- )
  (    3 /USB/USBD_D+ )
  (    4 N-000156 )
  (    5 N-000156 )
  (    6 /USB/USB_CASE_DEV )
  (    7 /USB/USB_CASE_DEV )
  (    8 /USB/USB_CASE_DEV )
  (    9 /USB/USB_CASE_DEV )
 )
 ( /4C5F1EDC/4C71BA25 MLF16  U7 MIC2550-MLF {Lib=MIC2550-MLF}
  (    1 /USB/USBD_SPD )
  (    2 /USB/USBD_RCV )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP )
  (    4 /USB/USBD_VM )
  (    6 GND )
  (    7 GND )
  (    9 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
  (   10 N-000152 )
  (   11 N-000155 )
  (   12 +3.3V )
  (   14 +3.3V )
  (   15 +2.5V )
 )
 ( /4C5F1EDC/4C71BA1D MLF16  U6 MIC2550-MLF {Lib=MIC2550-MLF}
  (    1 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD )
  (    2 /USB/USBA_RCV )
  (    3 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP )
  (    4 /USB/USBA_VM )
  (    6 GND )
  (    7 GND )
  (    9 /USB/USBA_OE_N )
  (   10 N-000154 )
  (   11 N-000153 )
  (   12 +3.3V )
  (   14 +3.3V )
  (   15 +2.5V )
 )
 ( /4C5F1EDC/4C6552BE $noname  C35 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552BD 0402  C36 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552BC 0402  C37 100nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B9 $noname  V4 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBD_D- )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B8 $noname  V3 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBD_D+ )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B7 $noname  C38 4.7nF {Lib=C}
  (    1 /USB/USB_CASE_DEV )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B6 $noname  R15 1M {Lib=R}
  (    1 /USB/USB_CASE_DEV )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B1 0603  L7 FB {Lib=INDUCTOR}
  (    1 N-000162 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C63F252 0603  L4 FB {Lib=INDUCTOR}
  (    1 N-000160 )
  (    2 N-000159 )
 )
 ( /4C5F1EDC/4C63F248 0603  L5 FB {Lib=INDUCTOR}
  (    1 N-000158 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D27 $noname  R10 1M {Lib=R}
  (    1 /USB/USB_CASE_HOST )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D1E $noname  C16 4.7nF {Lib=C}
  (    1 /USB/USB_CASE_HOST )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA7 0603  V1 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBA_D+ )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA3 0603  V2 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBA_D- )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2B55 $noname  F1 MICROSMD075F {Lib=MICROSMD075F}
  (    1 N-000160 )
  (    2 +5V )
 )
 ( /4C5F1EDC/4C5F23DD $noname  J5 USB-48204-0001 {Lib=USB-48204-0001}
  (    1 N-000159 )
  (    2 /USB/USBA_D- )
  (    3 /USB/USBA_D+ )
  (    4 N-000158 )
  (   S1 /USB/USB_CASE_HOST )
  (   S2 /USB/USB_CASE_HOST )
  (   S3 /USB/USB_CASE_HOST )
  (   S4 /USB/USB_CASE_HOST )
 )
 ( /4C5F1EDC/4C5F2039 $noname  C15 100nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2037 0402  C14 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2033 $noname  C13 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D8114 $noname  C9 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_PLL1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D810A 0402  L3 FB {Lib=INDUCTOR}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 /Ethernet_Phy/ETH_PLL1.8V )
 )
 ( /4C4320F3/4C5D8104 $noname  C6 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D80F3 0402  L1 FB {Lib=INDUCTOR}
  (    1 +1.8V )
  (    2 /Ethernet_Phy/ETH_A1.8V )
 )
 ( /4C4320F3/4C5D80F0 $noname  C4 100nF {Lib=C}
  (    1 +1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D80ED $noname  C2 1uF {Lib=C}
  (    1 +1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FB7 0402  L2 FB {Lib=INDUCTOR}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/ETH_A3.3V )
 )
 ( /4C4320F3/4C5D7FA7 $noname  C8 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA5 $noname  C7 1uF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA3 $noname  C5 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA1 $noname  C3 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F9F $noname  C1 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F39 $noname  R1 4.7K {Lib=R}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO )
  (    2 +3.3V )
 )
 ( /4C4320F3/4C5D7ECF $noname  R2 6.65K {Lib=R}
  (    1 N-000131 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E43 $noname  C11 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E41 $noname  C10 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DCB $noname  C12 47nF {Lib=C}
  (    1 /Ethernet_Phy/MAG_SHIELD )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DC4 $noname  R9 1M {Lib=R}
  (    1 /Ethernet_Phy/MAG_SHIELD )
  (    2 GND )
 )
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO )
  (    2 /Ethernet_Phy/ETH_MDC )
  (    3 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 )
  (    4 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD2 )
  (    5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 )
  (    6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
  (    7 +3.3V )
  (    8 GND )
  (    9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV )
  (   10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC )
  (   11 /Ethernet_Phy/ETH_RXER )
  (   12 GND )
  (   13 +1.8V )
  (   14 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
  (   15 /Ethernet_Phy/ETH_TXC )
  (   16 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN )
  (   17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
  (   18 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 )
  (   19 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 )
  (   20 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 )
  (   21 /Ethernet_Phy/ETH_COL )
  (   22 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
  (   23 GND )
  (   24 +3.3V )
  (   25 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT )
  (   26 /Ethernet_Phy/ETH_LED0 )
  (   27 /Ethernet_Phy/ETH_LED1 )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /Ethernet_Phy/ETH_A1.8V )
  (   32 /Ethernet_Phy/MAG_RX- )
  (   33 /Ethernet_Phy/MAG_RX+ )
  (   34 ? )
  (   35 GND )
  (   36 GND )
  (   37 N-000131 )
  (   38 /Ethernet_Phy/ETH_A3.3V )
  (   39 GND )
  (   40 /Ethernet_Phy/MAG_TX- )
  (   41 /Ethernet_Phy/MAG_TX+ )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 ? )
  (   46 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK )
  (   47 /Ethernet_Phy/ETH_PLL1.8V )
  (   48 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N )
 )
 ( /4C4320F3/4C5D7AFE $noname  R3 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_TX+ )
 )
 ( /4C4320F3/4C5D7AFC $noname  R4 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_TX- )
 )
 ( /4C4320F3/4C5D7AF9 $noname  R6 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_RX- )
 )
 ( /4C4320F3/4C5D7AF7 $noname  R5 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_RX+ )
 )
 ( /4C4320F3/4C5D71DB $noname  R8 220 {Lib=R}
  (    1 N-000148 )
  (    2 /Ethernet_Phy/ETH_LED1 )
 )
 ( /4C4320F3/4C5D719D $noname  R7 220 {Lib=R}
  (    1 N-000147 )
  (    2 /Ethernet_Phy/ETH_LED0 )
 )
 ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
  (    1 /Ethernet_Phy/MAG_TX+ )
  (    2 /Ethernet_Phy/MAG_TX- )
  (    3 +3.3V )
  (    4 GND )
  (    5 GND )
  (    6 +3.3V )
  (    7 /Ethernet_Phy/MAG_RX+ )
  (    8 /Ethernet_Phy/MAG_RX- )
  (    9 +3.3V )
  (   10 N-000147 )
  (   11 +3.3V )
  (   12 N-000148 )
  (   13 /Ethernet_Phy/MAG_SHIELD )
  (   14 /Ethernet_Phy/MAG_SHIELD )
 )
 ( /4C421DD3/4C609C8E $noname  U3 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0 )
  (    3 +2.5V )
  (    4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
  (    5 /DDR_Banks/M1_DQ2 )
  (    6 GND )
  (    7 /DDR_Banks/M1_DQ3 )
  (    8 /DDR_Banks/M1_DQ4 )
  (    9 +2.5V )
  (   10 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
  (   11 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
  (   12 GND )
  (   13 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M1_LDM )
  (   21 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# )
  (   22 /DDR_Banks/M1_CAS# )
  (   23 /DDR_Banks/M1_RAS# )
  (   24 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# )
  (   25 ? )
  (   26 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 )
  (   27 /DDR_Banks/M1_BA1 )
  (   28 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 )
  (   29 /DDR_Banks/M1_A0 )
  (   30 /DDR_Banks/M1_A1 )
  (   31 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
  (   32 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /DDR_Banks/M1_A4 )
  (   36 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A5 )
  (   37 /DDR_Banks/M1_A6 )
  (   38 /DDR_Banks/M1_A7 )
  (   39 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
  (   40 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
  (   41 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
  (   42 /DDR_Banks/M1_A12 )
  (   43 ? )
  (   44 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# )
  (   45 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE )
  (   46 /DDR_Banks/M1_CLK )
  (   47 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM )
  (   48 GND )
  (   49 /DDR_Banks/M1_VREF )
  (   50 ? )
  (   51 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
  (   55 +2.5V )
  (   56 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 )
  (   57 /DDR_Banks/M1_DQ10 )
  (   58 GND )
  (   59 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
  (   60 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 )
  (   61 +2.5V )
  (   62 /DDR_Banks/M1_DQ13 )
  (   63 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
  (   64 GND )
  (   65 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 )
  (   66 GND )
 )
 ( /4C421DD3/4C65D2A9 0402  C70 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C65D28E 0402  C71 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61D1D4 1206  C34 10uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61D151 1206  C33 10uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA5 0402  C28 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA4 0402  C29 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA3 0402  C31 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA2 0402  C30 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA1 0402  C32 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA0 0603  C27 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF2F 0603  C21 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF27 0402  C26 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF17 0402  C24 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF16 0402  C25 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEF7 0402  C23 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEB9 0402  C22 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CE31 0402  R13 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 /DDR_Banks/M1_VREF )
 )
 ( /4C421DD3/4C61CE30 0402  R14 1K_1% {Lib=R}
  (    1 /DDR_Banks/M1_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CDB5 0402  R12 1K_1% {Lib=R}
  (    1 /DDR_Banks/M0_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CD4A 0402  R11 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_VREF )
 )
 ( /4C421DD3/4C61CCE3 0402  C19 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 /DDR_Banks/M1_VREF )
 )
 ( /4C421DD3/4C61CCE2 0402  C20 100nF {Lib=CAP}
  (    1 /DDR_Banks/M1_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CC96 0402  C18 100nF {Lib=CAP}
  (    1 /DDR_Banks/M0_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CC73 0402  C17 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_VREF )
 )
 ( /4C421DD3/4C609B99 $noname  U2 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_DQ0 )
  (    3 +2.5V )
  (    4 /DDR_Banks/M0_DQ1 )
  (    5 /DDR_Banks/M0_DQ2 )
  (    6 GND )
  (    7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
  (    8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 )
  (    9 +2.5V )
  (   10 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 )
  (   11 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 )
  (   12 GND )
  (   13 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M0_LDM )
  (   21 /DDR_Banks/M0_WE# )
  (   22 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
  (   23 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 )
  (   27 /DDR_Banks/M0_BA1 )
  (   28 /DDR_Banks/M0_A10 )
  (   29 /DDR_Banks/M0_A0 )
  (   30 /DDR_Banks/M0_A1 )
  (   31 /DDR_Banks/M0_A2 )
  (   32 /DDR_Banks/M0_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 )
  (   36 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
  (   37 /DDR_Banks/M0_A6 )
  (   38 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 )
  (   39 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 )
  (   40 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 )
  (   41 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A11 )
  (   42 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 )
  (   43 ? )
  (   44 /DDR_Banks/M0_CLK# )
  (   45 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE )
  (   46 /DDR_Banks/M0_CLK )
  (   47 /DDR_Banks/M0_UDM )
  (   48 GND )
  (   49 /DDR_Banks/M0_VREF )
  (   50 ? )
  (   51 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M0_DQ8 )
  (   55 +2.5V )
  (   56 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
  (   57 /DDR_Banks/M0_DQ10 )
  (   58 GND )
  (   59 /DDR_Banks/M0_DQ11 )
  (   60 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 )
  (   61 +2.5V )
  (   62 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 )
  (   63 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14 )
  (   64 GND )
  (   65 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15 )
  (   66 GND )
 )
)
*
{ Allowed footprints by component:
$component C140
 SM*
 C?
 C1-1
$endlist
$component C142
 SM*
 C?
 C1-1
$endlist
$component C144
 CP*
 SM*
$endlist
$component C143
 SM*
 C?
 C1-1
$endlist
$component C141
 SM*
 C?
 C1-1
$endlist
$component C136
 SM*
 C?
 C1-1
$endlist
$component C138
 SM*
 C?
 C1-1
$endlist
$component C139
 CP*
 SM*
$endlist
$component C137
 SM*
 C?
 C1-1
$endlist
$component C133
 SM*
 C?
 C1-1
$endlist
$component C135
 CP*
 SM*
$endlist
$component C134
 SM*
 C?
 C1-1
$endlist
$component C131
 SM*
 C?
 C1-1
$endlist
$component C132
 CP*
 SM*
$endlist
$component C130
 CP*
 SM*
$endlist
$component C129
 SM*
 C?
 C1-1
$endlist
$component C107
 CP*
 SM*
$endlist
$component C110
 SM*
 C?
 C1-1
$endlist
$component R64
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R63
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C116
 CP*
 SM*
$endlist
$component C113
 SM*
 C?
 C1-1
$endlist
$component C125
 SM*
 C?
 C1-1
$endlist
$component C128
 CP*
 SM*
$endlist
$component R67
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R68
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C121
 SM*
 C?
 C1-1
$endlist
$component C118
 CP*
 SM*
$endlist
$component C117
 CP*
 SM*
$endlist
$component C120
 SM*
 C?
 C1-1
$endlist
$component R66
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R65
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C127
 CP*
 SM*
$endlist
$component C124
 SM*
 C?
 C1-1
$endlist
$component C112
 SM*
 C?
 C1-1
$endlist
$component C115
 CP*
 SM*
$endlist
$component R61
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R62
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C109
 SM*
 C?
 C1-1
$endlist
$component C106
 CP*
 SM*
$endlist
$component C105
 CP*
 SM*
$endlist
$component C108
 SM*
 C?
 C1-1
$endlist
$component R60
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R59
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C114
 CP*
 SM*
$endlist
$component C111
 SM*
 C?
 C1-1
$endlist
$component C94
 SM*
 C?
 C1-1
$endlist
$component C92
 SM*
 C?
 C1-1
$endlist
$component C93
 SM*
 C?
 C1-1
$endlist
$component C91
 SM*
 C?
 C1-1
$endlist
$component C90
 SM*
 C?
 C1-1
$endlist
$component R30
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R29
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C77
 SM*
 C?
 C1-1
$endlist
$component C76
 SM*
 C?
 C1-1
$endlist
$component C66
 SM*
 C?
 C1-1
$endlist
$component C63
 SM*
 C?
 C1-1
$endlist
$component C60
 SM*
 C?
 C1-1
$endlist
$component C57
 SM*
 C?
 C1-1
$endlist
$component C54
 SM*
 C?
 C1-1
$endlist
$component C69
 SM*
 C?
 C1-1
$endlist
$component C67
 SM*
 C?
 C1-1
$endlist
$component C64
 SM*
 C?
 C1-1
$endlist
$component C61
 SM*
 C?
 C1-1
$endlist
$component C58
 SM*
 C?
 C1-1
$endlist
$component C55
 SM*
 C?
 C1-1
$endlist
$component C68
 SM*
 C?
 C1-1
$endlist
$component C65
 SM*
 C?
 C1-1
$endlist
$component C62
 SM*
 C?
 C1-1
$endlist
$component C59
 SM*
 C?
 C1-1
$endlist
$component C56
 SM*
 C?
 C1-1
$endlist
$component C50
 SM*
 C?
 C1-1
$endlist
$component C47
 SM*
 C?
 C1-1
$endlist
$component C44
 SM*
 C?
 C1-1
$endlist
$component C41
 SM*
 C?
 C1-1
$endlist
$component C53
 SM*
 C?
 C1-1
$endlist
$component C51
 SM*
 C?
 C1-1
$endlist
$component C49
 SM*
 C?
 C1-1
$endlist
$component C46
 SM*
 C?
 C1-1
$endlist
$component C52
 SM*
 C?
 C1-1
$endlist
$component C43
 SM*
 C?
 C1-1
$endlist
$component C40
 SM*
 C?
 C1-1
$endlist
$component C48
 SM*
 C?
 C1-1
$endlist
$component C45
 SM*
 C?
 C1-1
$endlist
$component C42
 SM*
 C?
 C1-1
$endlist
$component C39
 SM*
 C?
 C1-1
$endlist
$component R23
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R22
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R24
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R21
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R19
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R20
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R17
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R18
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R16
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C146
 SM*
 C?
 C1-1
$endlist
$component C147
 SM*
 C?
 C1-1
$endlist
$component C150
 CP*
 SM*
$endlist
$component R69
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C145
 SM*
 C?
 C1-1
$endlist
$component C148
 SM*
 C?
 C1-1
$endlist
$component R74
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C151
 SM*
 C?
 C1-1
$endlist
$component C149
 SM*
 C?
 C1-1
$endlist
$component R71
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R70
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R73
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R72
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R76
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R75
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C104
 SM*
 C?
 C1-1
$endlist
$component R57
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R56
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R58
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R45
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R44
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R41
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R40
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C100
 SM*
 C?
 C1-1
$endlist
$component C99
 SM*
 C?
 C1-1
$endlist
$component C103
 SM*
 C?
 C1-1
$endlist
$component R43
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R42
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C102
 SM*
 C?
 C1-1
$endlist
$component C101
 SM*
 C?
 C1-1
$endlist
$component C95
 SM*
 C?
 C1-1
$endlist
$component R35
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R36
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C98
 SM*
 C?
 C1-1
$endlist
$component R39
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R38
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C97
 SM*
 C?
 C1-1
$endlist
$component C96
 SM*
 C?
 C1-1
$endlist
$component R37
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R34
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R33
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R31
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R32
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C82
 SM*
 C?
 C1-1
$endlist
$component C83
 SM*
 C?
 C1-1
$endlist
$component C84
 SM*
 C?
 C1-1
$endlist
$component R27
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R28
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C85
 SM*
 C?
 C1-1
$endlist
$component C81
 SM*
 C?
 C1-1
$endlist
$component R26
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R25
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C80
 SM*
 C?
 C1-1
$endlist
$component C79
 SM*
 C?
 C1-1
$endlist
$component C78
 SM*
 C?
 C1-1
$endlist
$component C75
 SM*
 C?
 C1-1
$endlist
$component C74
 SM*
 C?
 C1-1
$endlist
$component C73
 SM*
 C?
 C1-1
$endlist
$component C72
 SM*
 C?
 C1-1
$endlist
$component R53
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R54
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R55
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R49
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R50
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R52
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R51
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R48
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R47
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R46
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C35
 SM*
 C?
 C1-1
$endlist
$component C36
 SM*
 C?
 C1-1
$endlist
$component C37
 SM*
 C?
 C1-1
$endlist
$component C38
 SM*
 C?
 C1-1
$endlist
$component R15
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R10
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C16
 SM*
 C?
 C1-1
$endlist
$component C15
 SM*
 C?
 C1-1
$endlist
$component C14
 SM*
 C?
 C1-1
$endlist
$component C13
 SM*
 C?
 C1-1
$endlist
$component C9
 SM*
 C?
 C1-1
$endlist
$component C6
 SM*
 C?
 C1-1
$endlist
$component C4
 SM*
 C?
 C1-1
$endlist
$component C2
 SM*
 C?
 C1-1
$endlist
$component C8
 SM*
 C?
 C1-1
$endlist
$component C7
 SM*
 C?
 C1-1
$endlist
$component C5
 SM*
 C?
 C1-1
$endlist
$component C3
 SM*
 C?
 C1-1
$endlist
$component C1
 SM*
 C?
 C1-1
$endlist
$component R1
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R2
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C11
 SM*
 C?
 C1-1
$endlist
$component C10
 SM*
 C?
 C1-1
$endlist
$component C12
 SM*
 C?
 C1-1
$endlist
$component R9
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R3
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R4
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R6
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R5
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R8
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R7
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C70
 SM*
 C?
 C1-1
$endlist
$component C71
 SM*
 C?
 C1-1
$endlist
$component C34
 SM*
 C?
 C1-1
$endlist
$component C33
 SM*
 C?
 C1-1
$endlist
$component C28
 SM*
 C?
 C1-1
$endlist
$component C29
 SM*
 C?
 C1-1
$endlist
$component C31
 SM*
 C?
 C1-1
$endlist
$component C30
 SM*
 C?
 C1-1
$endlist
$component C32
 SM*
 C?
 C1-1
$endlist
$component C27
 SM*
 C?
 C1-1
$endlist
$component C21
 SM*
 C?
 C1-1
$endlist
$component C26
 SM*
 C?
 C1-1
$endlist
$component C24
 SM*
 C?
 C1-1
$endlist
$component C25
 SM*
 C?
 C1-1
$endlist
$component C23
 SM*
 C?
 C1-1
$endlist
$component C22
 SM*
 C?
 C1-1
$endlist
$component R13
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R14
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R12
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R11
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C19
 SM*
 C?
 C1-1
$endlist
$component C20
 SM*
 C?
 C1-1
$endlist
$component C18
 SM*
 C?
 C1-1
$endlist
$component C17
 SM*
 C?
 C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/DBG_PRG/FPGA_TDO" "FPGA_TDO"
 U1 A19
 IC1 22
Net 2 "/DBG_PRG/FPGA_TDI" "FPGA_TDI"
 U1 E18
 IC1 23
Net 3 "/DBG_PRG/FPGA_TMS" "FPGA_TMS"
 IC1 21
 U1 C18
Net 4 "/DBG_PRG/FPGA_TCK" "FPGA_TCK"
 U1 G15
 IC1 24
Net 5 "/DBG_PRG/AVR_SCK" "AVR_SCK"
 IC1 40
 U9 1
Net 6 "/DDR Banks/M0_UDM" "M0_UDM"
 U2 47
 R23 2
Net 7 "/FPGA Port 1, Port 3 DDR, USB/M0_LDQS" "M0_LDQS"
 RP16 8
 U2 16
Net 8 "/DDR Banks/M0_CLK" "M0_CLK"
 U1 H4
 R21 1
 U2 46
Net 9 "/DDR Banks/M0_CLK#" "M0_CLK#"
 R21 2
 U2 44
 U1 H3
Net 10 "GND" "GND"
 C6 2
 C4 2
 C2 2
 J1 CASE
 C1 2
 U1 G18
 U4 23
 U4 44
 U4 35
 U4 36
 U4 8
 U4 12
 U1 AB22
 U1 AA9
 U1 W19
 U1 R18
 R2 2
 C11 2
 C10 2
 C12 2
 R9 2
 C8 2
 C7 2
 C5 2
 C3 2
 U1 L18
 C9 2
 U3 58
 C132 2
 U1 J9
 C27 2
 C21 2
 C26 2
 C24 2
 C25 2
 C23 2
 C33 2
 C28 2
 C29 2
 C31 2
 U2 6
 U1 D4
 U1 U2
 U1 N2
 C22 2
 R14 2
 R12 2
 C20 2
 C18 2
 U1 J2
 U2 64
 U1 E2
 U1 A1
 U2 66
 U2 12
 C129 2
 U2 52
 C130 2
 U2 24
 U2 34
 C70 2
 C71 2
 C34 2
 U2 48
 U2 58
 U1 M14
 U1 K14
 U1 N13
 U1 L13
 U1 J13
 U24 44
 U24 35
 U24 39
 C30 2
 C32 2
 C131 2
 C134 2
 C135 2
 C133 2
 U1 B9
 C137 2
 C139 2
 C138 2
 U1 W7
 U1 U7
 U1 H7
 U1 E7
 U1 R5
 U1 L5
 U1 G5
 U1 B5
 U1 V4
 C136 2
 C141 2
 C143 2
 J1 CASE
 J1 CASE
 J1 COM
 J1 6
 U5 13
 U5 36
 C72 2
 C73 2
 C74 2
 C144 2
 C142 2
 U8 4
 C140 2
 C75 1
 IC1 9
 IC1 18
 IC1 47
 IC1 45
 IC1 25
 IC1 34
 C145 2
 R69 2
 C147 2
 C146 2
 C77 2
 C76 2
 C94 2
 C150 2
 C149 1
 C151 2
 FB1 2
 C148 2
 U10 5
 R41 2
 R31 2
 C100 2
 C99 2
 U13 5
 C104 2
 R33 2
 U14 5
 R25 2
 C81 2
 U9 PAD
 C80 2
 C78 2
 U10 2
 U11 2
 U12 2
 U9 8
 U17 5
 U10 PAD
 R44 2
 C103 2
 R42 2
 C102 2
 U16 5
 R35 2
 C95 2
 C85 2
 R27 2
 C84 2
 C98 2
 R38 2
 C82 2
 C97 2
 U15 2
 U7 7
 R47 1
 R46 1
 C35 2
 U6 6
 U6 7
 C50 2
 C56 2
 C59 2
 C62 2
 C37 2
 V4 2
 V3 2
 C38 2
 R15 2
 V2 2
 C57 2
 C15 2
 C14 2
 C60 2
 C13 2
 R10 2
 C63 2
 C16 2
 V1 2
 C66 2
 U7 6
 C68 2
 C55 2
 C58 2
 C61 2
 J4 4
 J4 5
 U4 39
 U1 AA17
 U1 AA13
 C65 2
 R53 1
 R54 1
 C90 2
 C91 2
 C93 2
 C92 2
 C40 2
 C43 2
 C52 2
 C39 2
 C42 2
 C45 2
 C48 2
 C64 2
 C67 2
 C69 2
 C54 2
 L7 2
 L5 2
 C36 2
 C46 2
 C49 2
 C51 2
 C53 2
 C41 2
 C44 2
 C47 2
 U1 E21
 U24 30
 U1 N11
 U1 N15
 U1 L11
 U1 AA5
 U1 P14
 U1 V14
 U1 E15
 U1 J15
 C121 2
 C118 2
 C117 2
 C120 2
 R66 2
 C127 2
 U22 2
 U1 N17
 U1 W16
 U1 B17
 U3 66
 U3 48
 U3 12
 U1 V10
 U1 P10
 U1 M10
 U1 K10
 U1 N9
 U1 L9
 U1 M12
 U3 6
 U1 AB1
 U1 U21
 U1 N21
 U1 E11
 U1 J21
 U1 J11
 U3 52
 U3 34
 U1 K12
 U3 64
 C110 2
 R64 2
 C116 2
 U24 6
 U1 D18
 U1 P12
 R60 2
 C114 2
 U18 2
 U1 A22
 U1 B13
 U19 2
 C115 2
 R62 2
 U20 2
 U23 2
 C128 2
 R68 2
 C106 2
 C105 2
 C108 2
 C107 2
 C109 2
Net 11 "/FPGA Port 1, Port 3 DDR, USB/M1_CLK#" "M1_CLK#"
 U1 J19
 R16 1
 U3 44
Net 12 "/DDR Banks/M1_CLK" "M1_CLK"
 U3 46
 R16 2
 U1 H20
Net 13 "/FPGA Port 1, Port 3 DDR, USB/M1_CKE" "M1_CKE"
 R17 2
 U3 45
Net 14 "/DDR Banks/M1_CAS#" "M1_CAS#"
 U3 22
 RP3 5
Net 15 "/DDR Banks/M0_LDM" "M0_LDM"
 RP16 7
 U2 20
Net 16 "/FPGA Port 1, Port 3 DDR, USB/M0_UDQS" "M0_UDQS"
 U2 51
 R22 2
Net 17 "/FPGA Port 1, Port 3 DDR, USB/M1_UDQS" "M1_UDQS"
 U3 51
 R19 2
Net 18 "/DDR Banks/M1_LDM" "M1_LDM"
 U3 20
 RP3 7
Net 19 "/FPGA Port 1, Port 3 DDR, USB/M1_LDQS" "M1_LDQS"
 RP3 8
 U3 16
Net 20 "/FPGA Port 1, Port 3 DDR, USB/M1_UDM" "M1_UDM"
 U3 47
 R18 2
Net 21 "/FPGA Port 1, Port 3 DDR, USB/M1_CS#" "M1_CS#"
 R20 2
 U3 24
Net 22 "/FPGA, Port0, Port2, PROG IF/NF_ALE" "NF_ALE"
 U5 17
 U1 A14
Net 23 "/Non volatile memories/NF_CLE" "NF_CLE"
 U1 B14
 U5 16
Net 24 "/Non volatile memories/NF_WE_N" "NF_WE_N"
 U1 C14
 U5 18
Net 25 "/FPGA, Port0, Port2, PROG IF/NF_CS1_N" "NF_CS1_N"
 U5 9
 U1 D15
Net 26 "/Non volatile memories/NF_RE_N" "NF_RE_N"
 U5 8
 U1 C15
Net 27 "/FPGA, Port0, Port2, PROG IF/NF_RNB" "NF_RNB"
 U5 7
 U5 6
 U1 A15
Net 28 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK"
 U8 6
 U1 AA21
Net 29 "/FPGA, Port0, Port2, PROG IF/PROG_CSO" "PROG_CSO"
 U1 T5
 U8 1
Net 30 "/FPGA Port 1, Port 3 DDR, USB/USBA_SPD" "USBA_SPD"
 U6 1
 U1 F16
Net 31 "/USB/USBA_OE_N" "USBA_OE_N"
 U1 C19
 U6 9
Net 32 "/USB/USBA_RCV" "USBA_RCV"
 U6 2
 U1 F17
Net 33 "/FPGA Port 1, Port 3 DDR, USB/USBA_VP" "USBA_VP"
 U1 D19
 U6 3
Net 34 "/PSU/AVR_MISO" "AVR_MISO"
 U9 20
 IC1 38
Net 35 "/PSU/AVR_MOSI" "AVR_MOSI"
 U9 16
 IC1 39
Net 36 "/DBG_PRG/AVR_RST" "AVR_RST"
 IC1 37
 U9 13
 R57 1
Net 37 "/FPGA, Port0, Port2, PROG IF/SD_CMD" "SD_CMD"
 J1 3
 U1 C16
Net 38 "/Non volatile memories/SD_CLK" "SD_CLK"
 U1 A17
 J1 5
Net 39 "/FPGA, Port0, Port2, PROG IF/ETH_TXEN" "ETH_TXEN"
 U4 16
 U1 D9
Net 40 "/FPGA, Port0, Port2, PROG IF/ETH_TXER" "ETH_TXER"
 U4 14
 U1 D8
Net 41 "/FPGA, Port0, Port2, PROG IF/ETH_CLK" "ETH_CLK"
 U4 46
 U1 A4
Net 42 "/FPGA, Port0, Port2, PROG IF/ETH_INT" "ETH_INT"
 U1 A10
 U4 25
Net 43 "/DDR Banks/M0_WE#" "M0_WE#"
 U2 21
 RP16 6
Net 44 "/FPGA Port 1, Port 3 DDR, USB/M0_RAS#" "M0_RAS#"
 RP15 8
 U2 23
Net 45 "/DDR Banks/M1_RAS#" "M1_RAS#"
 U3 23
 RP2 8
Net 46 "/FPGA Port 1, Port 3 DDR, USB/M1_WE#" "M1_WE#"
 RP3 6
 U3 21
Net 47 "/FPGA Port 1, Port 3 DDR, USB/M0_CAS#" "M0_CAS#"
 U2 22
 RP16 5
Net 48 "/FPGA Port 1, Port 3 DDR, USB/M0_CKE" "M0_CKE"
 R24 2
 U2 45
Net 49 "/USB/USBA_VM" "USBA_VM"
 U1 D20
 U6 4
Net 50 "/USB/USBD_SPD" "USBD_SPD"
 U1 B20
 U7 1
Net 51 "/FPGA Port 1, Port 3 DDR, USB/USBD_OE_N" "USBD_OE_N"
 U1 A21
 U7 9
Net 52 "/USB/USBD_RCV" "USBD_RCV"
 U7 2
 U1 A20
Net 53 "/FPGA Port 1, Port 3 DDR, USB/USBD_VP" "USBD_VP"
 U7 3
 U1 B21
Net 54 "/USB/USBD_VM" "USBD_VM"
 U7 4
 U1 B22
Net 55 "/FPGA, Port0, Port2, PROG IF/ETH_RXC" "ETH_RXC"
 U1 A7
 U4 10
Net 56 "/FPGA, Port0, Port2, PROG IF/ETH_RESET_N" "ETH_RESET_N"
 U4 48
 U1 C7
Net 57 "/FPGA, Port0, Port2, PROG IF/ETH_CRS" "ETH_CRS"
 U1 B10
 U4 22
Net 58 "/Ethernet Phy/ETH_COL" "ETH_COL"
 U1 A9
 U4 21
Net 59 "/FPGA, Port0, Port2, PROG IF/ETH_MDIO" "ETH_MDIO"
 U1 D6
 R1 1
 U4 1
Net 60 "/Ethernet Phy/ETH_MDC" "ETH_MDC"
 U4 2
 U1 D7
Net 61 "/FPGA, Port0, Port2, PROG IF/ETH_RXDV" "ETH_RXDV"
 U4 9
 U1 A6
Net 62 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
 U4 11
 U1 B8
Net 63 "/Ethernet Phy/ETH_TXC" "ETH_TXC"
 U4 15
 U1 C8
Net 64 "/FPGA, Port0, Port2, PROG IF/IS_STANDBY" "IS_STANDBY"
 U24 22
 U1 Y5
Net 65 "/Image Sensor/IS_TRIGGER" "IS_TRIGGER"
 U24 27
 U1 Y3
Net 66 "/Image Sensor/IS_PIXEL" "IS_PIXEL"
 U24 13
 U1 AB6
Net 67 "/FPGA, Port0, Port2, PROG IF/IS_FRAME" "IS_FRAME"
 U24 28
 U1 AB2
Net 68 "+2.8_VDDIO" "+2.8_VDDIO"
 C124 1
 C143 1
 C141 1
 U24 12
 C140 1
 C142 1
 C144 1
 U24 18
 R65 1
 U22 6
 C127 1
Net 69 "+2.8_VAAPIX" "+2.8_VAAPIX"
 C132 1
 C112 1
 C115 1
 U24 37
 C131 1
 U24 38
 U19 6
 R61 1
Net 70 "/FPGA, Port0, Port2, PROG IF/IS_SDA" "IS_SDA"
 U1 AA6
 U24 16
Net 71 "/FPGA, Port0, Port2, PROG IF/IS_I2C_ADDR" "IS_I2C_ADDR"
 U1 AB4
 U24 24
Net 72 "/FPGA, Port0, Port2, PROG IF/IS_RESET_N" "IS_RESET_N"
 U1 AB5
 U24 17
Net 73 "/Image Sensor/IS_LINE" "IS_LINE"
 U1 AA2
 U24 29
Net 74 "/FPGA, Port0, Port2, PROG IF/IS_FLASH" "IS_FLASH"
 U1 AB3
 U24 26
Net 75 "/FPGA, Port0, Port2, PROG IF/IS_TEST" "IS_TEST"
 U24 25
 U1 AA4
Net 76 "/FPGA, Port0, Port2, PROG IF/IS_OE_N" "IS_OE_N"
 U24 23
 U1 Y4
Net 77 "/Image Sensor/IS_EXTCLK" "IS_EXTCLK"
 U24 5
 U1 W12
Net 78 "/Image Sensor/IS_SCL" "IS_SCL"
 U1 Y12
 U24 15
Net 79 "+2.8_VAA" "+2.8_VAA"
 R59 1
 C133 1
 U24 40
 U24 34
 U18 6
 C134 1
 U24 36
 C111 1
 C114 1
 C135 1
Net 80 "/Image Sensor/+1.8_VDD" "+1.8_VDD"
 C139 1
 C137 1
 U24 14
 C136 1
 C138 1
 R63 1
 U24 19
 C116 1
 C113 1
 U20 6
Net 81 "+2.8_VDDPLL" "+2.8_VDDPLL"
 R67 1
 C128 1
 C129 1
 C125 1
 U23 6
 C130 1
 U24 4
Net 86 "+2.5V" "+2.5V"
 C52 1
 C43 1
 U1 R12
 C40 1
 C94 1
 U1 E19
 U1 L16
 U1 J18
 U1 J5
 U1 N5
 U1 U5
 U1 L7
 U1 F4
 U1 F6
 C101 1
 C102 1
 U1 C21
 U1 G21
 U1 L21
 U1 R21
 U1 W21
 U1 N18
 C77 1
 R43 1
 L11 1
 U1 U18
 C103 1
 U1 F11
 U1 G12
 U2 33
 U2 61
 U2 18
 U2 3
 U1 U11
 U1 M15
 U1 H9
 U1 K15
 U1 H15
 C34 1
 C71 1
 C70 1
 U2 15
 U3 55
 U3 1
 U3 61
 C19 1
 R11 1
 U3 9
 R13 1
 U3 3
 U1 R10
 U2 9
 C17 1
 U2 1
 U3 15
 U3 33
 U2 55
 U3 18
 C63 1
 C60 1
 C57 1
 C15 1
 C66 1
 U1 V6
 U1 R2
 U1 W2
 U1 C2
 U1 G2
 U1 L2
 C53 1
 U1 R6
 C51 1
 C49 1
 C46 1
 C37 1
 C54 1
 U1 N8
 U1 L8
 C68 1
 C29 1
 C28 1
 C33 1
 C22 1
 C23 1
 C25 1
 C24 1
 C26 1
 C21 1
 U1 D16
 U7 15
 U6 15
 C56 1
 C59 1
 C27 1
 C65 1
 C31 1
 C62 1
 C30 1
 C32 1
Net 89 "/DDR Banks/M0_VREF" "M0_VREF"
 U2 49
 R12 1
 R11 2
 C17 2
 C18 1
Net 90 "/DDR Banks/M1_VREF" "M1_VREF"
 U3 49
 R13 2
 R14 1
 C20 1
 C19 2
Net 99 "VCCO2" "VCCO2"
 U1 V8
 U1 T9
 U1 W5
 U1 V16
 U1 AA7
 U1 V12
 U1 T13
 U1 AA3
 C58 1
 C55 1
 C69 1
 C67 1
 C64 1
 C61 1
 U1 AA19
 U1 AA15
 U1 AA11
 U8 8
Net 100 "+3.3V" "+3.3V"
 U1 E9
 U1 B19
 U1 E17
 U1 B15
 U1 G14
 U1 B4
 U1 B7
 C80 1
 R75 1
 R76 1
 C79 1
 U1 Y20
 U1 E13
 C44 1
 C41 1
 C91 1
 C90 1
 R30 1
 U1 G10
 C104 1
 U1 B11
 R57 2
 R29 1
 C50 1
 C47 1
 R5 1
 R6 1
 R4 1
 R3 1
 J4 9
 J4 6
 J4 3
 U4 7
 U4 24
 C1 1
 C3 1
 C5 1
 L2 1
 C10 1
 C11 1
 R1 2
 J4 11
 R55 1
 U6 14
 U6 12
 C36 1
 C35 1
 R48 1
 U7 14
 U7 12
 C13 1
 C14 1
 C73 1
 C72 1
 U9 9
 C81 1
 J1 4
 U5 12
 U5 19
 U5 37
 C74 1
 R26 1
 L8 1
 C75 2
Net 131 "" ""
 U4 37
 R2 1
Net 132 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
 C6 1
 L1 2
 U4 31
 L3 1
Net 133 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
 L3 2
 C9 1
 U4 47
Net 136 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD"
 R9 1
 C12 1
 J4 14
 J4 13
Net 137 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
 L2 2
 U4 38
 C8 1
 C7 1
Net 138 "+1.8V" "+1.8V"
 C2 1
 C4 1
 L1 1
 U4 13
Net 140 "/Ethernet Phy/MAG_RX-" "MAG_RX-"
 R6 2
 U4 32
 J4 8
Net 142 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
 U4 27
 R8 2
Net 146 "/Ethernet Phy/MAG_TX-" "MAG_TX-"
 J4 2
 U4 40
 R4 2
Net 147 "" ""
 J4 10
 R7 1
Net 148 "" ""
 R8 1
 J4 12
Net 149 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
 U4 26
 R7 2
Net 150 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
 R3 2
 J4 1
 U4 41
Net 151 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
 R5 2
 J4 7
 U4 33
Net 152 "" ""
 U7 10
 R50 2
Net 153 "" ""
 U6 11
 R51 2
Net 154 "" ""
 R52 2
 U6 10
Net 155 "" ""
 R49 2
 U7 11
Net 156 "" ""
 J7 4
 J7 5
Net 157 "/USB/USBD_D+" "USBD_D+"
 R49 1
 J7 3
 V3 1
 R55 2
 V3 1
 R53 2
Net 158 "" ""
 L5 1
 J5 4
Net 159 "" ""
 L4 2
 J5 1
Net 160 "" ""
 L4 1
 F1 1
Net 161 "+5V" "+5V"
 C98 1
 C97 1
 F1 2
 R39 1
 U15 5
 C96 1
Net 162 "" ""
 J7 1
 L7 1
Net 163 "/USB/USBD_D-" "USBD_D-"
 R54 2
 J7 2
 V4 1
 V4 1
 R50 1
Net 164 "/USB/USBA_D-" "USBA_D-"
 R46 2
 V2 1
 R52 1
 J5 2
 V2 1
Net 165 "/USB/USBA_D+" "USBA_D+"
 J5 3
 V1 1
 V1 1
 R51 1
 R47 2
 R48 2
Net 166 "/USB/USB_CASE_HOST" "USB_CASE_HOST"
 C16 1
 R10 1
 J5 S4
 J5 S3
 J5 S2
 J5 S1
Net 167 "/USB/USB_CASE_DEV" "USB_CASE_DEV"
 J7 9
 J7 8
 J7 7
 J7 6
 R15 1
 C38 1
Net 168 "" ""
 L10 1
 U15 1
Net 169 "/PSU/1.2V_EN" "1.2V_EN"
 U9 3
 R58 1
 U12 1
Net 170 "/PSU/VFB2.5" "VFB2.5"
 U10 9
 R43 2
 R42 1
 C101 2
Net 171 "/PSU/VFB3.3" "VFB3.3"
 C79 2
 U11 5
 R26 2
 R25 1
Net 172 "/PSU/3.3V_EN" "3.3V_EN"
 U11 1
 R56 1
 U9 5
Net 173 "/PSU/lout_5.0" "lout_5.0"
 R35 1
 U9 14
 U16 3
Net 174 "/PSU/lout_2.5" "lout_2.5"
 R44 1
 U17 3
 U9 11
Net 175 "" ""
 C100 1
 R40 2
Net 176 "/PSU/Iout_1.2" "Iout_1.2"
 R33 1
 U9 2
 U14 3
Net 177 "/PSU/5V_EN" "5V_EN"
 R37 1
 U9 15
 U15 4
Net 178 "/PSU/2.5V_EN" "2.5V_EN"
 R41 1
 U9 12
 U10 1
Net 179 "+BATT" "+BATT"
 U17 1
 U14 1
 R34 2
 U13 1
 R32 2
 R36 2
 U16 1
 R45 2
Net 180 "" ""
 R40 1
 U10 10
Net 181 "/PSU/SW_2.5" "SW_2.5"
 L11 2
 U10 3
 U10 4
Net 182 "/PSU/lout_3.3" "lout_3.3"
 U13 3
 U9 4
 R31 1
Net 183 "/PSU/SW_3.3" "SW_3.3"
 U11 3
 L8 2
Net 184 "/PSU/VFB1.2" "VFB1.2"
 C83 2
 R27 1
 R28 2
 U12 5
Net 185 "+1.2V" "+1.2V"
 C76 1
 C48 1
 C92 1
 C45 1
 C42 1
 C39 1
 C93 1
 U1 P13
 U1 J14
 U1 L14
 U1 P11
 U1 M11
 U1 K11
 U1 J8
 U1 L12
 U1 J12
 U1 N12
 U1 K9
 U1 M9
 U1 P9
 U1 J10
 U1 L10
 U1 N10
 U1 N14
 U1 R14
 U1 K13
 U1 M13
 L9 1
 C85 1
 C83 1
 C84 1
 R28 1
Net 186 "/PSU/VFB5.0" "VFB5.0"
 U15 3
 C96 2
 R38 1
 R39 2
Net 187 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2"
 C82 1
 U12 4
 R58 2
 R34 1
 U14 6
Net 188 "/PSU/SW_1.2" "SW_1.2"
 L9 2
 U12 3
Net 191 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3"
 U13 6
 U11 4
 R32 1
 C78 1
 R56 2
Net 202 "/PSU/VIN_DC-DC-2.5" "VIN_DC-DC-2.5"
 U17 6
 R45 1
 U10 8
 U10 6
 U10 7
 C99 1
Net 205 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0"
 L10 2
 R37 2
 U16 6
 U15 6
 C95 1
 R36 1
Net 206 "/DBG_PRG/5V_USB" "5V_USB"
 J8 1
 C148 1
 FB2 1
Net 207 "/DBG_PRG/FTDI_USB_DP" "FTDI_USB_DP"
 J8 3
 R71 2
Net 208 "" ""
 IC1 44
 X1 2
 C147 1
Net 226 "" ""
 C146 1
 X1 1
 IC1 43
Net 227 "/DBG_PRG/VCC_USB" "VCC_USB"
 IC1 3
 R73 2
 C150 1
 FB2 2
 R74 1
 IC1 4
 IC1 42
Net 228 "/DBG_PRG/USB_CASE_FTDI" "USB_CASE_FTDI"
 C145 1
 J8 6
 J8 7
 J8 8
 J8 9
 R69 1
Net 229 "" ""
 J8 5
 J8 4
 FB1 1
Net 230 "/DBG_PRG/FTDI_USB_DM" "FTDI_USB_DM"
 J8 2
 R70 2
Net 231 "" ""
 C151 1
 R74 2
 IC1 46
Net 232 "" ""
 IC1 10
 R75 2
Net 233 "" ""
 R73 1
 IC1 2
Net 234 "" ""
 IC1 5
 R72 1
Net 235 "" ""
 IC1 8
 R70 1
Net 236 "" ""
 R72 2
 IC1 7
 R71 1
Net 237 "" ""
 IC1 26
 R76 2
Net 238 "/DBG_PRG/3.3V_USB" "3.3V_USB"
 IC1 6
 IC1 14
 C149 2
 IC1 31
Net 257 "/FPGA Port 1, Port 3 DDR, USB/R_M1_RAS#" "R_M1_RAS#"
 U1 H21
 RP2 1
Net 258 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A2" "R_M1_A2"
 RP1 3
 U1 E22
Net 259 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A3" "R_M1_A3"
 RP1 4
 U1 G20
Net 260 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A1" "R_M1_A1"
 U1 F22
 RP1 2
Net 261 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A0" "R_M1_A0"
 U1 F21
 RP1 1
Net 262 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A10" "R_M1_A10"
 RP2 4
 U1 G19
Net 263 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA1" "R_M1_BA1"
 U1 K17
 RP2 3
Net 264 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA0" "R_M1_BA0"
 RP2 2
 U1 J17
Net 265 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ15" "R_M0_DQ15"
 RP10 4
 U1 V1
Net 266 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ14" "R_M0_DQ14"
 U1 V2
 RP10 3
Net 267 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ13" "R_M0_DQ13"
 U1 U1
 RP10 2
Net 268 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ12" "R_M0_DQ12"
 U1 U3
 RP10 1
Net 269 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ10" "R_M0_DQ10"
 RP11 3
 U1 R3
Net 270 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CKE" "R_M1_CKE"
 U1 D21
 R17 1
Net 271 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CAS#" "R_M1_CAS#"
 RP3 4
 U1 H22
Net 272 "/FPGA Port 1, Port 3 DDR, USB/R_M1_WE#" "R_M1_WE#"
 U1 H19
 RP3 3
Net 273 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDM" "R_M1_LDM"
 U1 L19
 RP3 2
Net 274 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDQS" "R_M1_LDQS"
 RP3 1
 U1 L20
Net 275 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A12" "R_M1_A12"
 RP7 8
 U1 D22
Net 276 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A11" "R_M1_A11"
 U1 F19
 RP7 7
Net 277 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A9" "R_M1_A9"
 U1 C22
 RP7 6
Net 278 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A8" "R_M1_A8"
 RP7 5
 U1 C20
Net 279 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A7" "R_M1_A7"
 RP6 8
 U1 E20
Net 280 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A6" "R_M1_A6"
 U1 K19
 RP6 7
Net 281 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A5" "R_M1_A5"
 U1 K20
 RP6 6
Net 282 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A4" "R_M1_A4"
 U1 F20
 RP6 5
Net 300 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ12" "R_M1_DQ12"
 RP8 5
 U1 U20
Net 302 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ10" "R_M1_DQ10"
 RP9 7
 U1 R20
Net 304 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ0" "R_M1_DQ0"
 RP5 1
 U1 N20
Net 305 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDM" "R_M1_UDM"
 U1 M20
 R18 1
Net 306 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ4" "R_M1_DQ4"
 RP4 1
 U1 J20
Net 347 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ14" "R_M1_DQ14"
 RP8 7
 U1 V21
Net 348 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDQS" "R_M1_UDQS"
 R19 1
 U1 T21
Net 349 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ8" "R_M1_DQ8"
 U1 P21
 RP9 5
Net 350 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ2" "R_M1_DQ2"
 U1 M21
 RP5 3
Net 351 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ6" "R_M1_DQ6"
 RP4 3
 U1 K21
Net 352 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CS#" "R_M1_CS#"
 U1 H16
 R20 1
Net 356 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ15" "R_M1_DQ15"
 RP8 8
 U1 V22
Net 357 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ13" "R_M1_DQ13"
 RP8 6
 U1 U22
Net 359 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ11" "R_M1_DQ11"
 RP9 8
 U1 R22
Net 360 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ9" "R_M1_DQ9"
 RP9 6
 U1 P22
Net 361 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ1" "R_M1_DQ1"
 U1 N22
 RP5 2
Net 362 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ3" "R_M1_DQ3"
 RP5 4
 U1 M22
Net 364 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ7" "R_M1_DQ7"
 U1 K22
 RP4 4
Net 365 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ5" "R_M1_DQ5"
 RP4 2
 U1 J22
Net 367 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A2" "R_M0_A2"
 RP14 3
 U1 H5
Net 368 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A6" "R_M0_A6"
 U1 J4
 RP17 2
Net 369 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A3" "R_M0_A3"
 U1 K6
 RP14 4
Net 370 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A10" "R_M0_A10"
 RP15 4
 U1 G4
Net 371 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A7" "R_M0_A7"
 RP17 1
 U1 H6
Net 372 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ2" "R_M0_DQ2"
 U1 M2
 RP13 3
Net 373 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ6" "R_M0_DQ6"
 U1 K2
 RP12 3
Net 374 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A0" "R_M0_A0"
 U1 H2
 RP14 1
Net 380 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ11" "R_M0_DQ11"
 RP11 4
 U1 R1
Net 381 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ9" "R_M0_DQ9"
 RP11 2
 U1 P1
Net 382 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ1" "R_M0_DQ1"
 U1 N1
 RP13 2
Net 383 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ0" "R_M0_DQ0"
 RP13 1
 U1 N3
Net 384 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A5" "R_M0_A5"
 U1 K3
 RP17 3
Net 385 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ4" "R_M0_DQ4"
 RP12 1
 U1 J3
Net 386 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA0" "R_M0_BA0"
 RP15 2
 U1 G3
Net 387 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A4" "R_M0_A4"
 U1 F3
 RP17 4
Net 388 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A8" "R_M0_A8"
 U1 E3
 RP18 4
Net 393 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ8" "R_M0_DQ8"
 U1 P2
 RP11 1
Net 394 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ3" "R_M0_DQ3"
 U1 M1
 RP13 4
Net 396 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ7" "R_M0_DQ7"
 U1 K1
 RP12 4
Net 397 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ5" "R_M0_DQ5"
 U1 J1
 RP12 2
Net 398 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A1" "R_M0_A1"
 RP14 2
 U1 H1
Net 399 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA1" "R_M0_BA1"
 RP15 3
 U1 G1
Net 401 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A9" "R_M0_A9"
 U1 E1
 RP18 3
Net 402 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A12" "R_M0_A12"
 U1 D1
 RP18 1
Net 403 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A11" "R_M0_A11"
 U1 C1
 RP18 2
Net 405 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CAS#" "R_M0_CAS#"
 U1 K4
 RP16 4
Net 406 "/FPGA Port 1, Port 3 DDR, USB/R_M0_WE#" "R_M0_WE#"
 RP16 3
 U1 F2
Net 407 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDM" "R_M0_LDM"
 U1 L4
 RP16 2
Net 408 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDQS" "R_M0_LDQS"
 U1 L3
 RP16 1
Net 409 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDQS" "R_M0_UDQS"
 R22 1
 U1 T2
Net 410 "/FPGA Port 1, Port 3 DDR, USB/R_M0_RAS#" "R_M0_RAS#"
 U1 K5
 RP15 1
Net 411 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CKE" "R_M0_CKE"
 U1 D2
 R24 1
Net 412 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDM" "R_M0_UDM"
 U1 M3
 R23 1
Net 415 "" ""
 R30 2
 U1 Y22
Net 418 "" ""
 U1 AA1
 R29 2
Net 461 "" ""
 U22 3
 U22 1
 C117 1
Net 462 "" ""
 U23 1
 U23 3
 C118 1
Net 463 "" ""
 U23 5
 C125 2
 R67 2
 R68 1
Net 464 "" ""
 U19 4
 C109 1
Net 465 "" ""
 C120 1
 U22 4
Net 466 "" ""
 C124 2
 U22 5
 R66 1
 R65 2
Net 467 "" ""
 C107 1
 U20 3
 U20 1
Net 468 "" ""
 U23 4
 C121 1
Net 469 "" ""
 U20 4
 C110 1
Net 470 "" ""
 U20 5
 C113 2
 R63 2
 R64 1
Net 471 "" ""
 U18 1
 C105 1
 U18 3
Net 472 "" ""
 C108 1
 U18 4
Net 473 "" ""
 C106 1
 U19 3
 U19 1
Net 474 "" ""
 R62 1
 R61 2
 C112 2
 U19 5
Net 475 "" ""
 U18 5
 C111 2
 R59 2
 R60 1
Net 504 "/DDR Banks/M1_DQ13" "M1_DQ13"
 U3 62
 RP8 3
Net 505 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ14" "M1_DQ14"
 RP8 2
 U3 63
Net 506 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ15" "M1_DQ15"
 RP8 1
 U3 65
Net 507 "/DDR Banks/M0_DQ0" "M0_DQ0"
 U2 2
 RP13 8
Net 508 "/DDR Banks/M0_DQ1" "M0_DQ1"
 U2 4
 RP13 7
Net 509 "/DDR Banks/M0_DQ2" "M0_DQ2"
 RP13 6
 U2 5
Net 510 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ3" "M0_DQ3"
 RP13 5
 U2 7
Net 511 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ4" "M0_DQ4"
 U2 8
 RP12 8
Net 512 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ5" "M0_DQ5"
 RP12 7
 U2 10
Net 513 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ6" "M0_DQ6"
 U2 11
 RP12 6
Net 514 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ7" "M0_DQ7"
 U2 13
 RP12 5
Net 515 "/DDR Banks/M0_DQ8" "M0_DQ8"
 RP11 8
 U2 54
Net 516 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ9" "M0_DQ9"
 RP11 7
 U2 56
Net 517 "/DDR Banks/M0_DQ10" "M0_DQ10"
 RP11 6
 U2 57
Net 518 "/DDR Banks/M0_DQ11" "M0_DQ11"
 U2 59
 RP11 5
Net 519 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ12" "M0_DQ12"
 U2 60
 RP10 8
Net 520 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ13" "M0_DQ13"
 U2 62
 RP10 7
Net 521 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ0" "M1_DQ0"
 RP5 8
 U3 2
Net 522 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ1" "M1_DQ1"
 U3 4
 RP5 7
Net 523 "/DDR Banks/M1_DQ2" "M1_DQ2"
 RP5 6
 U3 5
Net 524 "/DDR Banks/M1_DQ3" "M1_DQ3"
 RP5 5
 U3 7
Net 525 "/DDR Banks/M1_DQ4" "M1_DQ4"
 RP4 8
 U3 8
Net 526 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ5" "M1_DQ5"
 U3 10
 RP4 7
Net 527 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ6" "M1_DQ6"
 RP4 6
 U3 11
Net 528 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ7" "M1_DQ7"
 U3 13
 RP4 5
Net 529 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ8" "M1_DQ8"
 RP9 4
 U3 54
Net 530 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ9" "M1_DQ9"
 U3 56
 RP9 3
Net 531 "/DDR Banks/M1_DQ10" "M1_DQ10"
 U3 57
 RP9 2
Net 532 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ11" "M1_DQ11"
 U3 59
 RP9 1
Net 533 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ12" "M1_DQ12"
 RP8 4
 U3 60
Net 534 "/DDR Banks/M1_A4" "M1_A4"
 U3 35
 RP6 4
Net 535 "/FPGA Port 1, Port 3 DDR, USB/M1_A5" "M1_A5"
 RP6 3
 U3 36
Net 536 "/DDR Banks/M1_A6" "M1_A6"
 RP6 2
 U3 37
Net 537 "/DDR Banks/M1_A7" "M1_A7"
 U3 38
 RP6 1
Net 538 "/FPGA Port 1, Port 3 DDR, USB/M1_A8" "M1_A8"
 RP7 4
 U3 39
Net 539 "/FPGA Port 1, Port 3 DDR, USB/M1_A9" "M1_A9"
 U3 40
 RP7 3
Net 540 "/FPGA Port 1, Port 3 DDR, USB/M1_A10" "M1_A10"
 U3 28
 RP2 5
Net 541 "/FPGA Port 1, Port 3 DDR, USB/M1_A11" "M1_A11"
 U3 41
 RP7 2
Net 542 "/DDR Banks/M1_A12" "M1_A12"
 RP7 1
 U3 42
Net 543 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ14" "M0_DQ14"
 RP10 6
 U2 63
Net 544 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ15" "M0_DQ15"
 RP10 5
 U2 65
Net 545 "/DDR Banks/M0_A0" "M0_A0"
 RP14 8
 U2 29
Net 546 "/DDR Banks/M0_A1" "M0_A1"
 U2 30
 RP14 7
Net 547 "/DDR Banks/M0_A2" "M0_A2"
 RP14 6
 U2 31
Net 548 "/DDR Banks/M0_A3" "M0_A3"
 RP14 5
 U2 32
Net 549 "/FPGA Port 1, Port 3 DDR, USB/M0_A4" "M0_A4"
 RP17 5
 U2 35
Net 550 "/FPGA Port 1, Port 3 DDR, USB/M0_A5" "M0_A5"
 U2 36
 RP17 6
Net 551 "/DDR Banks/M0_A6" "M0_A6"
 RP17 7
 U2 37
Net 552 "/FPGA Port 1, Port 3 DDR, USB/M0_A7" "M0_A7"
 U2 38
 RP17 8
Net 553 "/FPGA Port 1, Port 3 DDR, USB/M0_A8" "M0_A8"
 RP18 5
 U2 39
Net 554 "/FPGA Port 1, Port 3 DDR, USB/M0_A9" "M0_A9"
 U2 40
 RP18 6
Net 555 "/DDR Banks/M0_A10" "M0_A10"
 U2 28
 RP15 5
Net 556 "/FPGA Port 1, Port 3 DDR, USB/M0_A11" "M0_A11"
 U2 41
 RP18 7
Net 557 "/FPGA Port 1, Port 3 DDR, USB/M0_A12" "M0_A12"
 RP18 8
 U2 42
Net 558 "/DDR Banks/M1_A0" "M1_A0"
 U3 29
 RP1 8
Net 559 "/DDR Banks/M1_A1" "M1_A1"
 U3 30
 RP1 7
Net 560 "/FPGA Port 1, Port 3 DDR, USB/M1_A2" "M1_A2"
 RP1 6
 U3 31
Net 561 "/FPGA Port 1, Port 3 DDR, USB/M1_A3" "M1_A3"
 RP1 5
 U3 32
Net 562 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36"
 P1 30
 U1 T14
Net 565 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39"
 P1 23
 U1 AB13
Net 566 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40"
 U1 Y11
 P1 32
Net 569 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43"
 P1 34
 U1 V11
Net 570 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44"
 P1 31
 U1 W11
Net 571 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45"
 U1 Y9
 P1 35
Net 572 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46"
 U1 W10
 P1 36
Net 573 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47"
 P1 33
 U1 Y10
Net 574 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48"
 P1 40
 U1 W8
Net 576 "/FPGA GPIOS/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50"
 U1 W9
 P1 38
Net 578 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52"
 U1 V9
 P1 37
Net 580 "/FPGA GPIOS/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17"
 U1 V15
 P1 13
Net 581 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18"
 U1 AA18
 P1 12
Net 583 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20"
 U1 Y17
 P1 15
Net 584 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21"
 U1 AB17
 P1 14
Net 585 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22"
 P1 19
 U1 AA14
Net 587 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24"
 U1 Y16
 P1 16
Net 588 "/FPGA GPIOS/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25"
 U1 W15
 P1 22
Net 590 "/FPGA GPIOS/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27"
 U1 W13
 P1 21
Net 591 "/FPGA GPIOS/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28"
 U1 AA16
 P1 17
Net 592 "/FPGA GPIOS/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29"
 U1 AB16
 P1 18
Net 593 "/FPGA GPIOS/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30"
 P1 20
 U1 W14
Net 595 "/FPGA GPIOS/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32"
 U1 Y15
 P1 26
Net 596 "/FPGA GPIOS/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33"
 U1 AB15
 P1 24
Net 599 "/FPGA Port 1, Port 3 DDR, USB/M0_BA0" "M0_BA0"
 U2 26
 RP15 7
Net 600 "/DDR Banks/M0_BA1" "M0_BA1"
 RP15 6
 U2 27
Net 601 "/FPGA Port 1, Port 3 DDR, USB/M1_BA0" "M1_BA0"
 RP2 7
 U3 26
Net 602 "/DDR Banks/M1_BA1" "M1_BA1"
 U3 27
 RP2 6
Net 605 "/FPGA GPIOS/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56"
 U1 U10
 P1 39
Net 614 "/Non volatile memories/NF_D6" "NF_D6"
 U5 43
 U1 A11
Net 615 "/Non volatile memories/NF_D7" "NF_D7"
 U5 44
 U1 D11
Net 616 "/FPGA, Port0, Port2, PROG IF/PROG_MISO0" "PROG_MISO0"
 U8 5
 U1 AB20
Net 617 "/FPGA, Port0, Port2, PROG IF/PROG_MISO1" "PROG_MISO1"
 U8 2
 U1 AA20
Net 618 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2"
 U1 U14
 U8 3
Net 619 "/FPGA, Port0, Port2, PROG IF/PROG_MISO3" "PROG_MISO3"
 U1 U13
 U8 7
Net 620 "/Non volatile memories/SD_DAT0" "SD_DAT0"
 U1 A18
 J1 7
Net 621 "/Non volatile memories/SD_DAT1" "SD_DAT1"
 J1 8
 U1 B18
Net 622 "/FPGA, Port0, Port2, PROG IF/SD_DAT2" "SD_DAT2"
 U1 A16
 J1 1
Net 623 "/FPGA, Port0, Port2, PROG IF/SD_DAT3" "SD_DAT3"
 J1 2
 U1 B16
Net 624 "/FPGA, Port0, Port2, PROG IF/NF_D0" "NF_D0"
 U1 C12
 U5 29
Net 625 "/Non volatile memories/NF_D1" "NF_D1"
 U1 D14
 U5 30
Net 626 "/FPGA, Port0, Port2, PROG IF/NF_D2" "NF_D2"
 U5 31
 U1 A13
Net 627 "/FPGA, Port0, Port2, PROG IF/NF_D3" "NF_D3"
 U1 B12
 U5 32
Net 628 "/Non volatile memories/NF_D4" "NF_D4"
 U1 A12
 U5 41
Net 629 "/FPGA, Port0, Port2, PROG IF/NF_D5" "NF_D5"
 U1 C11
 U5 42
Net 630 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0"
 U1 D10
 U4 17
Net 631 "/FPGA, Port0, Port2, PROG IF/ETH_TXD1" "ETH_TXD1"
 U1 C9
 U4 18
Net 632 "/FPGA, Port0, Port2, PROG IF/ETH_TXD2" "ETH_TXD2"
 U4 19
 U1 C10
Net 633 "/FPGA, Port0, Port2, PROG IF/ETH_TXD3" "ETH_TXD3"
 U1 A8
 U4 20
Net 634 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0"
 U1 B6
 U4 6
Net 635 "/FPGA, Port0, Port2, PROG IF/ETH_RXD1" "ETH_RXD1"
 U4 5
 U1 A5
Net 636 "/FPGA, Port0, Port2, PROG IF/ETH_RXD2" "ETH_RXD2"
 U4 4
 U1 C6
Net 637 "/FPGA, Port0, Port2, PROG IF/ETH_RXD3" "ETH_RXD3"
 U4 3
 U1 C5
Net 638 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_0" "FPGA_BANK0_IO_0"
 P1 5
 U1 AA22
Net 639 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1"
 P1 2
 U1 T18
Net 640 "/FPGA GPIOS/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2"
 P1 25
 U1 T17
Net 641 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3"
 U1 Y19
 P1 10
Net 643 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5"
 U1 Y18
 P1 11
Net 644 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6"
 P1 28
 U1 T16
Net 645 "/FPGA GPIOS/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7"
 U1 T15
 P1 27
Net 646 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8"
 P1 1
 U1 U17
Net 647 "/FPGA GPIOS/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9"
 P1 4
 U1 U16
Net 648 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10"
 U1 V19
 P1 7
Net 649 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11"
 U1 V18
 P1 9
Net 650 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12"
 P1 29
 U1 R16
Net 652 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14"
 U1 V17
 P1 6
Net 653 "/FPGA GPIOS/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15"
 P1 8
 U1 W17
Net 654 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_16" "FPGA_BANK0_IO_16"
 P1 3
 U1 U15
Net 655 "/Image Sensor/IS_DOUT0" "IS_DOUT0"
 U24 45
 U1 AB12
Net 656 "/FPGA, Port0, Port2, PROG IF/IS_DOUT1" "IS_DOUT1"
 U1 AA12
 U24 46
Net 657 "/FPGA, Port0, Port2, PROG IF/IS_DOUT2" "IS_DOUT2"
 U1 AB11
 U24 47
Net 658 "/FPGA, Port0, Port2, PROG IF/IS_DOUT3" "IS_DOUT3"
 U1 AB10
 U24 48
Net 659 "/FPGA, Port0, Port2, PROG IF/IS_DOUT4" "IS_DOUT4"
 U1 AA10
 U24 1
Net 660 "/FPGA, Port0, Port2, PROG IF/IS_DOUT5" "IS_DOUT5"
 U1 AB9
 U24 2
Net 661 "/FPGA, Port0, Port2, PROG IF/IS_DOUT6" "IS_DOUT6"
 U24 3
 U1 Y8
Net 662 "/Image Sensor/IS_DOUT7" "IS_DOUT7"
 U1 AA8
 U24 7
Net 663 "/FPGA, Port0, Port2, PROG IF/IS_DOUT8" "IS_DOUT8"
 U1 AB8
 U24 8
Net 664 "/Image Sensor/IS_DOUT9" "IS_DOUT9"
 U1 Y7
 U24 9
Net 665 "/Image Sensor/IS_DOUT10" "IS_DOUT10"
 U24 10
 U1 Y6
Net 666 "/FPGA, Port0, Port2, PROG IF/IS_DOUT11" "IS_DOUT11"
 U1 AB7
 U24 11
}
#End