xue/kicad/xue-rnc/xue-rnc.net

# EESchema Netlist Version 1.1 created  Sat 28 Aug 2010 09:57:24 PM COT
(
 ( /4C716A4D/4C716CAB $noname  J6 CONN_8X2 {Lib=CONN_8X2}
  (    1 /DBG_PRG/FPGA_TCK )
  (    2 ? )
  (    3 /DBG_PRG/FPGA_TMS )
  (    4 ? )
  (    5 /DBG_PRG/FPGA_TDO )
  (    6 ? )
  (    7 /DBG_PRG/FPGA_TDI )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 ? )
  (   13 ? )
  (   14 ? )
  (   15 ? )
  (   16 ? )
 )
 ( /4C69ED5F/4C79C99E 0805  C95 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-5.0 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C99C 0402  R35 R {Lib=R}
  (    1 /PSU/Iout_5.0 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C99B 1206  R36 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-5.0 )
  (    2 N-000430 )
 )
 ( /4C69ED5F/4C79C99A MLP6  U16 FAN4010 {Lib=FAN4010}
  (    1 N-000430 )
  (    2 ? )
  (    3 /PSU/Iout_5.0 )
  (    5 GND )
  (    6 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C79C8B2 0402  C98 100nF {Lib=CAP}
  (    1 +5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8B1 0402  R39 R {Lib=R}
  (    1 +5V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C79C8B0 0402  R38 R {Lib=R}
  (    1 /PSU/VFB1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8AF 1206  C97 10uF {Lib=CAP}
  (    1 +5V )
  (    2 GND )
 )
 ( /4C69ED5F/4C79C8AE 0402  C96 22pF {Lib=CAP}
  (    1 +5V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C79C828 1210  L10 4.7uH {Lib=INDUCTOR}
  (    1 N-000428 )
  (    2 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C79C7C0 0402  R37 R {Lib=R}
  (    1 N-000435 )
  (    2 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C79C65B SOT23_6  U15 A7117 {Lib=A7117}
  (    1 N-000428 )
  (    2 GND )
  (    3 /PSU/VFB1.2 )
  (    4 N-000435 )
  (    5 +5V )
  (    6 /PSU/VIN_DC-DC-5.0 )
 )
 ( /4C69ED5F/4C770714 MLP6  U14 FAN4010 {Lib=FAN4010}
  (    1 N-000425 )
  (    2 ? )
  (    3 /PSU/Iout_1.2 )
  (    5 GND )
  (    6 ? )
 )
 ( /4C69ED5F/4C770713 1206  R34 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-1.2 )
  (    2 N-000425 )
 )
 ( /4C69ED5F/4C770712 0402  R33 R {Lib=R}
  (    1 /PSU/Iout_1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C77067B 0402  R31 R {Lib=R}
  (    1 /PSU/Iout_3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C77060E 1206  R32 R {Lib=R}
  (    1 /PSU/VIN_DC-DC-3.3 )
  (    2 N-000426 )
 )
 ( /4C69ED5F/4C7705B0 MLP6  U13 FAN4010 {Lib=FAN4010}
  (    1 N-000426 )
  (    2 ? )
  (    3 /PSU/Iout_3.3 )
  (    5 GND )
  (    6 /PSU/VIN_DC-DC-3.3 )
 )
 ( /4C69ED5F/4C6D2FD7 0805  C82 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD6 0402  C83 22pF {Lib=CAP}
  (    1 +1.2V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2FD5 1206  C84 10uF {Lib=CAP}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD3 0402  R27 R {Lib=R}
  (    1 /PSU/VFB1.2 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2FD2 0402  R28 R {Lib=R}
  (    1 +1.2V )
  (    2 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2FD1 1210  L9 2.2uH {Lib=INDUCTOR}
  (    1 +1.2V )
  (    2 /PSU/SW_1.2 )
 )
 ( /4C69ED5F/4C6D2FD0 0402  C85 100nF {Lib=CAP}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2F0B 0402  C81 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2E6A 1210  L8 2.2uH {Lib=INDUCTOR}
  (    1 +3.3V )
  (    2 /PSU/SW_3.3 )
 )
 ( /4C69ED5F/4C6D2DDD 0402  R26 R {Lib=R}
  (    1 +3.3V )
  (    2 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6D2DBC 0402  R25 R {Lib=R}
  (    1 /PSU/VFB3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2C83 1206  C80 10uF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2C7F 0402  C79 22pF {Lib=CAP}
  (    1 +3.3V )
  (    2 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6D2C7C 0805  C78 4.7uF {Lib=CAP}
  (    1 /PSU/VIN_DC-DC-3.3 )
  (    2 GND )
 )
 ( /4C69ED5F/4C6D2AE0 SOT23-5  U12 A7108 {Lib=A7108}
  (    1 /PSU/VIN_DC-DC-1.2 )
  (    2 GND )
  (    3 /PSU/SW_1.2 )
  (    4 /PSU/VIN_DC-DC-1.2 )
  (    5 /PSU/VFB1.2 )
 )
 ( /4C69ED5F/4C6D2AA5 SOT23-5  U11 A7108 {Lib=A7108}
  (    1 /PSU/VIN_DC-DC-3.3 )
  (    2 GND )
  (    3 /PSU/SW_3.3 )
  (    4 /PSU/VIN_DC-DC-3.3 )
  (    5 /PSU/VFB3.3 )
 )
 ( /4C69ED5F/4C6C9DB9 DFN10  U10 A7130 {Lib=A7130}
  (    1 ? )
  (    2 GND )
  (    3 ? )
  (    4 ? )
  (    5 GND )
  (    6 ? )
  (    7 ? )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (  PAD GND )
 )
 ( /4C69ED5F/4C69EE11 MLF20m1  U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF}
  (    1 ? )
  (    2 ? )
  (    3 /PSU/Iout_1.2 )
  (    4 /PSU/Iout_3.3 )
  (    5 ? )
  (    6 ? )
  (    7 ? )
  (    8 GND )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 ? )
  (   13 ? )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 ? )
  (   20 ? )
  (  PAD GND )
 )
 ( /4C4227FE/4C6969AB $noname  C75 100nF {Lib=C}
  (    1 GND )
  (    2 +3.3V )
 )
 ( /4C4227FE/4C65D681 0603  C74 1uF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65D67C 0402  C73 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65D661 0402  C72 100nF {Lib=CAP}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4227FE/4C65A75D $noname  U8 X25X64MB {Lib=X25X64MB}
  (    1 /FPGA_Spartan6/PROG_CSO )
  (    2 /FPGA_Spartan6/PROG_MISO1 )
  (    3 /FPGA_Spartan6/PROG_MISO2 )
  (    4 GND )
  (    5 /FPGA_Spartan6/PROG_MISO0 )
  (    6 /FPGA_Spartan6/PROG_CCLK )
  (    7 /FPGA_Spartan6/PROG_MISO3 )
  (    8 VCCO2 )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  (    1 /Non_volatile_memories/SD_DAT2 )
  (    2 /Non_volatile_memories/SD_DAT3 )
  (    3 /FPGA_Spartan6/SD_CMD )
  (    4 +3.3V )
  (    5 /FPGA_Spartan6/SD_CLK )
  (    6 GND )
  (    7 /FPGA_Spartan6/SD_DAT0 )
  (    8 /FPGA_Spartan6/SD_DAT1 )
  ( CASE GND )
  (   CD ? )
  (  COM GND )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /FPGA_Spartan6/NF_RNB )
  (    7 /FPGA_Spartan6/NF_RNB )
  (    8 /Non_volatile_memories/NF_RE_N )
  (    9 /FPGA_Spartan6/NF_CS1_N )
  (   10 ? )
  (   11 ? )
  (   12 +3.3V )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 /FPGA_Spartan6/NF_CLE )
  (   17 /Non_volatile_memories/NF_ALE )
  (   18 /Non_volatile_memories/NF_WE_N )
  (   19 +3.3V )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 /FPGA_Spartan6/NF_D0 )
  (   30 /Non_volatile_memories/NF_D1 )
  (   31 /FPGA_Spartan6/NF_D2 )
  (   32 /FPGA_Spartan6/NF_D3 )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 +3.3V )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 /Non_volatile_memories/NF_D4 )
  (   42 /FPGA_Spartan6/NF_D5 )
  (   43 /FPGA_Spartan6/NF_D6 )
  (   44 /FPGA_Spartan6/NF_D7 )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C5F1EDC/4C75F027 ZX62D-B-5P8  J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
  (    1 N-000413 )
  (    2 /USB/USBD_D- )
  (    3 /USB/USBD_D+ )
  (    4 N-000414 )
  (    5 N-000414 )
  (    6 N-000424 )
  (    7 N-000424 )
  (    8 N-000424 )
  (    9 N-000424 )
 )
 ( /4C5F1EDC/4C71BA25 MLF16  U7 MIC2550-MLF {Lib=MIC2550-MLF}
  (    1 /FPGA_Spartan6/USBD_SPD )
  (    2 /FPGA_Spartan6/USBD_RCV )
  (    3 /USB/USBD_VP )
  (    4 /USB/USBD_VM )
  (    6 GND )
  (    7 GND )
  (    9 /USB/USBD_OE_N )
  (   10 /USB/USBD_D- )
  (   11 /USB/USBD_D+ )
  (   12 +3.3V )
  (   14 +3.3V )
  (   15 +2.5V )
 )
 ( /4C5F1EDC/4C71BA1D MLF16  U6 MIC2550-MLF {Lib=MIC2550-MLF}
  (    1 /USB/USBA_SPD )
  (    2 /FPGA_Spartan6/USBA_RCV )
  (    3 /USB/USBA_VP )
  (    4 /FPGA_Spartan6/USBA_VM )
  (    6 GND )
  (    7 GND )
  (    9 /USB/USBA_OE_N )
  (   10 /USB/USBA_D- )
  (   11 /USB/USBA_D+ )
  (   12 +3.3V )
  (   14 +3.3V )
  (   15 +2.5V )
 )
 ( /4C5F1EDC/4C6552BE $noname  C35 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552BD 0402  C36 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552BC 0402  C37 100nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B9 $noname  V4 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBD_D- )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B8 $noname  V3 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBD_D+ )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B7 $noname  C38 4.7nF {Lib=C}
  (    1 N-000424 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B6 $noname  R15 1M {Lib=R}
  (    1 N-000424 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C6552B1 0603  L7 FB {Lib=INDUCTOR}
  (    1 N-000413 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C63F252 0603  L4 FB {Lib=INDUCTOR}
  (    1 N-000417 )
  (    2 N-000422 )
 )
 ( /4C5F1EDC/4C63F248 0603  L5 FB {Lib=INDUCTOR}
  (    1 N-000418 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D27 $noname  R10 1M {Lib=R}
  (    1 N-000421 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D1E $noname  C16 4.7nF {Lib=C}
  (    1 N-000421 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA7 0603  V1 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBA_D+ )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA3 0603  V2 V0402MHS03 {Lib=V0402MHS03}
  (    1 /USB/USBA_D- )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2B55 $noname  F1 MICROSMD075F {Lib=MICROSMD075F}
  (    1 N-000417 )
  (    2 +5V )
 )
 ( /4C5F1EDC/4C5F23DD $noname  J5 USB-48204-0001 {Lib=USB-48204-0001}
  (    1 N-000422 )
  (    2 /USB/USBA_D- )
  (    3 /USB/USBA_D+ )
  (    4 N-000418 )
  (   S1 N-000421 )
  (   S2 N-000421 )
  (   S3 N-000421 )
  (   S4 N-000421 )
 )
 ( /4C5F1EDC/4C5F2039 $noname  C15 100nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2037 0402  C14 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2033 $noname  C13 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C749A0C 0402  C94 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C748EDB 0402  C92 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C748EDA 0402  C93 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C73D252 0402  C91 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C73D074 0402  C90 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C7168DD 0402  R30 330 {Lib=R}
  (    1 +3.3V )
  (    2 N-000261 )
 )
 ( /4C431A63/4C716877 0402  R29 4.7k {Lib=R}
  (    1 +3.3V )
  (    2 N-000385 )
 )
 ( /4C431A63/4C6B29DA 0402  C77 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C6B29A3 0402  C76 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C6B216E 0402  R23 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M0_UDM )
  (    2 /DDR_Banks/M0_UDM )
 )
 ( /4C431A63/4C6B216D 0402  R22 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M0_UDQS )
  (    2 /FPGA_Spartan6/M0_UDQS )
 )
 ( /4C431A63/4C6B216B 0402  R24 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M0_CKE )
  (    2 /DDR_Banks/M0_CKE )
 )
 ( /4C431A63/4C6B1B90 0402  R21 120 {Lib=R}
  (    1 /DDR_Banks/M0_CLK )
  (    2 /DDR_Banks/M0_CLK# )
 )
 ( /4C431A63/4C6A0D58 R_PACK4-0402  RP14 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_A0 )
  (    2 /FPGA_Spartan6/R_M0_A1 )
  (    3 /FPGA_Spartan6/R_M0_A2 )
  (    4 /FPGA_Spartan6/R_M0_A3 )
  (    5 /DDR_Banks/M0_A3 )
  (    6 /FPGA_Spartan6/M0_A2 )
  (    7 /DDR_Banks/M0_A1 )
  (    8 /FPGA_Spartan6/M0_A0 )
 )
 ( /4C431A63/4C6A0D57 R_PACK4-0402  RP15 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_RAS# )
  (    2 /FPGA_Spartan6/R_M0_BA0 )
  (    3 /FPGA_Spartan6/R_M0_BA1 )
  (    4 /FPGA_Spartan6/R_M0_A10 )
  (    5 /DDR_Banks/M0_A10 )
  (    6 /FPGA_Spartan6/M0_BA1 )
  (    7 /DDR_Banks/M0_BA0 )
  (    8 /DDR_Banks/M0_RAS# )
 )
 ( /4C431A63/4C6A0D56 R_PACK4-0402  RP16 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_LDQS )
  (    2 /FPGA_Spartan6/R_M0_LDM )
  (    3 /FPGA_Spartan6/R_M0_WE# )
  (    4 /FPGA_Spartan6/R_M0_CAS# )
  (    5 /DDR_Banks/M0_CAS# )
  (    6 /DDR_Banks/M0_WE# )
  (    7 /DDR_Banks/M0_LDM )
  (    8 /DDR_Banks/M0_LDQS )
 )
 ( /4C431A63/4C6A0D55 R_PACK4-0402  RP17 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_A7 )
  (    2 /FPGA_Spartan6/R_M0_A6 )
  (    3 /FPGA_Spartan6/R_M0_A5 )
  (    4 /FPGA_Spartan6/R_M0_A4 )
  (    5 /FPGA_Spartan6/M0_A4 )
  (    6 /DDR_Banks/M0_A5 )
  (    7 /DDR_Banks/M0_A6 )
  (    8 /DDR_Banks/M0_A7 )
 )
 ( /4C431A63/4C6A0D54 R_PACK4-0402  RP18 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_A12 )
  (    2 /FPGA_Spartan6/R_M0_A11 )
  (    3 /FPGA_Spartan6/R_M0_A9 )
  (    4 /FPGA_Spartan6/R_M0_A8 )
  (    5 /FPGA_Spartan6/M0_A8 )
  (    6 /FPGA_Spartan6/M0_A9 )
  (    7 /FPGA_Spartan6/M0_A11 )
  (    8 /FPGA_Spartan6/M0_A12 )
 )
 ( /4C431A63/4C69FCE8 R_PACK4-0402  RP12 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_DQ4 )
  (    2 /FPGA_Spartan6/R_M0_DQ5 )
  (    3 /FPGA_Spartan6/R_M0_DQ6 )
  (    4 /FPGA_Spartan6/R_M0_DQ7 )
  (    5 /DDR_Banks/M0_DQ7 )
  (    6 /FPGA_Spartan6/M0_DQ6 )
  (    7 /FPGA_Spartan6/M0_DQ5 )
  (    8 /DDR_Banks/M0_DQ4 )
 )
 ( /4C431A63/4C69FCE7 R_PACK4-0402  RP13 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_DQ0 )
  (    2 /FPGA_Spartan6/R_M0_DQ1 )
  (    3 /FPGA_Spartan6/R_M0_DQ2 )
  (    4 /FPGA_Spartan6/R_M0_DQ3 )
  (    5 /FPGA_Spartan6/M0_DQ3 )
  (    6 /FPGA_Spartan6/M0_DQ2 )
  (    7 /DDR_Banks/M0_DQ1 )
  (    8 /DDR_Banks/M0_DQ0 )
 )
 ( /4C431A63/4C69FCE6 R_PACK4-0402  RP11 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_DQ8 )
  (    2 /FPGA_Spartan6/R_M0_DQ9 )
  (    3 /FPGA_Spartan6/R_M0_DQ10 )
  (    4 /FPGA_Spartan6/R_M0_DQ11 )
  (    5 /FPGA_Spartan6/M0_DQ11 )
  (    6 /FPGA_Spartan6/M0_DQ10 )
  (    7 /DDR_Banks/M0_DQ9 )
  (    8 /FPGA_Spartan6/M0_DQ8 )
 )
 ( /4C431A63/4C69FC19 R_PACK4-0402  RP10 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M0_DQ12 )
  (    2 /FPGA_Spartan6/R_M0_DQ13 )
  (    3 /FPGA_Spartan6/R_M0_DQ14 )
  (    4 /FPGA_Spartan6/R_M0_DQ15 )
  (    5 /FPGA_Spartan6/M0_DQ15 )
  (    6 /FPGA_Spartan6/M0_DQ14 )
  (    7 /FPGA_Spartan6/M0_DQ13 )
  (    8 /FPGA_Spartan6/M0_DQ12 )
 )
 ( /4C431A63/4C69E7DD 0402  R19 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M1_UDQS )
  (    2 /DDR_Banks/M1_UDQS )
 )
 ( /4C431A63/4C69E92D 0402  R20 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M1_CS# )
  (    2 /DDR_Banks/M1_CS# )
 )
 ( /4C431A63/4C69E7F8 0402  R17 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M1_CKE )
  (    2 /FPGA_Spartan6/M1_CKE )
 )
 ( /4C431A63/4C69E7C2 0402  R18 33 {Lib=R}
  (    1 /FPGA_Spartan6/R_M1_UDM )
  (    2 /DDR_Banks/M1_UDM )
 )
 ( /4C431A63/4C69E3A6 $noname  RP9 R_PACK4 {Lib=R_PACK4}
  (    1 /DDR_Banks/M1_DQ11 )
  (    2 /DDR_Banks/M1_DQ10 )
  (    3 /DDR_Banks/M1_DQ9 )
  (    4 /DDR_Banks/M1_DQ8 )
  (    5 /FPGA_Spartan6/R_M1_DQ8 )
  (    6 /FPGA_Spartan6/R_M1_DQ9 )
  (    7 /FPGA_Spartan6/R_M1_DQ10 )
  (    8 /FPGA_Spartan6/R_M1_DQ11 )
 )
 ( /4C431A63/4C69E299 $noname  RP8 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/M1_DQ15 )
  (    2 /DDR_Banks/M1_DQ14 )
  (    3 /FPGA_Spartan6/M1_DQ13 )
  (    4 /DDR_Banks/M1_DQ12 )
  (    5 /FPGA_Spartan6/R_M1_DQ12 )
  (    6 /FPGA_Spartan6/R_M1_DQ13 )
  (    7 /FPGA_Spartan6/R_M1_DQ14 )
  (    8 /FPGA_Spartan6/R_M1_DQ15 )
 )
 ( /4C431A63/4C69DF7A 0402  R16 120 {Lib=R}
  (    1 /FPGA_Spartan6/M1_CLK# )
  (    2 /FPGA_Spartan6/M1_CLK )
 )
 ( /4C431A63/4C69DC05 $noname  RP7 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/M1_A12 )
  (    2 /FPGA_Spartan6/M1_A11 )
  (    3 /DDR_Banks/M1_A9 )
  (    4 /DDR_Banks/M1_A8 )
  (    5 /FPGA_Spartan6/R_M1_A8 )
  (    6 /FPGA_Spartan6/R_M1_A9 )
  (    7 /FPGA_Spartan6/R_M1_A11 )
  (    8 /FPGA_Spartan6/R_M1_A12 )
 )
 ( /4C431A63/4C69DA8A $noname  RP6 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/M1_A7 )
  (    2 /DDR_Banks/M1_A6 )
  (    3 /DDR_Banks/M1_A5 )
  (    4 /FPGA_Spartan6/M1_A4 )
  (    5 /FPGA_Spartan6/R_M1_A4 )
  (    6 /FPGA_Spartan6/R_M1_A5 )
  (    7 /FPGA_Spartan6/R_M1_A6 )
  (    8 /FPGA_Spartan6/R_M1_A7 )
 )
 ( /4C431A63/4C69D3A9 $noname  RP5 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M1_DQ0 )
  (    2 /FPGA_Spartan6/R_M1_DQ1 )
  (    3 /FPGA_Spartan6/R_M1_DQ2 )
  (    4 /FPGA_Spartan6/R_M1_DQ3 )
  (    5 /FPGA_Spartan6/M1_DQ3 )
  (    6 /FPGA_Spartan6/M1_DQ2 )
  (    7 /DDR_Banks/M1_DQ1 )
  (    8 /FPGA_Spartan6/M1_DQ0 )
 )
 ( /4C431A63/4C69D3A4 $noname  RP3 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M1_LDQS )
  (    2 /FPGA_Spartan6/R_M1_LDM )
  (    3 /FPGA_Spartan6/R_M1_WE# )
  (    4 /FPGA_Spartan6/R_M1_CAS# )
  (    5 /FPGA_Spartan6/M1_CAS# )
  (    6 /DDR_Banks/M1_WE# )
  (    7 /DDR_Banks/M1_LDM )
  (    8 /DDR_Banks/M1_LDQS )
 )
 ( /4C431A63/4C69D3A3 $noname  RP4 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M1_DQ4 )
  (    2 /FPGA_Spartan6/R_M1_DQ5 )
  (    3 /FPGA_Spartan6/R_M1_DQ6 )
  (    4 /FPGA_Spartan6/R_M1_DQ7 )
  (    5 /DDR_Banks/M1_DQ7 )
  (    6 /DDR_Banks/M1_DQ6 )
  (    7 /FPGA_Spartan6/M1_DQ5 )
  (    8 /FPGA_Spartan6/M1_DQ4 )
 )
 ( /4C431A63/4C69CEE8 $noname  RP2 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M1_RAS# )
  (    2 /FPGA_Spartan6/R_M1_BA0 )
  (    3 /FPGA_Spartan6/R_M1_BA1 )
  (    4 /FPGA_Spartan6/R_M1_A10 )
  (    5 /FPGA_Spartan6/M1_A10 )
  (    6 /FPGA_Spartan6/M1_BA1 )
  (    7 /DDR_Banks/M1_BA0 )
  (    8 /FPGA_Spartan6/M1_RAS# )
 )
 ( /4C431A63/4C69C6B2 $noname  RP1 R_PACK4 {Lib=R_PACK4}
  (    1 /FPGA_Spartan6/R_M1_A0 )
  (    2 /FPGA_Spartan6/R_M1_A1 )
  (    3 /FPGA_Spartan6/R_M1_A2 )
  (    4 /FPGA_Spartan6/R_M1_A3 )
  (    5 /FPGA_Spartan6/M1_A3 )
  (    6 /FPGA_Spartan6/M1_A2 )
  (    7 /DDR_Banks/M1_A1 )
  (    8 /FPGA_Spartan6/M1_A0 )
 )
 ( /4C431A63/4C656D9D $noname  C66 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656D9A $noname  C63 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656D99 $noname  C60 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656D98 $noname  C57 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656D97 $noname  C54 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656D53 $noname  C69 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D49 $noname  C67 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D46 $noname  C64 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D45 $noname  C61 470nF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D44 $noname  C58 4.7uF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D43 $noname  C55 100uF {Lib=C}
  (    1 VCCO2 )
  (    2 GND )
 )
 ( /4C431A63/4C656D08 $noname  C68 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656CFC $noname  C65 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656CFB $noname  C62 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656CFA $noname  C59 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656CF9 $noname  C56 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656CBB $noname  C50 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C656CBA $noname  C47 470nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C656CB9 $noname  C44 4.7uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C656CB7 $noname  C41 100uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C431A63/4C656C49 $noname  C53 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656C27 $noname  C51 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656C24 $noname  C49 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656C16 $noname  C46 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656BFA $noname  C52 470nF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656BF9 $noname  C43 4.7uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656BF8 $noname  C40 100uF {Lib=C}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C431A63/4C656AC2 $noname  C48 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C656AC0 $noname  C45 470nF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C656ABD $noname  C42 4.7uF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C656A80 $noname  C39 100uF {Lib=C}
  (    1 +1.2V )
  (    2 GND )
 )
 ( /4C431A63/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   A1 GND )
  (   A2 ? )
  (   A3 ? )
  (   A4 /Ethernet_Phy/ETH_CLK )
  (   A5 /Ethernet_Phy/ETH_RXD1 )
  (   A6 /FPGA_Spartan6/ETH_RXDV )
  (   A7 /Ethernet_Phy/ETH_RXC )
  (   A8 /FPGA_Spartan6/ETH_TXD3 )
  (   A9 /FPGA_Spartan6/ETH_COL )
  (  A10 /Ethernet_Phy/ETH_INT )
  (  A11 /FPGA_Spartan6/NF_D6 )
  (  A12 /Non_volatile_memories/NF_D4 )
  (  A13 /FPGA_Spartan6/NF_D2 )
  (  A14 /Non_volatile_memories/NF_ALE )
  (  A15 /FPGA_Spartan6/NF_RNB )
  (  A16 /Non_volatile_memories/SD_DAT2 )
  (  A17 /FPGA_Spartan6/SD_CLK )
  (  A18 /FPGA_Spartan6/SD_DAT0 )
  (  A19 /DBG_PRG/FPGA_TDO )
  (  A20 /FPGA_Spartan6/USBD_RCV )
  (  A21 /USB/USBD_OE_N )
  (  A22 GND )
  (  AA1 N-000385 )
  (  AA2 ? )
  (  AA3 VCCO2 )
  (  AA4 ? )
  (  AA5 GND )
  (  AA6 ? )
  (  AA7 VCCO2 )
  (  AA8 ? )
  (  AA9 GND )
  ( AA10 ? )
  ( AA11 VCCO2 )
  ( AA12 ? )
  ( AA13 GND )
  ( AA14 ? )
  ( AA15 VCCO2 )
  ( AA16 ? )
  ( AA17 GND )
  ( AA18 ? )
  ( AA19 VCCO2 )
  ( AA20 /FPGA_Spartan6/PROG_MISO1 )
  ( AA21 /FPGA_Spartan6/PROG_CCLK )
  ( AA22 ? )
  (  AB1 GND )
  (  AB2 ? )
  (  AB3 ? )
  (  AB4 ? )
  (  AB5 ? )
  (  AB6 ? )
  (  AB7 ? )
  (  AB8 ? )
  (  AB9 ? )
  ( AB10 ? )
  ( AB11 ? )
  ( AB12 ? )
  ( AB13 ? )
  ( AB14 ? )
  ( AB15 ? )
  ( AB16 ? )
  ( AB17 ? )
  ( AB18 ? )
  ( AB19 ? )
  ( AB20 /FPGA_Spartan6/PROG_MISO0 )
  ( AB21 ? )
  ( AB22 GND )
  (   B1 ? )
  (   B2 ? )
  (   B3 ? )
  (   B4 +3.3V )
  (   B5 GND )
  (   B6 /Ethernet_Phy/ETH_RXD0 )
  (   B7 +3.3V )
  (   B8 /Ethernet_Phy/ETH_RXER )
  (   B9 GND )
  (  B10 /Ethernet_Phy/ETH_CRS )
  (  B11 +3.3V )
  (  B12 /FPGA_Spartan6/NF_D3 )
  (  B13 GND )
  (  B14 /FPGA_Spartan6/NF_CLE )
  (  B15 +3.3V )
  (  B16 /Non_volatile_memories/SD_DAT3 )
  (  B17 GND )
  (  B18 /FPGA_Spartan6/SD_DAT1 )
  (  B19 +3.3V )
  (  B20 /FPGA_Spartan6/USBD_SPD )
  (  B21 /USB/USBD_VP )
  (  B22 /USB/USBD_VM )
  (   C1 /FPGA_Spartan6/R_M0_A11 )
  (   C2 +2.5V )
  (   C3 ? )
  (   C4 ? )
  (   C5 /Ethernet_Phy/ETH_RXD3 )
  (   C6 /FPGA_Spartan6/ETH_RXD2 )
  (   C7 /FPGA_Spartan6/ETH_RESET_N )
  (   C8 /Ethernet_Phy/ETH_TXC )
  (   C9 /FPGA_Spartan6/ETH_TXD1 )
  (  C10 /Ethernet_Phy/ETH_TXD2 )
  (  C11 /FPGA_Spartan6/NF_D5 )
  (  C12 /FPGA_Spartan6/NF_D0 )
  (  C13 ? )
  (  C14 /Non_volatile_memories/NF_WE_N )
  (  C15 /Non_volatile_memories/NF_RE_N )
  (  C16 /FPGA_Spartan6/SD_CMD )
  (  C17 ? )
  (  C18 /DBG_PRG/FPGA_TMS )
  (  C19 /USB/USBA_OE_N )
  (  C20 /FPGA_Spartan6/R_M1_A8 )
  (  C21 +2.5V )
  (  C22 /FPGA_Spartan6/R_M1_A9 )
  (   D1 /FPGA_Spartan6/R_M0_A12 )
  (   D2 /FPGA_Spartan6/R_M0_CKE )
  (   D3 ? )
  (   D4 GND )
  (   D5 ? )
  (   D6 /Ethernet_Phy/ETH_MDIO )
  (   D7 /FPGA_Spartan6/ETH_MDC )
  (   D8 /Ethernet_Phy/ETH_TXER )
  (   D9 /Ethernet_Phy/ETH_TXEN )
  (  D10 /FPGA_Spartan6/ETH_TXD0 )
  (  D11 /FPGA_Spartan6/NF_D7 )
  (  D12 ? )
  (  D13 ? )
  (  D14 /Non_volatile_memories/NF_D1 )
  (  D15 /FPGA_Spartan6/NF_CS1_N )
  (  D16 +2.5V )
  (  D17 ? )
  (  D18 GND )
  (  D19 /USB/USBA_VP )
  (  D20 /FPGA_Spartan6/USBA_VM )
  (  D21 /FPGA_Spartan6/R_M1_CKE )
  (  D22 /FPGA_Spartan6/R_M1_A12 )
  (   E1 /FPGA_Spartan6/R_M0_A9 )
  (   E2 GND )
  (   E3 /FPGA_Spartan6/R_M0_A8 )
  (   E4 ? )
  (   E5 ? )
  (   E6 ? )
  (   E7 GND )
  (   E8 ? )
  (   E9 +3.3V )
  (  E10 ? )
  (  E11 GND )
  (  E12 ? )
  (  E13 +3.3V )
  (  E14 ? )
  (  E15 GND )
  (  E16 ? )
  (  E17 +3.3V )
  (  E18 /DBG_PRG/FPGA_TDI )
  (  E19 +2.5V )
  (  E20 /FPGA_Spartan6/R_M1_A7 )
  (  E21 GND )
  (  E22 /FPGA_Spartan6/R_M1_A2 )
  (   F1 ? )
  (   F2 /FPGA_Spartan6/R_M0_WE# )
  (   F3 /FPGA_Spartan6/R_M0_A4 )
  (   F4 +2.5V )
  (   F5 ? )
  (   F6 +2.5V )
  (   F7 ? )
  (   F8 ? )
  (   F9 ? )
  (  F10 ? )
  (  F11 +2.5V )
  (  F12 ? )
  (  F13 ? )
  (  F14 ? )
  (  F15 ? )
  (  F16 /USB/USBA_SPD )
  (  F17 /FPGA_Spartan6/USBA_RCV )
  (  F18 ? )
  (  F19 /FPGA_Spartan6/R_M1_A11 )
  (  F20 /FPGA_Spartan6/R_M1_A4 )
  (  F21 /FPGA_Spartan6/R_M1_A0 )
  (  F22 /FPGA_Spartan6/R_M1_A1 )
  (   G1 /FPGA_Spartan6/R_M0_BA1 )
  (   G2 +2.5V )
  (   G3 /FPGA_Spartan6/R_M0_BA0 )
  (   G4 /FPGA_Spartan6/R_M0_A10 )
  (   G5 GND )
  (   G6 ? )
  (   G7 ? )
  (   G8 ? )
  (   G9 ? )
  (  G10 +3.3V )
  (  G11 ? )
  (  G12 +2.5V )
  (  G13 ? )
  (  G14 +3.3V )
  (  G15 /DBG_PRG/FPGA_TCK )
  (  G16 ? )
  (  G17 ? )
  (  G18 GND )
  (  G19 /FPGA_Spartan6/R_M1_A10 )
  (  G20 /FPGA_Spartan6/R_M1_A3 )
  (  G21 +2.5V )
  (  G22 ? )
  (   H1 /FPGA_Spartan6/R_M0_A1 )
  (   H2 /FPGA_Spartan6/R_M0_A0 )
  (   H3 /DDR_Banks/M0_CLK# )
  (   H4 /DDR_Banks/M0_CLK )
  (   H5 /FPGA_Spartan6/R_M0_A2 )
  (   H6 /FPGA_Spartan6/R_M0_A7 )
  (   H7 GND )
  (   H8 ? )
  (   H9 +2.5V )
  (  H10 ? )
  (  H11 ? )
  (  H12 ? )
  (  H13 ? )
  (  H14 ? )
  (  H15 +2.5V )
  (  H16 /FPGA_Spartan6/R_M1_CS# )
  (  H17 ? )
  (  H18 ? )
  (  H19 /FPGA_Spartan6/R_M1_WE# )
  (  H20 /FPGA_Spartan6/M1_CLK )
  (  H21 /FPGA_Spartan6/R_M1_RAS# )
  (  H22 /FPGA_Spartan6/R_M1_CAS# )
  (   J1 /FPGA_Spartan6/R_M0_DQ5 )
  (   J2 GND )
  (   J3 /FPGA_Spartan6/R_M0_DQ4 )
  (   J4 /FPGA_Spartan6/R_M0_A6 )
  (   J5 +2.5V )
  (   J6 ? )
  (   J7 ? )
  (   J8 +1.2V )
  (   J9 GND )
  (  J10 +1.2V )
  (  J11 GND )
  (  J12 +1.2V )
  (  J13 GND )
  (  J14 +1.2V )
  (  J15 GND )
  (  J16 ? )
  (  J17 /FPGA_Spartan6/R_M1_BA0 )
  (  J18 +2.5V )
  (  J19 /FPGA_Spartan6/M1_CLK# )
  (  J20 /FPGA_Spartan6/R_M1_DQ4 )
  (  J21 GND )
  (  J22 /FPGA_Spartan6/R_M1_DQ5 )
  (   K1 /FPGA_Spartan6/R_M0_DQ7 )
  (   K2 /FPGA_Spartan6/R_M0_DQ6 )
  (   K3 /FPGA_Spartan6/R_M0_A5 )
  (   K4 /FPGA_Spartan6/R_M0_CAS# )
  (   K5 /FPGA_Spartan6/R_M0_RAS# )
  (   K6 /FPGA_Spartan6/R_M0_A3 )
  (   K7 ? )
  (   K8 ? )
  (   K9 +1.2V )
  (  K10 GND )
  (  K11 +1.2V )
  (  K12 GND )
  (  K13 +1.2V )
  (  K14 GND )
  (  K15 +2.5V )
  (  K16 ? )
  (  K17 /FPGA_Spartan6/R_M1_BA1 )
  (  K18 ? )
  (  K19 /FPGA_Spartan6/R_M1_A6 )
  (  K20 /FPGA_Spartan6/R_M1_A5 )
  (  K21 /FPGA_Spartan6/R_M1_DQ6 )
  (  K22 /FPGA_Spartan6/R_M1_DQ7 )
  (   L1 ? )
  (   L2 +2.5V )
  (   L3 /FPGA_Spartan6/R_M0_LDQS )
  (   L4 /FPGA_Spartan6/R_M0_LDM )
  (   L5 GND )
  (   L6 ? )
  (   L7 +2.5V )
  (   L8 +2.5V )
  (   L9 GND )
  (  L10 +1.2V )
  (  L11 GND )
  (  L12 +1.2V )
  (  L13 GND )
  (  L14 +1.2V )
  (  L15 ? )
  (  L16 +2.5V )
  (  L17 ? )
  (  L18 GND )
  (  L19 /FPGA_Spartan6/R_M1_LDM )
  (  L20 /FPGA_Spartan6/R_M1_LDQS )
  (  L21 +2.5V )
  (  L22 ? )
  (   M1 /FPGA_Spartan6/R_M0_DQ3 )
  (   M2 /FPGA_Spartan6/R_M0_DQ2 )
  (   M3 /FPGA_Spartan6/R_M0_UDM )
  (   M4 ? )
  (   M5 ? )
  (   M6 ? )
  (   M7 ? )
  (   M8 ? )
  (   M9 +1.2V )
  (  M10 GND )
  (  M11 +1.2V )
  (  M12 GND )
  (  M13 +1.2V )
  (  M14 GND )
  (  M15 +2.5V )
  (  M16 ? )
  (  M17 ? )
  (  M18 ? )
  (  M19 ? )
  (  M20 /FPGA_Spartan6/R_M1_UDM )
  (  M21 /FPGA_Spartan6/R_M1_DQ2 )
  (  M22 /FPGA_Spartan6/R_M1_DQ3 )
  (   N1 /FPGA_Spartan6/R_M0_DQ1 )
  (   N2 GND )
  (   N3 /FPGA_Spartan6/R_M0_DQ0 )
  (   N4 ? )
  (   N5 +2.5V )
  (   N6 ? )
  (   N7 ? )
  (   N8 +2.5V )
  (   N9 GND )
  (  N10 +1.2V )
  (  N11 GND )
  (  N12 +1.2V )
  (  N13 GND )
  (  N14 +1.2V )
  (  N15 GND )
  (  N16 ? )
  (  N17 GND )
  (  N18 +2.5V )
  (  N19 ? )
  (  N20 /FPGA_Spartan6/R_M1_DQ0 )
  (  N21 GND )
  (  N22 /FPGA_Spartan6/R_M1_DQ1 )
  (   P1 /FPGA_Spartan6/R_M0_DQ9 )
  (   P2 /FPGA_Spartan6/R_M0_DQ8 )
  (   P3 ? )
  (   P4 ? )
  (   P5 ? )
  (   P6 ? )
  (   P7 ? )
  (   P8 ? )
  (   P9 +1.2V )
  (  P10 GND )
  (  P11 +1.2V )
  (  P12 GND )
  (  P13 +1.2V )
  (  P14 GND )
  (  P15 ? )
  (  P16 ? )
  (  P17 ? )
  (  P18 ? )
  (  P19 ? )
  (  P20 ? )
  (  P21 /FPGA_Spartan6/R_M1_DQ8 )
  (  P22 /FPGA_Spartan6/R_M1_DQ9 )
  (   R1 /FPGA_Spartan6/R_M0_DQ11 )
  (   R2 +2.5V )
  (   R3 /FPGA_Spartan6/R_M0_DQ10 )
  (   R4 ? )
  (   R5 GND )
  (   R6 +2.5V )
  (   R7 ? )
  (   R8 ? )
  (   R9 ? )
  (  R10 +2.5V )
  (  R11 ? )
  (  R12 +2.5V )
  (  R13 ? )
  (  R14 +1.2V )
  (  R15 ? )
  (  R16 ? )
  (  R17 ? )
  (  R18 GND )
  (  R19 ? )
  (  R20 /FPGA_Spartan6/R_M1_DQ10 )
  (  R21 +2.5V )
  (  R22 /FPGA_Spartan6/R_M1_DQ11 )
  (   T1 ? )
  (   T2 /FPGA_Spartan6/R_M0_UDQS )
  (   T3 ? )
  (   T4 ? )
  (   T5 /FPGA_Spartan6/PROG_CSO )
  (   T6 ? )
  (   T7 ? )
  (   T8 ? )
  (   T9 VCCO2 )
  (  T10 ? )
  (  T11 ? )
  (  T12 ? )
  (  T13 VCCO2 )
  (  T14 ? )
  (  T15 ? )
  (  T16 ? )
  (  T17 ? )
  (  T18 ? )
  (  T19 ? )
  (  T20 ? )
  (  T21 /FPGA_Spartan6/R_M1_UDQS )
  (  T22 ? )
  (   U1 /FPGA_Spartan6/R_M0_DQ13 )
  (   U2 GND )
  (   U3 /FPGA_Spartan6/R_M0_DQ12 )
  (   U4 ? )
  (   U5 +2.5V )
  (   U6 ? )
  (   U7 GND )
  (   U8 ? )
  (   U9 ? )
  (  U10 ? )
  (  U11 +2.5V )
  (  U12 ? )
  (  U13 /FPGA_Spartan6/PROG_MISO3 )
  (  U14 /FPGA_Spartan6/PROG_MISO2 )
  (  U15 ? )
  (  U16 ? )
  (  U17 ? )
  (  U18 +2.5V )
  (  U19 ? )
  (  U20 /FPGA_Spartan6/R_M1_DQ12 )
  (  U21 GND )
  (  U22 /FPGA_Spartan6/R_M1_DQ13 )
  (   V1 /FPGA_Spartan6/R_M0_DQ15 )
  (   V2 /FPGA_Spartan6/R_M0_DQ14 )
  (   V3 ? )
  (   V4 GND )
  (   V5 ? )
  (   V6 +2.5V )
  (   V7 ? )
  (   V8 VCCO2 )
  (   V9 ? )
  (  V10 GND )
  (  V11 ? )
  (  V12 VCCO2 )
  (  V13 ? )
  (  V14 GND )
  (  V15 ? )
  (  V16 VCCO2 )
  (  V17 ? )
  (  V18 ? )
  (  V19 ? )
  (  V20 ? )
  (  V21 /FPGA_Spartan6/R_M1_DQ14 )
  (  V22 /FPGA_Spartan6/R_M1_DQ15 )
  (   W1 ? )
  (   W2 +2.5V )
  (   W3 ? )
  (   W4 ? )
  (   W5 VCCO2 )
  (   W6 ? )
  (   W7 GND )
  (   W8 ? )
  (   W9 ? )
  (  W10 ? )
  (  W11 ? )
  (  W12 ? )
  (  W13 ? )
  (  W14 ? )
  (  W15 ? )
  (  W16 GND )
  (  W17 ? )
  (  W18 ? )
  (  W19 GND )
  (  W20 ? )
  (  W21 +2.5V )
  (  W22 ? )
  (   Y1 ? )
  (   Y2 ? )
  (   Y3 ? )
  (   Y4 ? )
  (   Y5 ? )
  (   Y6 ? )
  (   Y7 ? )
  (   Y8 ? )
  (   Y9 ? )
  (  Y10 ? )
  (  Y11 ? )
  (  Y12 ? )
  (  Y13 ? )
  (  Y14 ? )
  (  Y15 ? )
  (  Y16 ? )
  (  Y17 ? )
  (  Y18 ? )
  (  Y19 ? )
  (  Y20 +3.3V )
  (  Y21 ? )
  (  Y22 N-000261 )
 )
 ( /4C4320F3/4C5D8114 $noname  C9 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_PLL1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D810A 0402  L3 FB {Lib=INDUCTOR}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 /Ethernet_Phy/ETH_PLL1.8V )
 )
 ( /4C4320F3/4C5D8104 $noname  C6 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D80F3 0402  L1 FB {Lib=INDUCTOR}
  (    1 +1.8V )
  (    2 /Ethernet_Phy/ETH_A1.8V )
 )
 ( /4C4320F3/4C5D80F0 $noname  C4 100nF {Lib=C}
  (    1 +1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D80ED $noname  C2 1uF {Lib=C}
  (    1 +1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FB7 0402  L2 FB {Lib=INDUCTOR}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/ETH_A3.3V )
 )
 ( /4C4320F3/4C5D7FA7 $noname  C8 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA5 $noname  C7 1uF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA3 $noname  C5 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA1 $noname  C3 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F9F $noname  C1 1uF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F39 $noname  R1 4.7K {Lib=R}
  (    1 /Ethernet_Phy/ETH_MDIO )
  (    2 +3.3V )
 )
 ( /4C4320F3/4C5D7ECF $noname  R2 6.65K {Lib=R}
  (    1 N-000401 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E43 $noname  C11 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E41 $noname  C10 100nF {Lib=C}
  (    1 +3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DCB $noname  C12 47nF {Lib=C}
  (    1 /Ethernet_Phy/MAG_SHIELD )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DC4 $noname  R9 1M {Lib=R}
  (    1 /Ethernet_Phy/MAG_SHIELD )
  (    2 GND )
 )
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 /Ethernet_Phy/ETH_MDIO )
  (    2 /FPGA_Spartan6/ETH_MDC )
  (    3 /Ethernet_Phy/ETH_RXD3 )
  (    4 /FPGA_Spartan6/ETH_RXD2 )
  (    5 /Ethernet_Phy/ETH_RXD1 )
  (    6 /Ethernet_Phy/ETH_RXD0 )
  (    7 +3.3V )
  (    8 GND )
  (    9 /FPGA_Spartan6/ETH_RXDV )
  (   10 /Ethernet_Phy/ETH_RXC )
  (   11 /Ethernet_Phy/ETH_RXER )
  (   12 GND )
  (   13 +1.8V )
  (   14 /Ethernet_Phy/ETH_TXER )
  (   15 /Ethernet_Phy/ETH_TXC )
  (   16 /Ethernet_Phy/ETH_TXEN )
  (   17 /FPGA_Spartan6/ETH_TXD0 )
  (   18 /FPGA_Spartan6/ETH_TXD1 )
  (   19 /Ethernet_Phy/ETH_TXD2 )
  (   20 /FPGA_Spartan6/ETH_TXD3 )
  (   21 /FPGA_Spartan6/ETH_COL )
  (   22 /Ethernet_Phy/ETH_CRS )
  (   23 GND )
  (   24 +3.3V )
  (   25 /Ethernet_Phy/ETH_INT )
  (   26 /Ethernet_Phy/ETH_LED0 )
  (   27 /Ethernet_Phy/ETH_LED1 )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /Ethernet_Phy/ETH_A1.8V )
  (   32 /Ethernet_Phy/MAG_RX- )
  (   33 /Ethernet_Phy/MAG_RX+ )
  (   34 ? )
  (   35 GND )
  (   36 GND )
  (   37 N-000401 )
  (   38 /Ethernet_Phy/ETH_A3.3V )
  (   39 GND )
  (   40 /Ethernet_Phy/MAG_TX- )
  (   41 /Ethernet_Phy/MAG_TX+ )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 ? )
  (   46 /Ethernet_Phy/ETH_CLK )
  (   47 /Ethernet_Phy/ETH_PLL1.8V )
  (   48 /FPGA_Spartan6/ETH_RESET_N )
 )
 ( /4C4320F3/4C5D7AFE $noname  R3 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_TX+ )
 )
 ( /4C4320F3/4C5D7AFC $noname  R4 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_TX- )
 )
 ( /4C4320F3/4C5D7AF9 $noname  R6 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_RX- )
 )
 ( /4C4320F3/4C5D7AF7 $noname  R5 49.9 {Lib=R}
  (    1 +3.3V )
  (    2 /Ethernet_Phy/MAG_RX+ )
 )
 ( /4C4320F3/4C5D71DB $noname  R8 220 {Lib=R}
  (    1 N-000404 )
  (    2 /Ethernet_Phy/ETH_LED1 )
 )
 ( /4C4320F3/4C5D719D $noname  R7 220 {Lib=R}
  (    1 N-000405 )
  (    2 /Ethernet_Phy/ETH_LED0 )
 )
 ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
  (    1 /Ethernet_Phy/MAG_TX+ )
  (    2 /Ethernet_Phy/MAG_TX- )
  (    3 +3.3V )
  (    4 GND )
  (    5 GND )
  (    6 +3.3V )
  (    7 /Ethernet_Phy/MAG_RX+ )
  (    8 /Ethernet_Phy/MAG_RX- )
  (    9 +3.3V )
  (   10 N-000405 )
  (   11 +3.3V )
  (   12 N-000404 )
  (   13 /Ethernet_Phy/MAG_SHIELD )
  (   14 /Ethernet_Phy/MAG_SHIELD )
 )
 ( /4C421DD3/4C609C8E $noname  U3 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /FPGA_Spartan6/M1_DQ0 )
  (    3 +2.5V )
  (    4 /DDR_Banks/M1_DQ1 )
  (    5 /FPGA_Spartan6/M1_DQ2 )
  (    6 GND )
  (    7 /FPGA_Spartan6/M1_DQ3 )
  (    8 /FPGA_Spartan6/M1_DQ4 )
  (    9 +2.5V )
  (   10 /FPGA_Spartan6/M1_DQ5 )
  (   11 /DDR_Banks/M1_DQ6 )
  (   12 GND )
  (   13 /DDR_Banks/M1_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /DDR_Banks/M1_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M1_LDM )
  (   21 /DDR_Banks/M1_WE# )
  (   22 /FPGA_Spartan6/M1_CAS# )
  (   23 /FPGA_Spartan6/M1_RAS# )
  (   24 /DDR_Banks/M1_CS# )
  (   25 ? )
  (   26 /DDR_Banks/M1_BA0 )
  (   27 /FPGA_Spartan6/M1_BA1 )
  (   28 /FPGA_Spartan6/M1_A10 )
  (   29 /FPGA_Spartan6/M1_A0 )
  (   30 /DDR_Banks/M1_A1 )
  (   31 /FPGA_Spartan6/M1_A2 )
  (   32 /FPGA_Spartan6/M1_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /FPGA_Spartan6/M1_A4 )
  (   36 /DDR_Banks/M1_A5 )
  (   37 /DDR_Banks/M1_A6 )
  (   38 /FPGA_Spartan6/M1_A7 )
  (   39 /DDR_Banks/M1_A8 )
  (   40 /DDR_Banks/M1_A9 )
  (   41 /FPGA_Spartan6/M1_A11 )
  (   42 /FPGA_Spartan6/M1_A12 )
  (   43 ? )
  (   44 /FPGA_Spartan6/M1_CLK# )
  (   45 /FPGA_Spartan6/M1_CKE )
  (   46 /FPGA_Spartan6/M1_CLK )
  (   47 /DDR_Banks/M1_UDM )
  (   48 GND )
  (   49 /DDR_Banks/M1_VREF )
  (   50 ? )
  (   51 /DDR_Banks/M1_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M1_DQ8 )
  (   55 +2.5V )
  (   56 /DDR_Banks/M1_DQ9 )
  (   57 /DDR_Banks/M1_DQ10 )
  (   58 GND )
  (   59 /DDR_Banks/M1_DQ11 )
  (   60 /DDR_Banks/M1_DQ12 )
  (   61 +2.5V )
  (   62 /FPGA_Spartan6/M1_DQ13 )
  (   63 /DDR_Banks/M1_DQ14 )
  (   64 GND )
  (   65 /FPGA_Spartan6/M1_DQ15 )
  (   66 GND )
 )
 ( /4C421DD3/4C65D2A9 0402  C70 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C65D28E 0402  C71 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61D1D4 1206  C34 10uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61D151 1206  C33 10uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA5 0402  C28 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA4 0402  C29 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA3 0402  C31 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA2 0402  C30 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA1 0402  C32 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA0 0603  C27 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF2F 0603  C21 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF27 0402  C26 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF17 0402  C24 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF16 0402  C25 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEF7 0402  C23 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEB9 0402  C22 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CE31 0402  R13 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 /DDR_Banks/M1_VREF )
 )
 ( /4C421DD3/4C61CE30 0402  R14 1K_1% {Lib=R}
  (    1 /DDR_Banks/M1_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CDB5 0402  R12 1K_1% {Lib=R}
  (    1 /DDR_Banks/M0_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CD4A 0402  R11 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_VREF )
 )
 ( /4C421DD3/4C61CCE3 0402  C19 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 /DDR_Banks/M1_VREF )
 )
 ( /4C421DD3/4C61CCE2 0402  C20 100nF {Lib=CAP}
  (    1 /DDR_Banks/M1_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CC96 0402  C18 100nF {Lib=CAP}
  (    1 /DDR_Banks/M0_VREF )
  (    2 GND )
 )
 ( /4C421DD3/4C61CC73 0402  C17 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_VREF )
 )
 ( /4C421DD3/4C609B99 $noname  U2 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_DQ0 )
  (    3 +2.5V )
  (    4 /DDR_Banks/M0_DQ1 )
  (    5 /FPGA_Spartan6/M0_DQ2 )
  (    6 GND )
  (    7 /FPGA_Spartan6/M0_DQ3 )
  (    8 /DDR_Banks/M0_DQ4 )
  (    9 +2.5V )
  (   10 /FPGA_Spartan6/M0_DQ5 )
  (   11 /FPGA_Spartan6/M0_DQ6 )
  (   12 GND )
  (   13 /DDR_Banks/M0_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /DDR_Banks/M0_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M0_LDM )
  (   21 /DDR_Banks/M0_WE# )
  (   22 /DDR_Banks/M0_CAS# )
  (   23 /DDR_Banks/M0_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 /DDR_Banks/M0_BA0 )
  (   27 /FPGA_Spartan6/M0_BA1 )
  (   28 /DDR_Banks/M0_A10 )
  (   29 /FPGA_Spartan6/M0_A0 )
  (   30 /DDR_Banks/M0_A1 )
  (   31 /FPGA_Spartan6/M0_A2 )
  (   32 /DDR_Banks/M0_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /FPGA_Spartan6/M0_A4 )
  (   36 /DDR_Banks/M0_A5 )
  (   37 /DDR_Banks/M0_A6 )
  (   38 /DDR_Banks/M0_A7 )
  (   39 /FPGA_Spartan6/M0_A8 )
  (   40 /FPGA_Spartan6/M0_A9 )
  (   41 /FPGA_Spartan6/M0_A11 )
  (   42 /FPGA_Spartan6/M0_A12 )
  (   43 ? )
  (   44 /DDR_Banks/M0_CLK# )
  (   45 /DDR_Banks/M0_CKE )
  (   46 /DDR_Banks/M0_CLK )
  (   47 /DDR_Banks/M0_UDM )
  (   48 GND )
  (   49 /DDR_Banks/M0_VREF )
  (   50 ? )
  (   51 /FPGA_Spartan6/M0_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /FPGA_Spartan6/M0_DQ8 )
  (   55 +2.5V )
  (   56 /DDR_Banks/M0_DQ9 )
  (   57 /FPGA_Spartan6/M0_DQ10 )
  (   58 GND )
  (   59 /FPGA_Spartan6/M0_DQ11 )
  (   60 /FPGA_Spartan6/M0_DQ12 )
  (   61 +2.5V )
  (   62 /FPGA_Spartan6/M0_DQ13 )
  (   63 /FPGA_Spartan6/M0_DQ14 )
  (   64 GND )
  (   65 /FPGA_Spartan6/M0_DQ15 )
  (   66 GND )
 )
)
*
{ Allowed footprints by component:
$component C95
 SM*
 C?
 C1-1
$endlist
$component R35
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R36
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C98
 SM*
 C?
 C1-1
$endlist
$component R39
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R38
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C97
 SM*
 C?
 C1-1
$endlist
$component C96
 SM*
 C?
 C1-1
$endlist
$component R37
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R34
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R33
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R31
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R32
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C82
 SM*
 C?
 C1-1
$endlist
$component C83
 SM*
 C?
 C1-1
$endlist
$component C84
 SM*
 C?
 C1-1
$endlist
$component R27
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R28
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C85
 SM*
 C?
 C1-1
$endlist
$component C81
 SM*
 C?
 C1-1
$endlist
$component R26
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R25
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C80
 SM*
 C?
 C1-1
$endlist
$component C79
 SM*
 C?
 C1-1
$endlist
$component C78
 SM*
 C?
 C1-1
$endlist
$component C75
 SM*
 C?
 C1-1
$endlist
$component C74
 SM*
 C?
 C1-1
$endlist
$component C73
 SM*
 C?
 C1-1
$endlist
$component C72
 SM*
 C?
 C1-1
$endlist
$component C35
 SM*
 C?
 C1-1
$endlist
$component C36
 SM*
 C?
 C1-1
$endlist
$component C37
 SM*
 C?
 C1-1
$endlist
$component C38
 SM*
 C?
 C1-1
$endlist
$component R15
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R10
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C16
 SM*
 C?
 C1-1
$endlist
$component C15
 SM*
 C?
 C1-1
$endlist
$component C14
 SM*
 C?
 C1-1
$endlist
$component C13
 SM*
 C?
 C1-1
$endlist
$component C94
 SM*
 C?
 C1-1
$endlist
$component C92
 SM*
 C?
 C1-1
$endlist
$component C93
 SM*
 C?
 C1-1
$endlist
$component C91
 SM*
 C?
 C1-1
$endlist
$component C90
 SM*
 C?
 C1-1
$endlist
$component R30
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R29
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C77
 SM*
 C?
 C1-1
$endlist
$component C76
 SM*
 C?
 C1-1
$endlist
$component R23
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R22
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R24
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R21
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R19
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R20
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R17
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R18
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R16
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C66
 SM*
 C?
 C1-1
$endlist
$component C63
 SM*
 C?
 C1-1
$endlist
$component C60
 SM*
 C?
 C1-1
$endlist
$component C57
 SM*
 C?
 C1-1
$endlist
$component C54
 SM*
 C?
 C1-1
$endlist
$component C69
 SM*
 C?
 C1-1
$endlist
$component C67
 SM*
 C?
 C1-1
$endlist
$component C64
 SM*
 C?
 C1-1
$endlist
$component C61
 SM*
 C?
 C1-1
$endlist
$component C58
 SM*
 C?
 C1-1
$endlist
$component C55
 SM*
 C?
 C1-1
$endlist
$component C68
 SM*
 C?
 C1-1
$endlist
$component C65
 SM*
 C?
 C1-1
$endlist
$component C62
 SM*
 C?
 C1-1
$endlist
$component C59
 SM*
 C?
 C1-1
$endlist
$component C56
 SM*
 C?
 C1-1
$endlist
$component C50
 SM*
 C?
 C1-1
$endlist
$component C47
 SM*
 C?
 C1-1
$endlist
$component C44
 SM*
 C?
 C1-1
$endlist
$component C41
 SM*
 C?
 C1-1
$endlist
$component C53
 SM*
 C?
 C1-1
$endlist
$component C51
 SM*
 C?
 C1-1
$endlist
$component C49
 SM*
 C?
 C1-1
$endlist
$component C46
 SM*
 C?
 C1-1
$endlist
$component C52
 SM*
 C?
 C1-1
$endlist
$component C43
 SM*
 C?
 C1-1
$endlist
$component C40
 SM*
 C?
 C1-1
$endlist
$component C48
 SM*
 C?
 C1-1
$endlist
$component C45
 SM*
 C?
 C1-1
$endlist
$component C42
 SM*
 C?
 C1-1
$endlist
$component C39
 SM*
 C?
 C1-1
$endlist
$component C9
 SM*
 C?
 C1-1
$endlist
$component C6
 SM*
 C?
 C1-1
$endlist
$component C4
 SM*
 C?
 C1-1
$endlist
$component C2
 SM*
 C?
 C1-1
$endlist
$component C8
 SM*
 C?
 C1-1
$endlist
$component C7
 SM*
 C?
 C1-1
$endlist
$component C5
 SM*
 C?
 C1-1
$endlist
$component C3
 SM*
 C?
 C1-1
$endlist
$component C1
 SM*
 C?
 C1-1
$endlist
$component R1
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R2
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C11
 SM*
 C?
 C1-1
$endlist
$component C10
 SM*
 C?
 C1-1
$endlist
$component C12
 SM*
 C?
 C1-1
$endlist
$component R9
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R3
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R4
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R6
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R5
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R8
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R7
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C70
 SM*
 C?
 C1-1
$endlist
$component C71
 SM*
 C?
 C1-1
$endlist
$component C34
 SM*
 C?
 C1-1
$endlist
$component C33
 SM*
 C?
 C1-1
$endlist
$component C28
 SM*
 C?
 C1-1
$endlist
$component C29
 SM*
 C?
 C1-1
$endlist
$component C31
 SM*
 C?
 C1-1
$endlist
$component C30
 SM*
 C?
 C1-1
$endlist
$component C32
 SM*
 C?
 C1-1
$endlist
$component C27
 SM*
 C?
 C1-1
$endlist
$component C21
 SM*
 C?
 C1-1
$endlist
$component C26
 SM*
 C?
 C1-1
$endlist
$component C24
 SM*
 C?
 C1-1
$endlist
$component C25
 SM*
 C?
 C1-1
$endlist
$component C23
 SM*
 C?
 C1-1
$endlist
$component C22
 SM*
 C?
 C1-1
$endlist
$component R13
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R14
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R12
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R11
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C19
 SM*
 C?
 C1-1
$endlist
$component C20
 SM*
 C?
 C1-1
$endlist
$component C18
 SM*
 C?
 C1-1
$endlist
$component C17
 SM*
 C?
 C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO"
 U8 1
 U1 T5
Net 2 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK"
 U1 AA21
 U8 6
Net 3 "/FPGA Spartan6/NF_RNB" "NF_RNB"
 U5 6
 U5 7
 U1 A15
Net 4 "/Non volatile memories/NF_RE_N" "NF_RE_N"
 U1 C15
 U5 8
Net 5 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N"
 U5 9
 U1 D15
Net 6 "/FPGA Spartan6/NF_CLE" "NF_CLE"
 U5 16
 U1 B14
Net 7 "/Non volatile memories/NF_WE_N" "NF_WE_N"
 U1 C14
 U5 18
Net 8 "/FPGA Spartan6/ETH_COL" "ETH_COL"
 U4 21
 U1 A9
Net 9 "/USB/USBD_VM" "USBD_VM"
 U7 4
 U1 B22
Net 10 "/FPGA Spartan6/USBD_RCV" "USBD_RCV"
 U7 2
 U1 A20
Net 11 "/USB/USBD_OE_N" "USBD_OE_N"
 U7 9
 U1 A21
Net 12 "/FPGA Spartan6/USBD_SPD" "USBD_SPD"
 U7 1
 U1 B20
Net 13 "/USB/USBD_VP" "USBD_VP"
 U1 B21
 U7 3
Net 14 "/Ethernet Phy/ETH_TXC" "ETH_TXC"
 U4 15
 U1 C8
Net 15 "/Ethernet Phy/ETH_RXC" "ETH_RXC"
 U4 10
 U1 A7
Net 16 "/USB/USBA_SPD" "USBA_SPD"
 U6 1
 U1 F16
Net 17 "/USB/USBA_OE_N" "USBA_OE_N"
 U6 9
 U1 C19
Net 18 "/FPGA Spartan6/USBA_RCV" "USBA_RCV"
 U6 2
 U1 F17
Net 19 "/USB/USBA_VP" "USBA_VP"
 U6 3
 U1 D19
Net 20 "/FPGA Spartan6/USBA_VM" "USBA_VM"
 U6 4
 U1 D20
Net 21 "/Ethernet Phy/ETH_CRS" "ETH_CRS"
 U4 22
 U1 B10
Net 22 "/FPGA Spartan6/SD_CMD" "SD_CMD"
 U1 C16
 J1 3
Net 23 "/FPGA Spartan6/ETH_MDC" "ETH_MDC"
 U4 2
 U1 D7
Net 24 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO"
 U1 D6
 R1 1
 U4 1
Net 25 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
 U1 C7
 U4 48
Net 26 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV"
 U4 9
 U1 A6
Net 27 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
 U4 11
 U1 B8
Net 28 "/DDR Banks/M1_CS#" "M1_CS#"
 U3 24
 R20 2
Net 29 "/DDR Banks/M1_UDM" "M1_UDM"
 R18 2
 U3 47
Net 30 "/DDR Banks/M1_LDQS" "M1_LDQS"
 RP3 8
 U3 16
Net 31 "/DDR Banks/M1_LDM" "M1_LDM"
 RP3 7
 U3 20
Net 32 "/DDR Banks/M1_UDQS" "M1_UDQS"
 R19 2
 U3 51
Net 33 "/FPGA Spartan6/M0_UDQS" "M0_UDQS"
 U2 51
 R22 2
Net 34 "/DDR Banks/M0_LDM" "M0_LDM"
 RP16 7
 U2 20
Net 35 "/FPGA Spartan6/M1_CKE" "M1_CKE"
 U3 45
 R17 2
Net 36 "/FPGA Spartan6/M1_CLK" "M1_CLK"
 U3 46
 R16 2
 U1 H20
Net 37 "/FPGA Spartan6/M1_CLK#" "M1_CLK#"
 R16 1
 U3 44
 U1 J19
Net 38 "GND" "GND"
 U2 66
 C22 2
 C20 2
 R12 2
 C18 2
 U2 64
 R14 2
 C32 2
 C30 2
 C31 2
 C29 2
 C28 2
 C33 2
 C23 2
 C25 2
 C24 2
 C26 2
 C21 2
 C93 2
 C91 2
 C90 2
 C76 2
 C77 2
 U2 34
 U2 24
 U2 52
 U2 12
 C27 2
 U3 58
 C34 2
 C71 2
 C70 2
 U1 N21
 U1 U21
 U1 AB1
 U1 K12
 U1 M12
 U1 P12
 U1 A22
 U1 B13
 C72 2
 U1 V4
 U1 B5
 U1 G5
 U1 L5
 U1 R5
 U1 M14
 U1 K14
 U1 N13
 U1 L13
 U1 J13
 U1 P14
 U1 V14
 U1 E15
 U1 J15
 U1 N15
 U1 AA5
 U1 E11
 U1 J11
 U1 L11
 U1 N11
 U1 E21
 U1 J21
 C43 2
 C40 2
 C66 2
 C63 2
 C60 2
 C57 2
 C54 2
 C69 2
 C67 2
 C64 2
 C61 2
 C58 2
 C55 2
 C68 2
 C48 2
 C45 2
 C42 2
 C39 2
 C73 2
 U8 4
 C41 2
 C74 2
 C44 2
 C47 2
 C50 2
 C75 1
 C56 2
 C59 2
 C62 2
 C65 2
 C53 2
 C51 2
 C49 2
 C46 2
 C52 2
 J1 CASE
 J1 CASE
 J1 CASE
 J1 COM
 J1 6
 U2 6
 U1 W19
 U1 R18
 U5 36
 U1 L18
 U1 G18
 U1 D18
 U1 N17
 U1 B17
 U1 W16
 U1 J9
 U1 B9
 U1 W7
 U1 U7
 U1 H7
 U1 E7
 U1 L9
 U1 N9
 U1 K10
 U1 M10
 U1 P10
 U1 V10
 U1 A1
 U1 E2
 U1 J2
 U1 N2
 U1 U2
 U1 D4
 U5 13
 U1 AA17
 U1 AA13
 U1 AB22
 U1 AA9
 U7 6
 U7 7
 U6 6
 U6 7
 V1 2
 V2 2
 C15 2
 C14 2
 C13 2
 L7 2
 L5 2
 R10 2
 C16 2
 U3 64
 U3 34
 U3 52
 U3 12
 U3 48
 C9 2
 C6 2
 C4 2
 C2 2
 U11 2
 U9 PAD
 U9 8
 C81 2
 C85 2
 U12 2
 C78 2
 C80 2
 R25 2
 U13 5
 R31 2
 R33 2
 R27 2
 C84 2
 C82 2
 C97 2
 R38 2
 C98 2
 U14 5
 U15 2
 U10 PAD
 U10 5
 U10 2
 C95 2
 C37 2
 C36 2
 C35 2
 V4 2
 V3 2
 C38 2
 R15 2
 U16 5
 R35 2
 C5 2
 C3 2
 C1 2
 U4 44
 R2 2
 C11 2
 C10 2
 C12 2
 R9 2
 C8 2
 C7 2
 U4 12
 U4 35
 U4 36
 U4 8
 U4 23
 U3 6
 U3 66
 C94 2
 C92 2
 U2 48
 U2 58
 J4 4
 J4 5
 U4 39
Net 39 "/DDR Banks/M0_CLK#" "M0_CLK#"
 R21 2
 U1 H3
 U2 44
Net 40 "/DDR Banks/M0_CLK" "M0_CLK"
 U1 H4
 R21 1
 U2 46
Net 41 "/DDR Banks/M0_CKE" "M0_CKE"
 R24 2
 U2 45
Net 42 "/DDR Banks/M0_CAS#" "M0_CAS#"
 RP16 5
 U2 22
Net 43 "/DDR Banks/M1_WE#" "M1_WE#"
 U3 21
 RP3 6
Net 44 "/FPGA Spartan6/M1_RAS#" "M1_RAS#"
 RP2 8
 U3 23
Net 45 "/DDR Banks/M0_RAS#" "M0_RAS#"
 U2 23
 RP15 8
Net 46 "/DDR Banks/M0_WE#" "M0_WE#"
 U2 21
 RP16 6
Net 47 "/Ethernet Phy/ETH_INT" "ETH_INT"
 U4 25
 U1 A10
Net 48 "/Ethernet Phy/ETH_CLK" "ETH_CLK"
 U1 A4
 U4 46
Net 49 "/Ethernet Phy/ETH_TXER" "ETH_TXER"
 U1 D8
 U4 14
Net 50 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
 U4 16
 U1 D9
Net 51 "/DDR Banks/M0_LDQS" "M0_LDQS"
 U2 16
 RP16 8
Net 52 "/DDR Banks/M0_UDM" "M0_UDM"
 U2 47
 R23 2
Net 53 "/FPGA Spartan6/M1_CAS#" "M1_CAS#"
 U3 22
 RP3 5
Net 54 "/Non volatile memories/NF_ALE" "NF_ALE"
 U5 17
 U1 A14
Net 55 "/FPGA Spartan6/SD_CLK" "SD_CLK"
 J1 5
 U1 A17
Net 56 "/DBG_PRG/FPGA_TCK" "FPGA_TCK"
 J6 1
 U1 G15
Net 57 "/DBG_PRG/FPGA_TMS" "FPGA_TMS"
 U1 C18
 J6 3
Net 58 "/DBG_PRG/FPGA_TDI" "FPGA_TDI"
 J6 7
 U1 E18
Net 59 "/DBG_PRG/FPGA_TDO" "FPGA_TDO"
 J6 5
 U1 A19
Net 64 "+2.5V" "+2.5V"
 C66 1
 C40 1
 C43 1
 U2 33
 C52 1
 C63 1
 C60 1
 C57 1
 C54 1
 C70 1
 C71 1
 C15 1
 C34 1
 U2 15
 U2 55
 U6 15
 C56 1
 C19 1
 C59 1
 C62 1
 U2 18
 U2 61
 U1 E19
 C53 1
 C51 1
 C49 1
 C46 1
 C23 1
 U1 J18
 U1 L16
 C22 1
 C33 1
 C28 1
 C29 1
 C31 1
 C30 1
 C68 1
 C65 1
 U1 U18
 U1 N18
 C21 1
 C26 1
 C24 1
 C25 1
 U1 D16
 U1 C21
 U1 G21
 U1 L21
 U1 R21
 U1 W21
 U1 F4
 U1 V6
 U1 R10
 U1 R6
 U1 L8
 U1 N8
 U1 H9
 U1 H15
 U1 K15
 U1 C2
 U1 G2
 U1 L2
 U1 R2
 U1 M15
 U1 W2
 U2 9
 U1 F11
 U1 U11
 U1 G12
 U1 R12
 U7 15
 R13 1
 R11 1
 U1 J5
 U1 N5
 C37 1
 U1 U5
 U1 F6
 U1 L7
 C17 1
 U2 1
 U2 3
 U3 61
 U3 9
 U3 3
 U3 33
 U3 18
 U3 55
 U3 1
 U3 15
 C77 1
 C94 1
 C32 1
 C27 1
Net 67 "/DDR Banks/M0_VREF" "M0_VREF"
 R12 1
 R11 2
 U2 49
 C18 1
 C17 2
Net 68 "/DDR Banks/M1_VREF" "M1_VREF"
 C20 1
 C19 2
 R14 1
 R13 2
 U3 49
Net 107 "+3.3V" "+3.3V"
 C10 1
 C11 1
 R30 1
 R1 2
 L2 1
 C5 1
 C3 1
 C1 1
 U4 24
 U1 B4
 U1 B19
 U1 E17
 U1 B15
 U5 12
 R29 1
 U5 37
 U5 19
 U1 Y20
 U4 7
 U6 14
 U6 12
 U7 14
 U7 12
 C91 1
 C13 1
 C14 1
 C35 1
 C36 1
 J1 4
 R3 1
 R4 1
 R6 1
 R5 1
 C90 1
 J4 3
 J4 6
 J4 9
 J4 11
 U1 G14
 U1 E13
 U1 B11
 U1 G10
 C80 1
 U1 E9
 C79 1
 U1 B7
 C73 1
 C72 1
 C81 1
 L8 1
 C50 1
 C75 2
 C47 1
 C44 1
 C74 1
 C41 1
 R26 1
Net 108 "VCCO2" "VCCO2"
 U1 T13
 C55 1
 C58 1
 U1 T9
 U1 V8
 U1 V12
 U8 8
 U1 AA11
 U1 AA15
 C69 1
 U1 AA19
 C67 1
 U1 AA3
 U1 W5
 U1 V16
 C64 1
 U1 AA7
 C61 1
Net 109 "+1.2V" "+1.2V"
 U1 K9
 C84 1
 C76 1
 C48 1
 C92 1
 U1 J8
 C42 1
 C39 1
 C45 1
 C83 1
 U1 M9
 U1 P9
 U1 J10
 C93 1
 U1 L10
 U1 N10
 U1 K11
 U1 M11
 U1 P11
 U1 J12
 U1 L12
 U1 N12
 R28 1
 U1 K13
 U1 M13
 U1 P13
 L9 1
 C85 1
 U1 N14
 U1 R14
 U1 J14
 U1 L14
Net 110 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#"
 U1 H19
 RP3 3
Net 111 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM"
 U1 L19
 RP3 2
Net 112 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS"
 U1 L20
 RP3 1
Net 113 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#"
 U1 H16
 R20 1
Net 114 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1"
 U1 K17
 RP2 3
Net 115 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0"
 U1 J17
 RP2 2
Net 131 "/FPGA Spartan6/R_M0_A3" "R_M0_A3"
 U1 K6
 RP14 4
Net 133 "/FPGA Spartan6/R_M0_A7" "R_M0_A7"
 RP17 1
 U1 H6
Net 138 "/FPGA Spartan6/R_M0_A2" "R_M0_A2"
 RP14 3
 U1 H5
Net 140 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14"
 RP8 7
 U1 V21
Net 141 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS"
 R19 1
 U1 T21
Net 142 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8"
 RP9 5
 U1 P21
Net 143 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2"
 RP5 3
 U1 M21
Net 144 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6"
 U1 K21
 RP4 3
Net 145 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#"
 RP2 1
 U1 H21
Net 146 "/FPGA Spartan6/R_M1_A0" "R_M1_A0"
 RP1 1
 U1 F21
Net 147 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE"
 R17 1
 U1 D21
Net 148 "/FPGA Spartan6/R_M1_A8" "R_M1_A8"
 RP7 5
 U1 C20
Net 149 "/FPGA Spartan6/R_M1_A7" "R_M1_A7"
 RP6 8
 U1 E20
Net 150 "/FPGA Spartan6/R_M1_A4" "R_M1_A4"
 RP6 5
 U1 F20
Net 151 "/FPGA Spartan6/R_M1_A3" "R_M1_A3"
 U1 G20
 RP1 4
Net 152 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4"
 RP4 1
 U1 J20
Net 153 "/FPGA Spartan6/R_M1_A5" "R_M1_A5"
 RP6 6
 U1 K20
Net 154 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM"
 R18 1
 U1 M20
Net 155 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0"
 U1 N20
 RP5 1
Net 157 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10"
 U1 R20
 RP9 7
Net 159 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12"
 RP8 5
 U1 U20
Net 164 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14"
 U1 V2
 RP10 3
Net 165 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS"
 R22 1
 U1 T2
Net 166 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8"
 RP11 1
 U1 P2
Net 167 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2"
 U1 M2
 RP13 3
Net 168 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6"
 U1 K2
 RP12 3
Net 169 "/FPGA Spartan6/R_M0_A0" "R_M0_A0"
 RP14 1
 U1 H2
Net 174 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15"
 U1 V1
 RP10 4
Net 175 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13"
 U1 U1
 RP10 2
Net 177 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11"
 RP11 4
 U1 R1
Net 178 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9"
 RP11 2
 U1 P1
Net 179 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1"
 U1 N1
 RP13 2
Net 180 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3"
 U1 M1
 RP13 4
Net 182 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7"
 RP12 4
 U1 K1
Net 183 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5"
 U1 J1
 RP12 2
Net 184 "/FPGA Spartan6/R_M0_A1" "R_M0_A1"
 RP14 2
 U1 H1
Net 185 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1"
 U1 G1
 RP15 3
Net 195 "/FPGA Spartan6/R_M0_A6" "R_M0_A6"
 U1 J4
 RP17 2
Net 196 "/FPGA Spartan6/R_M0_A10" "R_M0_A10"
 U1 G4
 RP15 4
Net 201 "/FPGA Spartan6/R_M0_A8" "R_M0_A8"
 U1 E3
 RP18 4
Net 202 "/FPGA Spartan6/R_M0_A4" "R_M0_A4"
 RP17 4
 U1 F3
Net 203 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0"
 U1 G3
 RP15 2
Net 204 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4"
 U1 J3
 RP12 1
Net 205 "/FPGA Spartan6/R_M0_A5" "R_M0_A5"
 U1 K3
 RP17 3
Net 206 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS"
 RP16 1
 U1 L3
Net 207 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0"
 RP13 1
 U1 N3
Net 209 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10"
 U1 R3
 RP11 3
Net 211 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12"
 RP10 1
 U1 U3
Net 228 "/FPGA Spartan6/R_M1_A9" "R_M1_A9"
 U1 C22
 RP7 6
Net 229 "/FPGA Spartan6/R_M1_A12" "R_M1_A12"
 U1 D22
 RP7 8
Net 230 "/FPGA Spartan6/R_M1_A2" "R_M1_A2"
 RP1 3
 U1 E22
Net 231 "/FPGA Spartan6/R_M1_A1" "R_M1_A1"
 U1 F22
 RP1 2
Net 233 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#"
 RP3 4
 U1 H22
Net 234 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5"
 RP4 2
 U1 J22
Net 235 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7"
 U1 K22
 RP4 4
Net 237 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3"
 U1 M22
 RP5 4
Net 238 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1"
 U1 N22
 RP5 2
Net 239 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9"
 RP9 6
 U1 P22
Net 240 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11"
 RP9 8
 U1 R22
Net 242 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13"
 U1 U22
 RP8 6
Net 243 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15"
 RP8 8
 U1 V22
Net 258 "/FPGA Spartan6/R_M1_A11" "R_M1_A11"
 U1 F19
 RP7 7
Net 259 "/FPGA Spartan6/R_M1_A10" "R_M1_A10"
 U1 G19
 RP2 4
Net 260 "/FPGA Spartan6/R_M1_A6" "R_M1_A6"
 U1 K19
 RP6 7
Net 261 "" ""
 U1 Y22
 R30 2
Net 314 "/FPGA Spartan6/R_M0_A9" "R_M0_A9"
 U1 E1
 RP18 3
Net 315 "/FPGA Spartan6/R_M0_A12" "R_M0_A12"
 RP18 1
 U1 D1
Net 316 "/FPGA Spartan6/R_M0_A11" "R_M0_A11"
 U1 C1
 RP18 2
Net 385 "" ""
 U1 AA1
 R29 2
Net 386 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#"
 U1 K4
 RP16 4
Net 387 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#"
 U1 F2
 RP16 3
Net 388 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM"
 U1 L4
 RP16 2
Net 389 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#"
 U1 K5
 RP15 1
Net 390 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE"
 U1 D2
 R24 1
Net 391 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM"
 U1 M3
 R23 1
Net 399 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
 L2 2
 C8 1
 C7 1
 U4 38
Net 400 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD"
 J4 14
 J4 13
 C12 1
 R9 1
Net 401 "" ""
 R2 1
 U4 37
Net 402 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
 R7 2
 U4 26
Net 403 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
 R8 2
 U4 27
Net 404 "" ""
 R8 1
 J4 12
Net 405 "" ""
 R7 1
 J4 10
Net 406 "/Ethernet Phy/MAG_RX-" "MAG_RX-"
 R6 2
 J4 8
 U4 32
Net 407 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
 C9 1
 U4 47
 L3 2
Net 408 "/Ethernet Phy/MAG_TX-" "MAG_TX-"
 U4 40
 R4 2
 J4 2
Net 409 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
 U4 33
 R5 2
 J4 7
Net 410 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
 R3 2
 U4 41
 J4 1
Net 411 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
 L3 1
 C6 1
 U4 31
 L1 2
Net 412 "+1.8V" "+1.8V"
 U4 13
 C2 1
 C4 1
 L1 1
Net 413 "" ""
 L7 1
 J7 1
Net 414 "" ""
 J7 4
 J7 5
Net 415 "/USB/USBD_D-" "USBD_D-"
 U7 10
 V4 1
 V4 1
 J7 2
Net 416 "/USB/USBA_D-" "USBA_D-"
 J5 2
 V2 1
 V2 1
 U6 10
Net 417 "" ""
 F1 1
 L4 1
Net 418 "" ""
 L5 1
 J5 4
Net 419 "+5V" "+5V"
 C98 1
 R39 1
 C97 1
 U15 5
 C96 1
 F1 2
Net 420 "/USB/USBA_D+" "USBA_D+"
 J5 3
 V1 1
 U6 11
 V1 1
Net 421 "" ""
 J5 S4
 R10 1
 C16 1
 J5 S1
 J5 S3
 J5 S2
Net 422 "" ""
 L4 2
 J5 1
Net 423 "/USB/USBD_D+" "USBD_D+"
 V3 1
 V3 1
 U7 11
 J7 3
Net 424 "" ""
 C38 1
 R15 1
 J7 9
 J7 8
 J7 7
 J7 6
Net 425 "" ""
 U14 1
 R34 2
Net 426 "" ""
 U13 1
 R32 2
Net 427 "/PSU/Iout_3.3" "Iout_3.3"
 R31 1
 U9 4
 U13 3
Net 428 "" ""
 L10 1
 U15 1
Net 429 "/PSU/VFB1.2" "VFB1.2"
 R28 2
 C96 2
 U12 5
 C83 2
 R38 1
 R39 2
 R27 1
 U15 3
Net 430 "" ""
 U16 1
 R36 2
Net 432 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0"
 U15 6
 U16 6
 R37 2
 L10 2
 C95 1
 R36 1
Net 434 "/PSU/Iout_5.0" "Iout_5.0"
 R35 1
 U16 3
Net 435 "" ""
 U15 4
 R37 1
Net 436 "/PSU/VFB3.3" "VFB3.3"
 R25 1
 U11 5
 C79 2
 R26 2
Net 437 "/PSU/Iout_1.2" "Iout_1.2"
 U14 3
 U9 3
 R33 1
Net 439 "/PSU/SW_1.2" "SW_1.2"
 L9 2
 U12 3
Net 440 "/PSU/SW_3.3" "SW_3.3"
 U11 3
 L8 2
Net 467 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3"
 U11 1
 C78 1
 U13 6
 R32 1
 U11 4
Net 468 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2"
 U12 1
 U12 4
 U14 6
 R34 1
 C82 1
Net 483 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3"
 U8 7
 U1 U13
Net 484 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2"
 U1 U14
 U8 3
Net 485 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1"
 U8 2
 U1 AA20
Net 486 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0"
 U8 5
 U1 AB20
Net 487 "/FPGA Spartan6/NF_D7" "NF_D7"
 U1 D11
 U5 44
Net 488 "/FPGA Spartan6/NF_D6" "NF_D6"
 U1 A11
 U5 43
Net 489 "/FPGA Spartan6/NF_D5" "NF_D5"
 U1 C11
 U5 42
Net 490 "/Non volatile memories/NF_D4" "NF_D4"
 U5 41
 U1 A12
Net 491 "/FPGA Spartan6/NF_D3" "NF_D3"
 U1 B12
 U5 32
Net 492 "/FPGA Spartan6/NF_D2" "NF_D2"
 U1 A13
 U5 31
Net 493 "/Non volatile memories/NF_D1" "NF_D1"
 U1 D14
 U5 30
Net 494 "/FPGA Spartan6/NF_D0" "NF_D0"
 U5 29
 U1 C12
Net 495 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1"
 U4 18
 U1 C9
Net 496 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0"
 U4 17
 U1 D10
Net 497 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3"
 U1 C5
 U4 3
Net 498 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
 U1 C6
 U4 4
Net 499 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
 U1 A5
 U4 5
Net 500 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0"
 U4 6
 U1 B6
Net 501 "/FPGA Spartan6/M0_BA1" "M0_BA1"
 U2 27
 RP15 6
Net 502 "/DDR Banks/M0_BA0" "M0_BA0"
 U2 26
 RP15 7
Net 503 "/FPGA Spartan6/M1_BA1" "M1_BA1"
 RP2 6
 U3 27
Net 504 "/DDR Banks/M1_BA0" "M1_BA0"
 U3 26
 RP2 7
Net 505 "/FPGA Spartan6/M1_DQ15" "M1_DQ15"
 RP8 1
 U3 65
Net 506 "/DDR Banks/M1_DQ14" "M1_DQ14"
 RP8 2
 U3 63
Net 507 "/FPGA Spartan6/M1_DQ13" "M1_DQ13"
 RP8 3
 U3 62
Net 508 "/DDR Banks/M1_DQ12" "M1_DQ12"
 U3 60
 RP8 4
Net 509 "/DDR Banks/M1_DQ11" "M1_DQ11"
 RP9 1
 U3 59
Net 510 "/DDR Banks/M1_DQ10" "M1_DQ10"
 RP9 2
 U3 57
Net 511 "/DDR Banks/M1_DQ9" "M1_DQ9"
 RP9 3
 U3 56
Net 512 "/DDR Banks/M1_DQ8" "M1_DQ8"
 U3 54
 RP9 4
Net 513 "/DDR Banks/M1_DQ7" "M1_DQ7"
 RP4 5
 U3 13
Net 514 "/DDR Banks/M1_DQ6" "M1_DQ6"
 U3 11
 RP4 6
Net 515 "/Non volatile memories/SD_DAT3" "SD_DAT3"
 U1 B16
 J1 2
Net 516 "/Non volatile memories/SD_DAT2" "SD_DAT2"
 J1 1
 U1 A16
Net 517 "/FPGA Spartan6/SD_DAT1" "SD_DAT1"
 U1 B18
 J1 8
Net 518 "/FPGA Spartan6/SD_DAT0" "SD_DAT0"
 U1 A18
 J1 7
Net 519 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3"
 U4 20
 U1 A8
Net 520 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2"
 U1 C10
 U4 19
Net 521 "/DDR Banks/M1_A5" "M1_A5"
 U3 36
 RP6 3
Net 522 "/FPGA Spartan6/M1_A4" "M1_A4"
 U3 35
 RP6 4
Net 523 "/FPGA Spartan6/M1_A3" "M1_A3"
 RP1 5
 U3 32
Net 524 "/FPGA Spartan6/M1_A2" "M1_A2"
 RP1 6
 U3 31
Net 525 "/DDR Banks/M1_A1" "M1_A1"
 RP1 7
 U3 30
Net 526 "/FPGA Spartan6/M1_A0" "M1_A0"
 RP1 8
 U3 29
Net 527 "/FPGA Spartan6/M0_A12" "M0_A12"
 RP18 8
 U2 42
Net 528 "/FPGA Spartan6/M0_A11" "M0_A11"
 U2 41
 RP18 7
Net 529 "/DDR Banks/M0_A10" "M0_A10"
 RP15 5
 U2 28
Net 530 "/FPGA Spartan6/M0_A9" "M0_A9"
 RP18 6
 U2 40
Net 531 "/FPGA Spartan6/M0_A8" "M0_A8"
 RP18 5
 U2 39
Net 532 "/DDR Banks/M0_A7" "M0_A7"
 U2 38
 RP17 8
Net 533 "/DDR Banks/M0_A6" "M0_A6"
 RP17 7
 U2 37
Net 534 "/DDR Banks/M0_A5" "M0_A5"
 U2 36
 RP17 6
Net 535 "/FPGA Spartan6/M0_A4" "M0_A4"
 RP17 5
 U2 35
Net 536 "/FPGA Spartan6/M1_DQ5" "M1_DQ5"
 RP4 7
 U3 10
Net 537 "/FPGA Spartan6/M1_DQ4" "M1_DQ4"
 RP4 8
 U3 8
Net 538 "/FPGA Spartan6/M1_DQ3" "M1_DQ3"
 U3 7
 RP5 5
Net 539 "/FPGA Spartan6/M1_DQ2" "M1_DQ2"
 U3 5
 RP5 6
Net 540 "/DDR Banks/M1_DQ1" "M1_DQ1"
 U3 4
 RP5 7
Net 541 "/FPGA Spartan6/M1_DQ0" "M1_DQ0"
 RP5 8
 U3 2
Net 542 "/FPGA Spartan6/M1_A12" "M1_A12"
 U3 42
 RP7 1
Net 543 "/FPGA Spartan6/M1_A11" "M1_A11"
 U3 41
 RP7 2
Net 544 "/FPGA Spartan6/M1_A10" "M1_A10"
 U3 28
 RP2 5
Net 545 "/DDR Banks/M1_A9" "M1_A9"
 U3 40
 RP7 3
Net 546 "/DDR Banks/M1_A8" "M1_A8"
 U3 39
 RP7 4
Net 547 "/FPGA Spartan6/M1_A7" "M1_A7"
 U3 38
 RP6 1
Net 548 "/DDR Banks/M1_A6" "M1_A6"
 RP6 2
 U3 37
Net 549 "/DDR Banks/M0_A3" "M0_A3"
 U2 32
 RP14 5
Net 550 "/FPGA Spartan6/M0_A2" "M0_A2"
 RP14 6
 U2 31
Net 551 "/DDR Banks/M0_A1" "M0_A1"
 U2 30
 RP14 7
Net 552 "/FPGA Spartan6/M0_A0" "M0_A0"
 U2 29
 RP14 8
Net 553 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
 RP10 5
 U2 65
Net 554 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
 RP10 6
 U2 63
Net 555 "/FPGA Spartan6/M0_DQ13" "M0_DQ13"
 RP10 7
 U2 62
Net 556 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
 U2 60
 RP10 8
Net 557 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
 U2 59
 RP11 5
Net 558 "/FPGA Spartan6/M0_DQ10" "M0_DQ10"
 U2 57
 RP11 6
Net 559 "/DDR Banks/M0_DQ9" "M0_DQ9"
 U2 56
 RP11 7
Net 560 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
 RP11 8
 U2 54
Net 561 "/DDR Banks/M0_DQ7" "M0_DQ7"
 RP12 5
 U2 13
Net 562 "/FPGA Spartan6/M0_DQ6" "M0_DQ6"
 RP12 6
 U2 11
Net 563 "/FPGA Spartan6/M0_DQ5" "M0_DQ5"
 RP12 7
 U2 10
Net 564 "/DDR Banks/M0_DQ4" "M0_DQ4"
 RP12 8
 U2 8
Net 565 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
 RP13 5
 U2 7
Net 566 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
 U2 5
 RP13 6
Net 567 "/DDR Banks/M0_DQ1" "M0_DQ1"
 U2 4
 RP13 7
Net 568 "/DDR Banks/M0_DQ0" "M0_DQ0"
 U2 2
 RP13 8
}
#End