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xue/kicad/xue-rnc/xue-rnc.net

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Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 04:08:26 PM COT
initial import
2010-07-24 14:58:53 +03:00
(
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( /4C4320F3/4C5D7F9F 0603 C1 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D80ED 0402 C2 1uF
( 1 /Etherne1 )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 0402 C3 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D80F0 0402 C4 100nF
( 1 /Etherne1 )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 0402 C5 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D8104 0402 C6 100nF
( 1 /Etherne2 )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 0603 C7 1uF
( 1 /Etherne3 )
( 2 GND )
)
( /4C4320F3/4C5D7FA7 0402 C8 100nF
( 1 /Etherne3 )
( 2 GND )
)
( /4C4320F3/4C5D8114 0402 C9 100nF
( 1 /Etherne4 )
( 2 GND )
)
( /4C4320F3/4C5D7E41 0402 C10 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E43 0402 C11 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB 0402 C12 47nF
( 1 N-000410 )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 0603 C13 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 0603 C14 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2039 0603 C15 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF
( 1 N-000425 )
( 2 GND )
)
( /4C421DD3/4C61CC73 0402 C17 100nF
( 1 +2.5V )
( 2 N-000096 )
)
( /4C421DD3/4C61CC96 0402 C18 100nF
( 1 N-000096 )
( 2 GND )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF
( 1 +2.5V )
( 2 N-000097 )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF
( 1 N-000097 )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 10uF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D1D4 1206 C34 10uF
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552BE 0805 C35 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BD 0805 C36 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BC 0402 C37 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552B7 0402 C38 4.7nF
( 1 N-000434 )
( 2 GND )
)
( /4C431A63/4C656A80 1210 C39 100uF
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656BF8 1210 C40 100uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CB7 1210 C41 100uF
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656ABD 0805 C42 4.7uF
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656BF9 0805 C43 4.7uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CB9 0805 C44 4.7uF
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656AC0 0402 C45 470nF
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656C16 0805 C46 4.7uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CBA 0402 C47 470nF
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656AC2 0402 C48 470nF
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656C24 0402 C49 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CBB 0402 C50 470nF
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656C27 0402 C51 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BFA 0402 C52 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C49 0402 C53 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D97 1210 C54 100uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D43 1210 C55 100uF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C431A63/4C656CF9 1210 C56 100uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D98 0805 C57 4.7uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D44 0805 C58 4.7uF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C431A63/4C656CFA 0805 C59 4.7uF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D99 0402 C60 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D45 0402 C61 470nF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C431A63/4C656CFB 0402 C62 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D9A 0402 C63 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D46 0402 C64 470nF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C431A63/4C656CFC 0402 C65 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D9D 0402 C66 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D49 0402 C67 470nF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C431A63/4C656D08 0402 C68 470nF
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D53 0402 C69 470nF
( 1 /FPGA_Sp5 )
( 2 GND )
)
( /4C421DD3/4C65D2A9 0402 C70 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C65D28E 0402 C71 10nF
( 1 +2.5V )
( 2 GND )
)
( /4C4227FE/4C65D661 0402 C72 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D67C 0402 C73 100nF
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D681 0603 C74 1uF
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C6969AB 0402 C75 100nF
( 1 GND )
( 2 +3.3V )
)
( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F
( 1 N-000421 )
( 2 +5V )
)
( /4C5F1EDC/4C6552BA 1210 F2 MICROSMD075F
( 1 N-000438 )
( 2 +5V )
)
( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD
( 1 /Non_vol6 )
( 2 /Non_vol7 )
( 3 /Non_vol8 )
( 4 +3.3V )
( 5 /Non_vol9 )
( 6 GND )
( 7 /Non_vol10 )
( 8 /Non_vol11 )
usb added
2010-08-13 17:27:10 +03:00
( CASE GND )
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( CD ? )
( COM GND )
)
( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025
( 1 N-000402 )
( 2 N-000408 )
( 3 +3.3V )
( 4 GND )
( 5 GND )
( 6 +3.3V )
( 7 N-000405 )
( 8 N-000409 )
( 9 +3.3V )
( 10 N-000404 )
( 11 +3.3V )
( 12 N-000406 )
( 13 N-000410 )
( 14 N-000410 )
)
( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001
( 1 N-000424 )
( 2 N-000422 )
( 3 N-000423 )
( 4 N-000426 )
( S1 N-000425 )
( S2 N-000425 )
( S3 N-000425 )
( S4 N-000425 )
)
( /4C4320F3/4C5D80F3 0402 L1 FB
( 1 /Etherne1 )
( 2 /Etherne2 )
)
( /4C4320F3/4C5D7FB7 0402 L2 FB
( 1 +3.3V )
( 2 /Etherne3 )
)
( /4C4320F3/4C5D810A 0402 L3 FB
( 1 /Etherne2 )
( 2 /Etherne4 )
)
( /4C5F1EDC/4C63F252 0603 L4 FB
( 1 N-000421 )
( 2 N-000424 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB
( 1 N-000426 )
( 2 GND )
)
( /4C5F1EDC/4C6552B0 0603 L6 FB
( 1 N-000438 )
( 2 ? )
)
( /4C5F1EDC/4C6552B1 0603 L7 FB
( 1 ? )
( 2 GND )
)
( /4C4320F3/4C5D7F39 0402 R1 4.7K
( 1 /FPGA_Sp12 )
( 2 +3.3V )
)
( /4C4320F3/4C5D7ECF 0402 R2 6.65K
( 1 N-000411 )
( 2 GND )
)
( /4C4320F3/4C5D7AFE 0402 R3 49.9
( 1 +3.3V )
( 2 N-000402 )
)
( /4C4320F3/4C5D7AFC 0402 R4 49.9
( 1 +3.3V )
( 2 N-000408 )
)
( /4C4320F3/4C5D7AF7 0402 R5 49.9
( 1 +3.3V )
( 2 N-000405 )
)
( /4C4320F3/4C5D7AF9 0402 R6 49.9
( 1 +3.3V )
( 2 N-000409 )
)
( /4C4320F3/4C5D719D 0402 R7 220
( 1 N-000404 )
( 2 /Etherne13 )
)
( /4C4320F3/4C5D71DB 0402 R8 220
( 1 N-000406 )
( 2 /Etherne14 )
)
( /4C4320F3/4C5D7DC4 0402 R9 1M
( 1 N-000410 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 0402 R10 1M
( 1 N-000425 )
( 2 GND )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1%
( 1 +2.5V )
( 2 N-000096 )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1%
( 1 N-000096 )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1%
( 1 +2.5V )
( 2 N-000097 )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1%
( 1 N-000097 )
( 2 GND )
)
( /4C5F1EDC/4C6552B6 0402 R15 1M
( 1 N-000434 )
( 2 GND )
)
( /4C421DD3/4C699384 R_PACK4-0402 RP1 R_PACK4
( 1 N-000093 )
( 2 N-000099 )
( 3 N-000094 )
( 4 N-000098 )
( 5 /DDR_Banks/M0_A0 )
( 6 /DDR_Banks/M0_A1 )
( 7 /DDR_Banks/M0_A2 )
( 8 /DDR_Banks/M0_A3 )
)
( /4C421DD3/4C699385 R_PACK4-0402 RP2 R_PACK4
( 1 N-000091 )
( 2 N-000101 )
( 3 N-000092 )
( 4 N-000100 )
( 5 /DDR_Banks/M0_A4 )
( 6 /DDR_Banks/M0_A5 )
( 7 /DDR_Banks/M0_A6 )
( 8 /DDR_Banks/M0_A7 )
)
( /4C421DD3/4C69933E R_PACK4-0402 RP3 R_PACK4
( 1 N-000089 )
( 2 N-000103 )
( 3 N-000090 )
( 4 N-000102 )
( 5 /DDR_Banks/M0_A8 )
( 6 /DDR_Banks/M0_A9 )
( 7 /DDR_Ban15 )
( 8 /DDR_Ban16 )
)
( /4C421DD3/4C69937F R_PACK4-0402 RP4 R_PACK4
( 1 N-000087 )
( 2 N-000105 )
( 3 N-000088 )
( 4 N-000104 )
( 5 /DDR_Ban17 )
( 6 /DDR_Ban18 )
( 7 /DDR_Ban19 )
( 8 /DDR_Ban20 )
)
( /4C421DD3/4C6993A2 R_PACK4-0402 RP5 R_PACK4
( 1 N-000085 )
( 2 N-000107 )
( 3 N-000086 )
( 4 N-000106 )
( 5 /DDR_Ban21 )
( 6 /DDR_Ban22 )
( 7 /DDR_Ban23 )
( 8 GND )
)
( /4C421DD3/4C6995A8 R_PACK4-0402 RP6 R_PACK4
( 1 N-000083 )
( 2 N-000109 )
( 3 N-000084 )
( 4 N-000108 )
( 5 /DDR_Ban24 )
( 6 /DDR_Ban25 )
( 7 /DDR_Ban26 )
( 8 /DDR_Ban27 )
)
( /4C421DD3/4C6995A6 R_PACK4-0402 RP7 R_PACK4
( 1 /DDR_Banks/M0DQ7 )
( 2 /DDR_Banks/M0DQ6 )
( 3 /DDR_Banks/M0DQ5 )
( 4 N-000110 )
( 5 /DDR_Ban28 )
( 6 /DDR_Ban29 )
( 7 /DDR_Ban30 )
( 8 /DDR_Ban31 )
)
( /4C421DD3/4C699D96 R_PACK2-0402 RP8 R_PACK2
( 1 /DDR_Ban32 )
( 2 /DDR_Ban33 )
( 3 N-000132 )
( 4 N-000056 )
)
( /4C421DD3/4C6993A3 R_PACK4-0402 RP9 R_PACK4
( 1 /DDR_Ban34 )
( 2 /DDR_Ban35 )
( 3 /DDR_Ban36 )
( 4 /DDR_Ban37 )
( 5 N-000082 )
( 6 N-000111 )
( 7 N-000081 )
( 8 N-000112 )
)
( /4C421DD3/4C6995A7 R_PACK4-0402 RP10 R_PACK4
( 1 /DDR_Ban38 )
( 2 /DDR_Ban39 )
( 3 /DDR_Ban40 )
( 4 /DDR_Ban41 )
( 5 N-000080 )
( 6 N-000113 )
( 7 N-000079 )
( 8 N-000114 )
)
( /4C421DD3/4C6995BC R_PACK4-0402 RP11 R_PACK4
( 1 /DDR_Ban42 )
( 2 /DDR_Ban43 )
( 3 /DDR_Ban44 )
( 4 /DDR_Ban45 )
( 5 N-000129 )
( 6 N-000061 )
( 7 N-000060 )
( 8 N-000130 )
)
( /4C421DD3/4C6993A0 R_PACK4-0402 RP12 R_PACK4
( 1 N-000118 )
( 2 N-000076 )
( 3 N-000117 )
( 4 N-000077 )
( 5 /DDR_Banks/M1_A0 )
( 6 /DDR_Banks/M1_A1 )
( 7 /DDR_Banks/M1_A2 )
( 8 /DDR_Banks/M1_A3 )
)
( /4C421DD3/4C6993A1 R_PACK4-0402 RP13 R_PACK4
( 1 N-000120 )
( 2 N-000074 )
( 3 N-000119 )
( 4 N-000075 )
( 5 /DDR_Banks/M1_A4 )
( 6 /DDR_Banks/M1_A5 )
( 7 /DDR_Banks/M1_A6 )
( 8 /DDR_Banks/M1_A7 )
)
( /4C421DD3/4C6995B3 R_PACK4-0402 RP14 R_PACK4
( 1 N-000122 )
( 2 N-000072 )
( 3 N-000121 )
( 4 N-000073 )
( 5 /DDR_Banks/M1_A8 )
( 6 /DDR_Banks/M1_A9 )
( 7 /DDR_Ban46 )
( 8 /DDR_Ban47 )
)
( /4C421DD3/4C6995B1 R_PACK4-0402 RP15 R_PACK4
( 1 N-000124 )
( 2 N-000070 )
( 3 N-000123 )
( 4 N-000071 )
( 5 /DDR_Ban48 )
( 6 /DDR_Ban49 )
( 7 /DDR_Ban50 )
( 8 /DDR_Ban51 )
)
( /4C421DD3/4C6995B2 R_PACK4-0402 RP16 R_PACK4
( 1 N-000126 )
( 2 N-000068 )
( 3 N-000125 )
( 4 N-000069 )
( 5 /DDR_Ban52 )
( 6 /DDR_Ban53 )
( 7 /DDR_Ban54 )
( 8 GND )
)
( /4C421DD3/4C6995BD R_PACK4-0402 RP17 R_PACK4
( 1 N-000128 )
( 2 N-000066 )
( 3 N-000127 )
( 4 N-000067 )
( 5 /DDR_Ban55 )
( 6 /DDR_Ban56 )
( 7 /DDR_Ban57 )
( 8 /DDR_Ban58 )
)
( /4C421DD3/4C6995B0 R_PACK4-0402 RP18 R_PACK4
( 1 /DDR_Banks/M1DQ7 )
( 2 /DDR_Banks/M1DQ6 )
( 3 /DDR_Banks/M1DQ5 )
( 4 N-000065 )
( 5 /DDR_Ban59 )
( 6 /DDR_Ban60 )
( 7 /DDR_Ban61 )
( 8 /DDR_Ban62 )
)
( /4C421DD3/4C699D71 R_PACK2-0402 RP19 R_PACK2
( 1 /DDR_Ban63 )
( 2 /DDR_Ban64 )
( 3 N-000133 )
( 4 N-000055 )
)
( /4C421DD3/4C6995AE R_PACK4-0402 RP20 R_PACK4
( 1 /DDR_Ban65 )
( 2 /DDR_Ban66 )
( 3 /DDR_Ban67 )
( 4 /DDR_Ban68 )
( 5 N-000134 )
( 6 N-000054 )
( 7 N-000135 )
( 8 N-000053 )
)
( /4C421DD3/4C6995AF R_PACK4-0402 RP21 R_PACK4
( 1 /DDR_Ban69 )
( 2 /DDR_Ban70 )
( 3 /DDR_Ban71 )
( 4 /DDR_Ban72 )
( 5 N-000136 )
( 6 N-000052 )
( 7 N-000137 )
( 8 N-000051 )
)
( /4C421DD3/4C6995BA R_PACK4-0402 RP22 R_PACK4
( 1 /DDR_Ban73 )
( 2 /DDR_Ban74 )
( 3 /DDR_Ban75 )
( 4 /DDR_Ban76 )
( 5 N-000057 )
( 6 N-000059 )
( 7 N-000131 )
( 8 N-000058 )
)
( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484
( A1 GND )
( A2 ? )
( A3 ? )
( A4 /FPGA_Sp77 )
( A5 /FPGA_Sp78 )
( A6 /FPGA_Sp79 )
( A7 /FPGA_Sp80 )
( A8 /FPGA_Sp81 )
( A9 /FPGA_Sp82 )
( A10 /FPGA_Sp83 )
( A11 /Non_vol84 )
( A12 /Non_vol85 )
( A13 /Non_vol86 )
( A14 ? )
( A15 /Non_vol87 )
( A16 /Non_vol88 )
( A17 /Non_vol6 )
( A18 /Non_vol10 )
( A19 ? )
( A20 ? )
( A21 ? )
( A22 GND )
( AA1 ? )
( AA2 ? )
( AA3 /FPGA_Sp5 )
( AA4 ? )
( AA5 GND )
( AA6 ? )
( AA7 /FPGA_Sp5 )
( AA8 ? )
( AA9 GND )
( AA10 ? )
( AA11 /FPGA_Sp5 )
( AA12 ? )
( AA13 GND )
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
( AA14 ? )
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( AA15 /FPGA_Sp5 )
( AA16 ? )
( AA17 GND )
( AA18 ? )
( AA19 /FPGA_Sp5 )
( AA20 /Non_vol89 )
( AA21 /Non_vol90 )
usb added
2010-08-13 17:27:10 +03:00
( AA22 ? )
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( AB1 GND )
( AB2 ? )
( AB3 ? )
( AB4 ? )
( AB5 ? )
( AB6 ? )
( AB7 ? )
( AB8 ? )
( AB9 ? )
( AB10 ? )
( AB11 ? )
usb added
2010-08-13 17:27:10 +03:00
( AB12 ? )
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( AB13 ? )
( AB14 ? )
( AB15 ? )
( AB16 ? )
( AB17 ? )
( AB18 ? )
( AB19 ? )
( AB20 /Non_vol91 )
usb added
2010-08-13 17:27:10 +03:00
( AB21 ? )
fixed placement
2010-08-13 00:12:57 +03:00
( AB22 GND )
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
( B1 ? )
( B2 ? )
( B3 ? )
( B4 +3.3V )
( B5 GND )
( B6 /FPGA_Sp92 )
( B7 +3.3V )
( B8 /FPGA_Sp93 )
( B9 GND )
( B10 /FPGA_Sp94 )
( B11 +3.3V )
( B12 /Non_vol95 )
( B13 GND )
( B14 ? )
( B15 +3.3V )
( B16 /Non_vol96 )
( B17 GND )
( B18 /Non_vol11 )
( B19 +3.3V )
( B20 ? )
( B21 ? )
( B22 ? )
( C1 /DDR_Ban16 )
( C2 +2.5V )
( C3 ? )
( C4 ? )
( C5 /FPGA_Sp12 )
( C6 /FPGA_Sp97 )
( C7 /FPGA_Sp98 )
( C8 /FPGA_Sp99 )
( C9 /FPGA_Sp100 )
( C10 /FPGA_Sp101 )
( C11 ? )
( C12 /Non_vol102 )
( C13 /Non_vol103 )
( C14 ? )
( C15 /Non_vol104 )
( C16 /Non_vol105 )
( C17 /Non_vol7 )
( C18 ? )
( C19 ? )
( C20 /DDR_Banks/M1_A8 )
( C21 +2.5V )
( C22 /DDR_Banks/M1_A9 )
( D1 /DDR_Ban17 )
( D2 /DDR_Ban21 )
( D3 ? )
( D4 GND )
( D5 ? )
( D6 /FPGA_Sp106 )
( D7 /FPGA_Sp107 )
( D8 /FPGA_Sp108 )
( D9 /FPGA_Sp109 )
( D10 /FPGA_Sp110 )
( D11 /Non_vol111 )
( D12 ? )
( D13 ? )
( D14 /Non_vol112 )
( D15 /Non_vol113 )
( D16 +2.5V )
( D17 /Non_vol8 )
( D18 GND )
( D19 ? )
( D20 ? )
( D21 /DDR_Ban52 )
( D22 /DDR_Ban48 )
( E1 /DDR_Banks/M0_A9 )
( E2 GND )
( E3 /DDR_Banks/M0_A8 )
( E4 ? )
( E5 ? )
( E6 ? )
( E7 GND )
( E8 ? )
( E9 +3.3V )
( E10 ? )
( E11 GND )
( E12 ? )
( E13 +3.3V )
( E14 ? )
( E15 GND )
( E16 /Non_vol9 )
( E17 +3.3V )
( E18 ? )
( E19 +2.5V )
( E20 /DDR_Banks/M1_A7 )
( E21 GND )
( E22 /DDR_Banks/M1_A2 )
( F1 ? )
( F2 /DDR_Ban45 )
( F3 /DDR_Banks/M0_A4 )
( F4 +2.5V )
( F5 ? )
( F6 +2.5V )
( F7 ? )
( F8 ? )
( F9 ? )
( F10 ? )
( F11 +2.5V )
( F12 ? )
( F13 ? )
( F14 ? )
( F15 ? )
( F16 ? )
( F17 ? )
( F18 ? )
( F19 /DDR_Ban47 )
( F20 /DDR_Banks/M1_A4 )
( F21 /DDR_Banks/M1_A0 )
( F22 /DDR_Banks/M1_A1 )
( G1 /DDR_Ban19 )
( G2 +2.5V )
( G3 /DDR_Ban18 )
( G4 /DDR_Ban15 )
( G5 GND )
( G6 ? )
( G7 ? )
( G8 ? )
( G9 ? )
( G10 +3.3V )
( G11 ? )
( G12 +2.5V )
( G13 ? )
( G14 +3.3V )
( G15 ? )
( G16 ? )
( G17 ? )
( G18 GND )
( G19 /DDR_Ban46 )
( G20 /DDR_Banks/M1_A3 )
( G21 +2.5V )
( G22 ? )
( H1 /DDR_Banks/M0_A1 )
( H2 /DDR_Banks/M0_A0 )
( H3 /DDR_Ban23 )
( H4 /DDR_Ban22 )
( H5 /DDR_Banks/M0_A2 )
( H6 /DDR_Banks/M0_A7 )
( H7 GND )
( H8 ? )
( H9 +2.5V )
( H10 ? )
( H11 ? )
( H12 ? )
( H13 ? )
( H14 ? )
( H15 +2.5V )
( H16 ? )
( H17 ? )
( H18 ? )
( H19 /DDR_Ban76 )
( H20 /DDR_Ban53 )
( H21 /DDR_Ban73 )
( H22 /DDR_Ban51 )
( J1 /DDR_Ban29 )
( J2 GND )
( J3 /DDR_Ban28 )
( J4 /DDR_Banks/M0_A6 )
( J5 +2.5V )
( J6 ? )
( J7 ? )
( J8 +1.2V )
( J9 GND )
( J10 +1.2V )
( J11 GND )
( J12 +1.2V )
( J13 GND )
( J14 +1.2V )
( J15 GND )
( J16 ? )
( J17 /DDR_Ban49 )
( J18 +2.5V )
( J19 /DDR_Ban54 )
( J20 /DDR_Ban59 )
( J21 GND )
( J22 /DDR_Ban60 )
( K1 /DDR_Ban31 )
( K2 /DDR_Ban30 )
( K3 /DDR_Banks/M0_A5 )
( K4 /DDR_Ban20 )
( K5 /DDR_Ban42 )
( K6 /DDR_Banks/M0_A3 )
( K7 ? )
( K8 ? )
( K9 +1.2V )
( K10 GND )
( K11 +1.2V )
( K12 GND )
( K13 +1.2V )
( K14 GND )
( K15 +2.5V )
( K16 ? )
( K17 /DDR_Ban50 )
( K18 ? )
( K19 /DDR_Banks/M1_A6 )
( K20 /DDR_Banks/M1_A5 )
( K21 /DDR_Ban61 )
( K22 /DDR_Ban62 )
( L1 ? )
( L2 +2.5V )
( L3 /DDR_Ban33 )
( L4 /DDR_Ban32 )
( L5 GND )
( L6 ? )
( L7 +2.5V )
( L8 +2.5V )
( L9 GND )
( L10 +1.2V )
( L11 GND )
( L12 +1.2V )
( L13 GND )
( L14 +1.2V )
( L15 ? )
( L16 +2.5V )
( L17 ? )
( L18 GND )
( L19 /DDR_Ban63 )
( L20 /DDR_Ban64 )
( L21 +2.5V )
( L22 ? )
( M1 /DDR_Ban27 )
( M2 /DDR_Ban26 )
( M3 /DDR_Ban43 )
( M4 ? )
( M5 ? )
( M6 ? )
( M7 ? )
( M8 ? )
( M9 +1.2V )
( M10 GND )
( M11 +1.2V )
( M12 GND )
( M13 +1.2V )
( M14 GND )
( M15 +2.5V )
( M16 ? )
( M17 ? )
( M18 /FPGA_Sp114 )
( M19 ? )
( M20 /DDR_Ban74 )
( M21 /DDR_Ban57 )
( M22 /DDR_Ban58 )
( N1 /DDR_Ban25 )
( N2 GND )
( N3 /DDR_Ban24 )
( N4 ? )
( N5 +2.5V )
( N6 ? )
( N7 ? )
( N8 +2.5V )
( N9 GND )
( N10 +1.2V )
( N11 GND )
( N12 +1.2V )
( N13 GND )
( N14 +1.2V )
( N15 ? )
( N16 /FPGA_Sp115 )
( N17 GND )
( N18 +2.5V )
( N19 ? )
( N20 /DDR_Ban55 )
( N21 GND )
( N22 /DDR_Ban56 )
( P1 /DDR_Ban39 )
( P2 /DDR_Ban38 )
( P3 ? )
( P4 ? )
( P5 ? )
( P6 ? )
( P7 ? )
( P8 ? )
( P9 +1.2V )
( P10 GND )
( P11 +1.2V )
( P12 GND )
( P13 +1.2V )
( P14 GND )
( P15 ? )
( P16 ? )
( P17 /FPGA_Sp116 )
( P18 /FPGA_Sp117 )
( P19 ? )
( P20 ? )
( P21 /DDR_Ban69 )
( P22 /DDR_Ban70 )
( R1 /DDR_Ban41 )
( R2 +2.5V )
( R3 /DDR_Ban40 )
( R4 ? )
( R5 GND )
( R6 +2.5V )
( R7 ? )
( R8 ? )
( R9 ? )
( R10 +2.5V )
( R11 ? )
( R12 +2.5V )
( R13 ? )
( R14 +1.2V )
( R15 ? )
( R16 ? )
( R17 ? )
( R18 GND )
( R19 /FPGA_Sp118 )
( R20 /DDR_Ban71 )
( R21 +2.5V )
( R22 /DDR_Ban72 )
( T1 ? )
( T2 /DDR_Ban44 )
( T3 ? )
( T4 ? )
( T5 /Non_vol119 )
( T6 ? )
( T7 ? )
( T8 ? )
( T9 /FPGA_Sp5 )
( T10 ? )
( T11 ? )
( T12 ? )
( T13 /FPGA_Sp5 )
( T14 ? )
( T15 ? )
( T16 ? )
( T17 ? )
( T18 ? )
( T19 ? )
( T20 ? )
( T21 /DDR_Ban75 )
( T22 ? )
( U1 /DDR_Ban35 )
( U2 GND )
( U3 /DDR_Ban34 )
( U4 ? )
( U5 +2.5V )
( U6 ? )
( U7 GND )
( U8 ? )
( U9 ? )
( U10 ? )
( U11 +2.5V )
( U12 ? )
( U13 /Non_vol120 )
( U14 /Non_vol121 )
( U15 ? )
( U16 ? )
( U17 ? )
( U18 +2.5V )
( U19 ? )
( U20 /DDR_Ban65 )
( U21 GND )
( U22 /DDR_Ban66 )
( V1 /DDR_Ban37 )
( V2 /DDR_Ban36 )
( V3 ? )
( V4 GND )
( V5 ? )
( V6 +2.5V )
( V7 ? )
( V8 /FPGA_Sp5 )
( V9 ? )
( V10 GND )
( V11 ? )
( V12 /FPGA_Sp5 )
( V13 ? )
( V14 GND )
( V15 ? )
( V16 /FPGA_Sp5 )
( V17 ? )
( V18 ? )
( V19 ? )
( V20 ? )
( V21 /DDR_Ban67 )
( V22 /DDR_Ban68 )
( W1 ? )
( W2 +2.5V )
( W3 ? )
( W4 ? )
( W5 /FPGA_Sp5 )
( W6 ? )
( W7 GND )
( W8 ? )
( W9 ? )
( W10 ? )
( W11 ? )
( W12 ? )
( W13 ? )
( W14 ? )
( W15 ? )
( W16 GND )
( W17 ? )
( W18 ? )
( W19 GND )
( W20 ? )
( W21 +2.5V )
( W22 ? )
( Y1 ? )
( Y2 ? )
( Y3 ? )
( Y4 ? )
( Y5 ? )
( Y6 ? )
( Y7 ? )
( Y8 ? )
( Y9 ? )
( Y10 ? )
( Y11 ? )
( Y12 ? )
( Y13 ? )
( Y14 ? )
( Y15 ? )
( Y16 ? )
( Y17 ? )
( Y18 ? )
( Y19 ? )
( Y20 ? )
( Y21 ? )
( Y22 ? )
)
( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG
( 1 +2.5V )
( 2 N-000108 )
( 3 +2.5V )
( 4 N-000084 )
( 5 N-000109 )
( 6 GND )
( 7 N-000083 )
( 8 N-000110 )
( 9 +2.5V )
( 10 /DDR_Banks/M0DQ5 )
( 11 /DDR_Banks/M0DQ6 )
( 12 GND )
( 13 /DDR_Banks/M0DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 N-000132 )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 N-000056 )
( 21 N-000129 )
( 22 N-000087 )
( 23 N-000130 )
( 24 N-000085 )
( 25 ? )
( 26 N-000088 )
( 27 N-000105 )
( 28 N-000103 )
( 29 N-000098 )
( 30 N-000094 )
( 31 N-000099 )
( 32 N-000093 )
( 33 +2.5V )
( 34 GND )
( 35 N-000100 )
( 36 N-000092 )
( 37 N-000101 )
( 38 N-000091 )
( 39 N-000102 )
( 40 N-000090 )
( 41 N-000089 )
( 42 N-000104 )
( 43 ? )
( 44 N-000107 )
( 45 N-000106 )
( 46 N-000086 )
( 47 N-000060 )
( 48 GND )
( 49 N-000096 )
( 50 ? )
( 51 N-000061 )
( 52 GND )
( 53 ? )
( 54 N-000114 )
( 55 +2.5V )
( 56 N-000079 )
( 57 N-000113 )
( 58 GND )
( 59 N-000080 )
( 60 N-000112 )
( 61 +2.5V )
( 62 N-000081 )
( 63 N-000111 )
( 64 GND )
( 65 N-000082 )
( 66 GND )
)
( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG
( 1 +2.5V )
( 2 N-000067 )
( 3 +2.5V )
( 4 N-000127 )
( 5 N-000066 )
( 6 GND )
( 7 N-000128 )
( 8 N-000065 )
( 9 +2.5V )
( 10 /DDR_Banks/M1DQ5 )
( 11 /DDR_Banks/M1DQ6 )
( 12 GND )
( 13 /DDR_Banks/M1DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 N-000133 )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 N-000055 )
( 21 N-000057 )
( 22 N-000124 )
( 23 N-000058 )
( 24 N-000126 )
( 25 ? )
( 26 N-000123 )
( 27 N-000070 )
( 28 N-000072 )
( 29 N-000077 )
( 30 N-000117 )
( 31 N-000076 )
( 32 N-000118 )
( 33 +2.5V )
( 34 GND )
( 35 N-000075 )
( 36 N-000119 )
( 37 N-000074 )
( 38 N-000120 )
( 39 N-000073 )
( 40 N-000121 )
( 41 N-000122 )
( 42 N-000071 )
( 43 ? )
( 44 N-000068 )
( 45 N-000069 )
( 46 N-000125 )
( 47 N-000131 )
( 48 GND )
( 49 N-000097 )
( 50 ? )
( 51 N-000059 )
( 52 GND )
( 53 ? )
( 54 N-000051 )
( 55 +2.5V )
( 56 N-000137 )
( 57 N-000052 )
( 58 GND )
( 59 N-000136 )
( 60 N-000053 )
( 61 +2.5V )
( 62 N-000135 )
( 63 N-000054 )
( 64 GND )
( 65 N-000134 )
( 66 GND )
)
( /4C4320F3/4C432132 LQFP48 U4 K8001
( 1 /FPGA_Sp12 )
( 2 /FPGA_Sp110 )
( 3 /FPGA_Sp106 )
( 4 /FPGA_Sp97 )
( 5 /FPGA_Sp92 )
( 6 /FPGA_Sp79 )
( 7 +3.3V )
( 8 GND )
( 9 /FPGA_Sp98 )
( 10 /FPGA_Sp108 )
( 11 /FPGA_Sp80 )
( 12 GND )
( 13 /Etherne1 )
( 14 /FPGA_Sp93 )
( 15 /FPGA_Sp107 )
( 16 /FPGA_Sp81 )
( 17 /FPGA_Sp109 )
( 18 /FPGA_Sp99 )
( 19 /FPGA_Sp100 )
( 20 /FPGA_Sp82 )
( 21 /FPGA_Sp94 )
( 22 /FPGA_Sp101 )
( 23 GND )
( 24 +3.3V )
( 25 /FPGA_Sp83 )
( 26 /Etherne13 )
( 27 /Etherne14 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Etherne2 )
( 32 N-000409 )
( 33 N-000405 )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000411 )
( 38 /Etherne3 )
( 39 GND )
( 40 N-000408 )
( 41 N-000402 )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /FPGA_Sp77 )
( 47 /Etherne4 )
( 48 /FPGA_Sp78 )
)
( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /Non_vol88 )
( 7 /Non_vol88 )
( 8 /Non_vol96 )
( 9 /Non_vol105 )
( 10 ? )
( 11 ? )
( 12 +3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 /Non_vol113 )
( 17 /Non_vol87 )
( 18 /Non_vol104 )
( 19 +3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 /Non_vol112 )
( 30 /Non_vol86 )
( 31 /Non_vol103 )
( 32 /Non_vol85 )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 +3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 /Non_vol95 )
( 42 /Non_vol102 )
( 43 /Non_vol111 )
( 44 /Non_vol84 )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS
( 1 +2.5V )
( 2 /FPGA_Sp118 )
( 3 /FPGA_Sp115 )
( 4 /FPGA_Sp116 )
( 5 /FPGA_Sp114 )
( 7 GND )
( 8 GND )
( 9 /FPGA_Sp117 )
( 10 N-000422 )
( 11 N-000423 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C5F1EDC/4C6552BF TSSOP-14 U7 MIC2550AYTS
( 1 +2.5V )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 7 GND )
( 8 GND )
( 9 ? )
( 10 N-000433 )
( 11 N-000429 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C4227FE/4C65A75D SO8E U8 X25X64MB
( 1 /Non_vol119 )
( 2 /Non_vol89 )
( 3 /Non_vol121 )
( 4 GND )
( 5 /Non_vol91 )
( 6 /Non_vol90 )
( 7 /Non_vol120 )
( 8 /FPGA_Sp5 )
)
( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03
( 1 N-000423 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03
( 1 N-000422 )
( 2 GND )
)
( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03
( 1 N-000429 )
( 2 GND )
)
( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03
( 1 N-000433 )
( 2 GND )
initial import
2010-07-24 14:58:53 +03:00
)
)
*
Phy
2010-08-08 20:15:44 +03:00
{ Allowed footprints by component:
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C1
decoupling nand flash added
2010-08-14 02:38:38 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C2
decoupling nand flash added
2010-08-14 02:38:38 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C3
decoupling nand flash added
2010-08-14 02:38:38 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C4
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C5
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C6
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C7
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C8
SM*
C?
C1-1
VCC fixed
2010-08-14 01:34:12 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C9
SM*
C?
C1-1
VCC fixed
2010-08-14 01:34:12 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C10
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C11
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C12
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
SM*
C?
C1-1
$endlist
VCC fixed
2010-08-14 01:34:12 +03:00
$component C13
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C14
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C15
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C16
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C17
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C18
Phy
2010-08-08 20:15:44 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C19
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
early placement
2010-08-10 06:25:05 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C20
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C21
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C22
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C23
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C24
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C25
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C26
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C27
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C28
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
ddr footprint changed
2010-08-10 05:29:52 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C29
usb added
2010-08-13 17:27:10 +03:00
SM*
C?
C1-1
Phy
2010-08-08 20:15:44 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C30
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C31
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C32
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C33
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C34
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C35
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C36
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C37
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C38
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C39
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
VCC fixed
2010-08-14 01:34:12 +03:00
$component C40
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C41
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C42
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C43
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C44
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C45
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C46
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C47
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C48
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C49
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C50
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C51
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C52
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C53
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C54
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C55
eth-phy placement
2010-08-14 15:42:37 +03:00
SM*
C?
C1-1
VCC fixed
2010-08-14 01:34:12 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C56
eth-phy placement
2010-08-14 15:42:37 +03:00
SM*
C?
C1-1
VCC fixed
2010-08-14 01:34:12 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C57
SM*
C?
C1-1
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C58
SM*
C?
C1-1
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C59
SM*
C?
C1-1
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C60
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C61
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C62
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C63
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C64
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C65
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C66
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C67
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C68
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C69
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C70
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C71
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C72
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C73
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C74
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component C75
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
SM*
C?
C1-1
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R1
eth-phy placement
2010-08-14 15:42:37 +03:00
R?
SM0603
SM0805
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R2
eth-phy placement
2010-08-14 15:42:37 +03:00
R?
SM0603
SM0805
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R3
R?
SM0603
SM0805
$endlist
$component R4
R?
SM0603
SM0805
$endlist
$component R5
R?
SM0603
SM0805
$endlist
$component R6
R?
SM0603
SM0805
$endlist
$component R7
R?
SM0603
SM0805
$endlist
$component R8
R?
SM0603
SM0805
$endlist
$component R9
R?
SM0603
SM0805
$endlist
$component R10
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
R?
SM0603
SM0805
$endlist
$component R11
R?
SM0603
SM0805
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R12
R?
SM0603
SM0805
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R13
R?
SM0603
SM0805
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R14
R?
SM0603
SM0805
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$endlist
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
$component R15
R?
SM0603
SM0805
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$endlist
Phy
2010-08-08 20:15:44 +03:00
$endfootprintlist
initial import
2010-07-24 14:58:53 +03:00
}
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