2010-08-09 23:37:18 +03:00
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EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT
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LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache
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2010-07-24 14:58:53 +03:00
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EELAYER 24 0
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EELAYER END
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2010-08-09 01:54:09 +03:00
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$Descr A3 16535 11700
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Sheet 1 6
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2010-07-24 14:58:53 +03:00
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Title ""
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2010-08-09 06:53:21 +03:00
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Date "9 aug 2010"
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2010-07-24 14:58:53 +03:00
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2010-08-09 23:37:18 +03:00
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Wire Wire Line
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10650 5400 9300 5400
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Wire Wire Line
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10650 5200 9300 5200
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Wire Wire Line
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10650 5000 9300 5000
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Wire Wire Line
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9300 7800 10600 7800
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Wire Wire Line
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9300 7600 10600 7600
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Wire Wire Line
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9300 7400 10600 7400
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Wire Wire Line
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9300 7200 10600 7200
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Wire Wire Line
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10600 6900 9300 6900
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Wire Wire Line
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9300 6700 10600 6700
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Wire Wire Line
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9300 6500 10600 6500
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2010-08-05 04:50:31 +03:00
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Wire Bus Line
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2010-08-09 06:53:21 +03:00
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4700 3150 5950 3150
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-09 06:53:21 +03:00
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4700 2800 5950 2800
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2010-07-28 14:48:02 +03:00
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Wire Wire Line
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2010-08-09 06:53:21 +03:00
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4700 3750 5950 3750
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Wire Wire Line
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4700 3900 5950 3900
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Wire Wire Line
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4700 4250 5950 4250
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Wire Wire Line
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4700 5950 5950 5950
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Wire Wire Line
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4700 6550 5950 6550
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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2010-08-09 06:53:21 +03:00
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4700 5250 5950 5250
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Wire Wire Line
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4700 6300 5950 6300
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Wire Wire Line
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4700 5700 5950 5700
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Wire Wire Line
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4700 5400 5950 5400
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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2010-08-09 06:53:21 +03:00
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4700 3050 5950 3050
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-09 06:53:21 +03:00
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5950 4100 4700 4100
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2010-08-09 01:54:09 +03:00
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4700 6150 5950 6150
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2010-08-04 05:23:17 +03:00
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Wire Bus Line
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2010-08-09 06:53:21 +03:00
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5950 5100 5950 5050
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Wire Bus Line
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5950 5050 4700 5050
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Wire Wire Line
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4700 6050 5950 6050
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Wire Wire Line
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4700 4000 5950 4000
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Wire Bus Line
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4700 5150 5950 5150
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Wire Wire Line
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4700 5800 5950 5800
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Wire Wire Line
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4700 5500 5950 5500
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Wire Wire Line
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4700 6400 5950 6400
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Wire Wire Line
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4700 4900 5950 4900
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Wire Wire Line
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4700 4350 5950 4350
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Wire Wire Line
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4700 4500 5950 4500
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Wire Wire Line
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4700 3650 5950 3650
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Wire Wire Line
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4700 3450 5950 3450
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Wire Wire Line
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4700 3350 5950 3350
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Wire Bus Line
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4700 2950 5950 2950
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2010-08-09 23:37:18 +03:00
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Wire Wire Line
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9300 6350 10600 6350
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Wire Wire Line
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9300 6600 10600 6600
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Wire Wire Line
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9300 6800 10600 6800
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Wire Wire Line
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9300 7000 10600 7000
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Wire Wire Line
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9300 7300 10600 7300
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Wire Wire Line
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9300 7500 10600 7500
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Wire Wire Line
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9300 7700 10600 7700
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Wire Wire Line
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9300 7900 10600 7900
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Wire Wire Line
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10650 5100 9300 5100
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Wire Wire Line
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10650 5300 9300 5300
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Text HLabel 9300 5400 0 60 BiDi ~ 0
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USBA_VM
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Text HLabel 9300 5300 0 60 BiDi ~ 0
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USBA_VP
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Text HLabel 9300 5200 0 60 BiDi ~ 0
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USBA_RCV
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Text HLabel 9300 5100 0 60 BiDi ~ 0
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USBA_OE_N
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Text HLabel 9300 5000 0 60 BiDi ~ 0
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USBA_SPD
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Text HLabel 9300 6900 0 60 BiDi ~ 0
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ETH_MDIO
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Text HLabel 9300 7500 0 60 BiDi ~ 0
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ETH_TXC
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Text HLabel 9300 7900 0 60 Input ~ 0
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ETH_CLK
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Text HLabel 9300 7800 0 60 Input ~ 0
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ETH_TXER
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Text HLabel 9300 7700 0 60 Input ~ 0
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ETH_TXEN
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Text HLabel 9300 7600 0 60 Input ~ 0
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ETH_TXD[0..3]
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Text HLabel 9300 7000 0 60 Input ~ 0
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ETH_MDC
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Text HLabel 9300 6600 0 60 Input ~ 0
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ETH_RESET_N
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Text HLabel 9300 7400 0 60 Output ~ 0
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ETH_RXER
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Text HLabel 9300 7300 0 60 Output ~ 0
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ETH_RXDV
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Text HLabel 9300 7200 0 60 Output ~ 0
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ETH_RXD[0..3]
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Text HLabel 9300 6800 0 60 Output ~ 0
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ETH_COL
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Text HLabel 9300 6700 0 60 Output ~ 0
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ETH_CRS
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2010-07-24 14:58:53 +03:00
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$Sheet
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2010-08-09 01:54:09 +03:00
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S 5950 2700 3350 5800
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2010-07-24 14:58:53 +03:00
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U 4C431A63
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F0 "FPGA Spartan6" 60
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F1 "FPGA.sch" 60
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2010-08-09 01:54:09 +03:00
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F2 "M1_CLK" O L 5950 4000 60
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F3 "M1_CLK#" O L 5950 4100 60
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F4 "M0_CLK" O L 5950 6050 60
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F5 "M0_CLK#" O L 5950 6150 60
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F6 "ETH_INT" I R 9300 6350 60
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F7 "M0_A[0..12]" O L 5950 5150 60
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F8 "M1_A[0..12]" O L 5950 3050 60
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F9 "M0_DQ[0..15]" B L 5950 5050 60
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2010-08-09 06:53:21 +03:00
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F10 "M0_UDQS" O L 5950 5400 60
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F11 "M0_LDM" O L 5950 5800 60
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F12 "M0_LDQS" O L 5950 5500 60
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F13 "M0_UDM" O L 5950 5700 60
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F14 "M0_RAS#" O L 5950 6400 60
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F15 "M0_WE#" O L 5950 6550 60
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F16 "M0_CKE" O L 5950 5950 60
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F17 "M0_CAS#" O L 5950 6300 60
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F18 "M1_CAS#" O L 5950 4250 60
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F19 "M1_CKE" O L 5950 3900 60
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F20 "M0_CS#" O L 5950 4900 60
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F21 "M1_CS#" O L 5950 2800 60
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F22 "M1_WE#" O L 5950 4500 60
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F23 "M1_RAS#" O L 5950 4350 60
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F24 "M1_UDM" O L 5950 3650 60
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F25 "M1_LDQS" O L 5950 3450 60
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F26 "M1_LDM" O L 5950 3750 60
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F27 "M1_UDQS" O L 5950 3350 60
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F28 "M1_DQ[0..15]" B L 5950 2950 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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2010-08-09 23:37:18 +03:00
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Text HLabel 9300 6500 0 60 Output ~ 0
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ETH_RXC
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Text HLabel 10650 5400 2 60 BiDi ~ 0
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USBA_VM
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Text HLabel 10650 5300 2 60 BiDi ~ 0
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USBA_VP
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Text HLabel 10650 5200 2 60 BiDi ~ 0
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USBA_RCV
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Text HLabel 10650 5100 2 60 BiDi ~ 0
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USBA_OE_N
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Text HLabel 10650 5000 2 60 BiDi ~ 0
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USBA_SPD
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$Sheet
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S 10650 4900 1150 650
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U 4C5F1EDC
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F0 "USB" 60
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F1 "USB.sch" 60
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$EndSheet
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$Sheet
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S 10600 6250 1300 1800
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U 4C4320F3
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F0 "Ethernet Phy" 60
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F1 "eth_phy.sch" 60
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F2 "ETH_RXC" O L 10600 6500 60
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F3 "ETH_RST_N" I L 10600 6600 60
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F4 "ETH_CRS" O L 10600 6700 60
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F5 "ETH_COL" O L 10600 6800 60
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F6 "ETH_INT" O L 10600 6350 60
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F7 "ETH_MDIO" B L 10600 6900 60
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F8 "ETH_MDC" I L 10600 7000 60
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F9 "ETH_RXD[0..3]" O L 10600 7200 60
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F10 "ETH_RXDV" O L 10600 7300 60
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F11 "ETH_RXER" O L 10600 7400 60
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F12 "ETH_TXC" B L 10600 7500 60
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F13 "ETH_TXD[0..3]" I L 10600 7600 60
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F14 "ETH_TXEN" I L 10600 7700 60
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F15 "ETH_TXER" I L 10600 7800 60
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F16 "ETH_CLK" I L 10600 7900 60
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$EndSheet
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2010-07-24 14:58:53 +03:00
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$Sheet
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2010-08-09 01:54:09 +03:00
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S 10650 2700 1150 1850
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2010-07-24 14:58:53 +03:00
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U 4C4227FE
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F0 "Non volatile memories" 60
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F1 "NV_MEMORIES.sch" 60
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$EndSheet
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$Sheet
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2010-08-09 01:54:09 +03:00
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S 3600 2700 1100 4000
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2010-07-24 14:58:53 +03:00
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U 4C421DD3
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F0 "DDR Banks" 60
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F1 "DRAM.sch" 60
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2010-08-09 01:54:09 +03:00
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F2 "M0_BA[0..1]" I R 4700 5250 60
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F3 "M1_BA[0..1]" I R 4700 3150 60
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F4 "M0_WE#" I R 4700 6550 60
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F5 "M0_RAS#" I R 4700 6400 60
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F6 "M1_RAS#" I R 4700 4350 60
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F7 "M1_WE#" I R 4700 4500 60
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F8 "M0_CAS#" I R 4700 6300 60
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F9 "M0_CKE" I R 4700 5950 60
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F10 "M0_CLK" I R 4700 6050 60
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F11 "M0_CLK#" I R 4700 6150 60
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F12 "M0_CS#" I R 4700 4900 60
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F13 "M1_CLK#" I R 4700 4100 60
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F14 "M1_CLK" I R 4700 4000 60
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F15 "M1_CKE" I R 4700 3900 60
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F16 "M1_CAS#" I R 4700 4250 60
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F17 "M0_DQ[0..15]" B R 4700 5050 60
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F18 "M0_UDM" I R 4700 5700 60
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F19 "M0_LDQS" I R 4700 5500 60
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F20 "M0_A[0..12]" I R 4700 5150 60
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F21 "M0_LDM" I R 4700 5800 60
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F22 "M0_UDQS" I R 4700 5400 60
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F23 "M1_UDQS" I R 4700 3350 60
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F24 "M1_LDM" I R 4700 3750 60
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F25 "M1_LDQS" I R 4700 3450 60
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F26 "M1_UDM" I R 4700 3650 60
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F27 "M1_CS#" I R 4700 2800 60
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F28 "M1_A[0..12]" I R 4700 3050 60
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F29 "M1_DQ[0..15]" B R 4700 2950 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$EndSCHEMATC
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