mirror of
git://projects.qi-hardware.com/xue.git
synced 2024-11-08 11:58:27 +02:00
Merge branch 'master' of projects.qi-hardware.com:xue
This commit is contained in:
Andres Calderon
commit
be6e03b56d
BIN
docs/xue-bom.ods
BIN
docs/xue-bom.ods
Binary file not shown.
@ -38,18 +38,18 @@ PrintMonochrome=1
|
||||
ShowSheetReferenceAndTitleBlock=1
|
||||
[eeschema/libraries]
|
||||
LibName1=power
|
||||
LibName2=../library/r_pack2
|
||||
LibName3=../library/v0402mhs03
|
||||
LibName4=../library/usb-48204-0001
|
||||
LibName5=../library/microsmd075f
|
||||
LibName6=../library/mic2550
|
||||
LibName7=../library/rj45-48025
|
||||
LibName8=../library/xue-nv
|
||||
LibName9=../library/xc6slx75fgg484
|
||||
LibName10=../library/xc6slx45fgg484
|
||||
LibName11=../library/micron_mobile_ddr
|
||||
LibName12=../library/micron_ddr_512Mb
|
||||
LibName13=../library/k8001
|
||||
LibName2=../components/r_pack2
|
||||
LibName3=../components/v0402mhs03
|
||||
LibName4=../components/usb-48204-0001
|
||||
LibName5=../components/microsmd075f
|
||||
LibName6=../components/mic2550
|
||||
LibName7=../components/rj45-48025
|
||||
LibName8=../components/xue-nv
|
||||
LibName9=../components/xc6slx75fgg484
|
||||
LibName10=../components/xc6slx45fgg484
|
||||
LibName11=../components/micron_mobile_ddr
|
||||
LibName12=../components/micron_ddr_512Mb
|
||||
LibName13=../components/k8001
|
||||
LibName14=device
|
||||
LibName15=transistors
|
||||
LibName16=conn
|
||||
@ -79,18 +79,18 @@ LibName39=opto
|
||||
LibName40=atmel
|
||||
LibName41=contrib
|
||||
LibName42=valves
|
||||
LibName43=../library/pasives-connectors
|
||||
LibName44=../library/x25x64mb
|
||||
LibName45=../library/attiny
|
||||
LibName46=../library/PSU
|
||||
LibName47=../library/tps793xx
|
||||
LibName48=../library/reg102
|
||||
LibName49=../library/mt9m033
|
||||
LibName50=../library/m12-tu400a
|
||||
LibName51=../library/ft2232c
|
||||
LibName52=../library/fxo-hc536r
|
||||
LibName53=../library/zx62d-b-5p8
|
||||
LibName54=../library/a7130
|
||||
LibName43=../components/pasives-connectors
|
||||
LibName44=../components/x25x64mb
|
||||
LibName45=../components/attiny
|
||||
LibName46=../components/PSU
|
||||
LibName47=../components/tps793xx
|
||||
LibName48=../components/reg102
|
||||
LibName49=../components/mt9m033
|
||||
LibName50=../components/m12-tu400a
|
||||
LibName51=../components/ft2232c
|
||||
LibName52=../components/fxo-hc536r
|
||||
LibName53=../components/zx62d-b-5p8
|
||||
LibName54=../components/a7130
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
|
||||
Binary file not shown.
Binary file not shown.
2031
sim/verilog/micron_2048Mb_ddr2/ddr2.v
Normal file
2031
sim/verilog/micron_2048Mb_ddr2/ddr2.v
Normal file
File diff suppressed because it is too large
Load Diff
94
sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v
Normal file
94
sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v
Normal file
@ -0,0 +1,94 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: ddr2_mcp.v
|
||||
*
|
||||
* Dependencies: ddr2.v, ddr2_parameters.vh
|
||||
*
|
||||
* Description: Micron SDRAM DDR2 (Double Data Rate 2) multi-chip package model
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
****************************************************************************************/
|
||||
`timescale 1ps / 1ps
|
||||
|
||||
module ddr2_mcp (
|
||||
ck,
|
||||
ck_n,
|
||||
cke,
|
||||
cs_n,
|
||||
ras_n,
|
||||
cas_n,
|
||||
we_n,
|
||||
dm_rdqs,
|
||||
ba,
|
||||
addr,
|
||||
dq,
|
||||
dqs,
|
||||
dqs_n,
|
||||
rdqs_n,
|
||||
odt
|
||||
);
|
||||
|
||||
`include "ddr2_parameters.vh"
|
||||
|
||||
// Declare Ports
|
||||
input ck;
|
||||
input ck_n;
|
||||
input [CS_BITS-1:0] cke;
|
||||
input [CS_BITS-1:0] cs_n;
|
||||
input ras_n;
|
||||
input cas_n;
|
||||
input we_n;
|
||||
inout [DM_BITS-1:0] dm_rdqs;
|
||||
input [BA_BITS-1:0] ba;
|
||||
input [ADDR_BITS-1:0] addr;
|
||||
inout [DQ_BITS-1:0] dq;
|
||||
inout [DQS_BITS-1:0] dqs;
|
||||
inout [DQS_BITS-1:0] dqs_n;
|
||||
output [DQS_BITS-1:0] rdqs_n;
|
||||
input [CS_BITS-1:0] odt;
|
||||
|
||||
wire [RANKS-1:0] cke_mcp = cke;
|
||||
wire [RANKS-1:0] cs_n_mcp = cs_n;
|
||||
wire [RANKS-1:0] odt_mcp = odt;
|
||||
|
||||
ddr2 rank [RANKS-1:0] (
|
||||
ck,
|
||||
ck_n,
|
||||
cke_mcp,
|
||||
cs_n_mcp,
|
||||
ras_n,
|
||||
cas_n,
|
||||
we_n,
|
||||
dm_rdqs,
|
||||
ba,
|
||||
addr,
|
||||
dq,
|
||||
dqs,
|
||||
dqs_n,
|
||||
rdqs_n,
|
||||
odt_mcp
|
||||
);
|
||||
|
||||
endmodule
|
||||
377
sim/verilog/micron_2048Mb_ddr2/ddr2_module.v
Normal file
377
sim/verilog/micron_2048Mb_ddr2/ddr2_module.v
Normal file
@ -0,0 +1,377 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: ddr2_module.v
|
||||
*
|
||||
* Dependencies: ddr2.v, ddr2.v, ddr2_parameters.vh
|
||||
*
|
||||
* Description: Micron SDRAM DDR2 (Double Data Rate 2) module model
|
||||
*
|
||||
* Limitation: - SPD (Serial Presence-Detect) is not modeled
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
* Rev Author Date Changes
|
||||
* ---------------------------------------------------------------------------------------
|
||||
* 1.00 SPH 09/18/09 Fixed cb connection in ECC mode
|
||||
* Added invalid ECC mode error message in x16 configuration
|
||||
****************************************************************************************/
|
||||
`timescale 1ps / 1ps
|
||||
|
||||
module ddr2_module (
|
||||
`ifdef SODIMM
|
||||
`else
|
||||
reset_n,
|
||||
cb ,
|
||||
`endif
|
||||
ck ,
|
||||
ck_n ,
|
||||
cke ,
|
||||
s_n ,
|
||||
ras_n ,
|
||||
cas_n ,
|
||||
we_n ,
|
||||
ba ,
|
||||
addr ,
|
||||
odt ,
|
||||
dqs ,
|
||||
dqs_n ,
|
||||
dq ,
|
||||
scl ,
|
||||
sa ,
|
||||
sda
|
||||
);
|
||||
|
||||
`include "ddr2_parameters.vh"
|
||||
|
||||
input [1:0] cke ;
|
||||
input ras_n ;
|
||||
input cas_n ;
|
||||
input we_n ;
|
||||
input [2:0] ba ;
|
||||
input [15:0] addr ;
|
||||
input [1:0] odt ;
|
||||
inout [17:0] dqs ;
|
||||
inout [17:0] dqs_n ;
|
||||
inout [63:0] dq ;
|
||||
input scl ; // no connect
|
||||
inout sda ; // no connect
|
||||
|
||||
`ifdef QUAD_RANK
|
||||
initial if (DEBUG) $display("%m: Quad Rank");
|
||||
`else `ifdef DUAL_RANK
|
||||
initial if (DEBUG) $display("%m: Dual Rank");
|
||||
`else
|
||||
initial if (DEBUG) $display("%m: Single Rank");
|
||||
`endif `endif
|
||||
|
||||
`ifdef ECC
|
||||
initial if (DEBUG) $display("%m: ECC");
|
||||
`ifdef SODIMM
|
||||
initial begin
|
||||
$display("%m ERROR: ECC is not available on SODIMM configurations");
|
||||
if (STOP_ON_ERROR) $stop(0);
|
||||
end
|
||||
`endif
|
||||
`ifdef x16
|
||||
initial begin
|
||||
$display("%m ERROR: ECC is not available on x16 configurations");
|
||||
if (STOP_ON_ERROR) $stop(0);
|
||||
end
|
||||
`endif
|
||||
`else
|
||||
initial if (DEBUG) $display("%m: non ECC");
|
||||
`endif
|
||||
|
||||
`ifdef RDIMM
|
||||
initial if (DEBUG) $display("%m: RDIMM");
|
||||
input reset_n;
|
||||
input ck ;
|
||||
input ck_n ;
|
||||
input [3:0] s_n ;
|
||||
inout [7:0] cb ;
|
||||
input [2:0] sa ; // no connect
|
||||
|
||||
wire [5:0] rck = {6{ck}};
|
||||
wire [5:0] rck_n = {6{ck_n}};
|
||||
reg [3:0] rs_n ;
|
||||
reg rras_n ;
|
||||
reg rcas_n ;
|
||||
reg rwe_n ;
|
||||
reg [2:0] rba ;
|
||||
reg [15:0] raddr ;
|
||||
reg [3:0] rcke ;
|
||||
reg [3:0] rodt ;
|
||||
|
||||
always @(negedge reset_n or posedge ck) begin
|
||||
if (!reset_n) begin
|
||||
rs_n <= #(500) 0;
|
||||
rras_n <= #(500) 0;
|
||||
rcas_n <= #(500) 0;
|
||||
rwe_n <= #(500) 0;
|
||||
rba <= #(500) 0;
|
||||
raddr <= #(500) 0;
|
||||
rcke <= #(500) 0;
|
||||
rodt <= #(500) 0;
|
||||
end else begin
|
||||
rs_n <= #(500) s_n ;
|
||||
rras_n <= #(500) ras_n;
|
||||
rcas_n <= #(500) cas_n;
|
||||
rwe_n <= #(500) we_n ;
|
||||
rba <= #(500) ba ;
|
||||
raddr <= #(500) addr ;
|
||||
`ifdef QUAD_RANK
|
||||
rcke <= #(500) {{2{cke[1]}}, {2{cke[0]}}};
|
||||
rodt <= #(500) {{2{odt[1]}}, {2{odt[0]}}};
|
||||
`else
|
||||
rcke <= #(500) {2'b00, cke};
|
||||
rodt <= #(500) {2'b00, odt};
|
||||
`endif
|
||||
|
||||
end
|
||||
end
|
||||
`else
|
||||
`ifdef SODIMM
|
||||
initial if (DEBUG) $display("%m: SODIMM");
|
||||
input [1:0] ck ;
|
||||
input [1:0] ck_n ;
|
||||
input [1:0] s_n ;
|
||||
input [1:0] sa ; // no connect
|
||||
|
||||
wire [7:0] cb;
|
||||
wire [5:0] rck = {{3{ck[1]}}, {3{ck[0]}}};
|
||||
wire [5:0] rck_n = {{3{ck_n[1]}}, {3{ck_n[0]}}};
|
||||
`else
|
||||
initial if (DEBUG) $display("%m: UDIMM");
|
||||
input reset_n;
|
||||
input [2:0] ck ;
|
||||
input [2:0] ck_n ;
|
||||
input [1:0] s_n ;
|
||||
inout [7:0] cb ;
|
||||
input [2:0] sa ; // no connect
|
||||
|
||||
wire [5:0] rck = {2{ck}};
|
||||
wire [5:0] rck_n = {2{ck_n}};
|
||||
`endif
|
||||
|
||||
wire [2:0] rba = ba ;
|
||||
wire [15:0] raddr = addr ;
|
||||
wire rras_n = ras_n;
|
||||
wire rcas_n = cas_n;
|
||||
wire rwe_n = we_n ;
|
||||
`ifdef QUAD_RANK
|
||||
wire [3:0] rs_n = {{2{s_n[1]}}, {2{s_n[0]}}};
|
||||
wire [3:0] rcke = {{2{cke[1]}}, {2{cke[0]}}};
|
||||
wire [3:0] rodt = {{2{odt[1]}}, {2{odt[0]}}};
|
||||
`else
|
||||
wire [3:0] rs_n = {2'b00, s_n};
|
||||
wire [3:0] rcke = {2'b00, cke};
|
||||
wire [3:0] rodt = {2'b00, odt};
|
||||
`endif
|
||||
`endif
|
||||
wire [15:0] rcb = {8'b0, cb};
|
||||
wire zero = 1'b0;
|
||||
wire one = 1'b1;
|
||||
|
||||
//ddr2 (ck , ck_n , cke , cs_n , ras_n , cas_n , we_n , dm_rdqs , ba , addr , dq , dqs , dqs_n , rdqs_n , odt );
|
||||
`ifdef x4
|
||||
initial if (DEBUG) $display("%m: Component Width = x4");
|
||||
ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[0]);
|
||||
ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[0]);
|
||||
ddr2 U3R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[0]);
|
||||
ddr2 U4R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[0]);
|
||||
ddr2 U6R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[0]);
|
||||
ddr2 U7R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[0]);
|
||||
ddr2 U8R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[0]);
|
||||
ddr2 U9R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[0]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[0]);
|
||||
`endif
|
||||
ddr2 U18R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[0]);
|
||||
ddr2 U17R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[0]);
|
||||
ddr2 U16R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[0]);
|
||||
ddr2 U15R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[0]);
|
||||
ddr2 U13R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[0]);
|
||||
ddr2 U12R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[0]);
|
||||
ddr2 U11R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[0]);
|
||||
ddr2 U10R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[0]);
|
||||
`ifdef ECC
|
||||
ddr2 U14R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[0]);
|
||||
`endif
|
||||
`ifdef DUAL_RANK
|
||||
ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[1]);
|
||||
ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[1]);
|
||||
ddr2 U3R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[1]);
|
||||
ddr2 U4R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[1]);
|
||||
ddr2 U6R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[1]);
|
||||
ddr2 U7R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[1]);
|
||||
ddr2 U8R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[1]);
|
||||
ddr2 U9R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[1]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[1]);
|
||||
`endif
|
||||
ddr2 U18R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[1]);
|
||||
ddr2 U17R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[1]);
|
||||
ddr2 U16R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[1]);
|
||||
ddr2 U15R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[1]);
|
||||
ddr2 U13R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[1]);
|
||||
ddr2 U12R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[1]);
|
||||
ddr2 U11R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[1]);
|
||||
ddr2 U10R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[1]);
|
||||
`ifdef ECC
|
||||
ddr2 U14R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[1]);
|
||||
`endif
|
||||
`endif
|
||||
`ifdef QUAD_RANK
|
||||
ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[2]);
|
||||
ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[2]);
|
||||
ddr2 U3R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[2]);
|
||||
ddr2 U4R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[2]);
|
||||
ddr2 U6R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[2]);
|
||||
ddr2 U7R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[2]);
|
||||
ddr2 U8R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[2]);
|
||||
ddr2 U9R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[2]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[2]);
|
||||
`endif
|
||||
ddr2 U18R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[2]);
|
||||
ddr2 U17R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[2]);
|
||||
ddr2 U16R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[2]);
|
||||
ddr2 U15R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[2]);
|
||||
ddr2 U13R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[2]);
|
||||
ddr2 U12R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[2]);
|
||||
ddr2 U11R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[2]);
|
||||
ddr2 U10R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[2]);
|
||||
`ifdef ECC
|
||||
ddr2 U14R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[2]);
|
||||
`endif
|
||||
ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[ 0] , dqs_n[ 0], , rodt[3]);
|
||||
ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[ 1] , dqs_n[ 1], , rodt[3]);
|
||||
ddr2 U3R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[ 2] , dqs_n[ 2], , rodt[3]);
|
||||
ddr2 U4R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[ 3] , dqs_n[ 3], , rodt[3]);
|
||||
ddr2 U6R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[ 4] , dqs_n[ 4], , rodt[3]);
|
||||
ddr2 U7R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[ 5] , dqs_n[ 5], , rodt[3]);
|
||||
ddr2 U8R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[ 6] , dqs_n[ 6], , rodt[3]);
|
||||
ddr2 U9R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[ 7] , dqs_n[ 7], , rodt[3]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[ 8] , dqs_n[ 8], , rodt[3]);
|
||||
`endif
|
||||
ddr2 U18R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[ 9] , dqs_n[ 9], , rodt[3]);
|
||||
ddr2 U17R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10] , dqs_n[ 10], , rodt[3]);
|
||||
ddr2 U16R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11] , dqs_n[ 11], , rodt[3]);
|
||||
ddr2 U15R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12] , dqs_n[ 12], , rodt[3]);
|
||||
ddr2 U13R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13] , dqs_n[ 13], , rodt[3]);
|
||||
ddr2 U12R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14] , dqs_n[ 14], , rodt[3]);
|
||||
ddr2 U11R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15] , dqs_n[ 15], , rodt[3]);
|
||||
ddr2 U10R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16] , dqs_n[ 16], , rodt[3]);
|
||||
`ifdef ECC
|
||||
ddr2 U14R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17] , dqs_n[ 17], , rodt[3]);
|
||||
`endif
|
||||
`endif
|
||||
`else `ifdef x8
|
||||
initial if (DEBUG) $display("%m: Component Width = x8");
|
||||
ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[0]);
|
||||
ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[0]);
|
||||
ddr2 U3R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[0]);
|
||||
ddr2 U4R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[0]);
|
||||
ddr2 U6R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[0]);
|
||||
ddr2 U7R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[0]);
|
||||
ddr2 U8R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[0]);
|
||||
ddr2 U9R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[0]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[0]);
|
||||
`endif
|
||||
`ifdef DUAL_RANK
|
||||
ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[1]);
|
||||
ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[1]);
|
||||
ddr2 U3R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[1]);
|
||||
ddr2 U4R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[1]);
|
||||
ddr2 U6R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[1]);
|
||||
ddr2 U7R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[1]);
|
||||
ddr2 U8R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[1]);
|
||||
ddr2 U9R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[1]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[1]);
|
||||
`endif
|
||||
`endif
|
||||
`ifdef QUAD_RANK
|
||||
ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[2]);
|
||||
ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[2]);
|
||||
ddr2 U3R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[2]);
|
||||
ddr2 U4R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[2]);
|
||||
ddr2 U6R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[2]);
|
||||
ddr2 U7R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[2]);
|
||||
ddr2 U8R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[2]);
|
||||
ddr2 U9R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[2]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[2]);
|
||||
`endif
|
||||
ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[ 9] , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[ 0] , dqs_n[ 0], dqs_n[ 9], rodt[3]);
|
||||
ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10] , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[ 1] , dqs_n[ 1], dqs_n[10], rodt[3]);
|
||||
ddr2 U3R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[11] , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[ 2] , dqs_n[ 2], dqs_n[11], rodt[3]);
|
||||
ddr2 U4R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12] , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[ 3] , dqs_n[ 3], dqs_n[12], rodt[3]);
|
||||
ddr2 U6R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[13] , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[ 4] , dqs_n[ 4], dqs_n[13], rodt[3]);
|
||||
ddr2 U7R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14] , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[ 5] , dqs_n[ 5], dqs_n[14], rodt[3]);
|
||||
ddr2 U8R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[15] , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[ 6] , dqs_n[ 6], dqs_n[15], rodt[3]);
|
||||
ddr2 U9R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16] , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[ 7] , dqs_n[ 7], dqs_n[16], rodt[3]);
|
||||
`ifdef ECC
|
||||
ddr2 U5R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[17] , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[ 8] , dqs_n[ 8], dqs_n[17], rodt[3]);
|
||||
`endif
|
||||
`endif
|
||||
`else `ifdef x16
|
||||
initial if (DEBUG) $display("%m: Component Width = x16");
|
||||
ddr2 U1R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[0]);
|
||||
ddr2 U2R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[0]);
|
||||
ddr2 U4R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[0]);
|
||||
ddr2 U5R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[0]);
|
||||
`ifdef ECC
|
||||
ddr2 U3R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[0]);
|
||||
`endif
|
||||
`ifdef DUAL_RANK
|
||||
ddr2 U1R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[1]);
|
||||
ddr2 U2R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[1]);
|
||||
ddr2 U4R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[1]);
|
||||
ddr2 U5R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[1]);
|
||||
`ifdef ECC
|
||||
ddr2 U3R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[1]);
|
||||
`endif
|
||||
`endif
|
||||
`ifdef QUAD_RANK
|
||||
ddr2 U1R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[2]);
|
||||
ddr2 U2R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[2]);
|
||||
ddr2 U4R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[2]);
|
||||
ddr2 U5R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[2]);
|
||||
`ifdef ECC
|
||||
ddr2 U3R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[2]);
|
||||
`endif
|
||||
ddr2 U1R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10: 9] , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0] , dqs_n[1:0], , rodt[3]);
|
||||
ddr2 U2R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12:11] , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2] , dqs_n[3:2], , rodt[3]);
|
||||
ddr2 U4R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14:13] , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4] , dqs_n[5:4], , rodt[3]);
|
||||
ddr2 U5R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16:15] , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6] , dqs_n[7:6], , rodt[3]);
|
||||
`ifdef ECC
|
||||
ddr2 U3R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]}, , rodt[3]);
|
||||
`endif
|
||||
`endif
|
||||
`endif `endif `endif
|
||||
|
||||
endmodule
|
||||
383
sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh
Normal file
383
sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh
Normal file
@ -0,0 +1,383 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with 2Gb datasheet rev B
|
||||
|
||||
// Timing parameters based on Speed Grade
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg187E
|
||||
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 75; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 132; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 157; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 175; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 188; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 250; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 425; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 250; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 350; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 0; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 75; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 175; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 125; // tIS ps Input Setup Time
|
||||
parameter TIH = 200; // tIH ps Input Hold Time
|
||||
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 13125; // tRP ps Precharge command period
|
||||
parameter TRPA = 15000; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 10; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 3; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 3; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 4; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 11; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
|
||||
`else `ifdef sg25E
|
||||
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 175; // tIS ps Input Setup Time
|
||||
parameter TIH = 250; // tIH ps Input Hold Time
|
||||
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 12500; // tRP ps Precharge command period
|
||||
parameter TRPA = 15000; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
|
||||
`else `ifdef sg25
|
||||
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 300; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 175; // tIS ps Input Setup Time
|
||||
parameter TIH = 250; // tIH ps Input Hold Time
|
||||
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 15000; // tRP ps Precharge command period
|
||||
parameter TRPA = 17500; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 10; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
||||
`else `ifdef sg3E
|
||||
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 200; // tIS ps Input Setup Time
|
||||
parameter TIH = 275; // tIH ps Input Hold Time
|
||||
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 12000; // tRP ps Precharge command period
|
||||
parameter TRPA = 15000; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
|
||||
`else `ifdef sg3
|
||||
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 340; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 200; // tIS ps Input Setup Time
|
||||
parameter TIH = 275; // tIH ps Input Hold Time
|
||||
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 15000; // tRP ps Precharge command period
|
||||
parameter TRPA = 18000; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
||||
`else `ifdef sg37E
|
||||
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 400; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 250; // tIS ps Input Setup Time
|
||||
parameter TIH = 375; // tIH ps Input Hold Time
|
||||
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 7500; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 15000; // tRP ps Precharge command period
|
||||
parameter TRPA = 18750; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
||||
`else `define sg5E
|
||||
parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
|
||||
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
|
||||
parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
|
||||
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
|
||||
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
|
||||
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
|
||||
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
|
||||
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
|
||||
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
|
||||
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
|
||||
parameter TQHS = 450; // tQHS ps Data hold skew factor
|
||||
parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
|
||||
parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
|
||||
parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
|
||||
parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
|
||||
parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter TIS = 350; // tIS ps Input Setup Time
|
||||
parameter TIH = 475; // tIH ps Input Hold Time
|
||||
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
|
||||
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
|
||||
parameter TWTR = 10000; // tWTR ps Write to Read command delay
|
||||
parameter TRP = 15000; // tRP ps Precharge command period
|
||||
parameter TRPA = 20000; // tRPA ps Precharge All period
|
||||
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
|
||||
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
|
||||
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
|
||||
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
|
||||
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
|
||||
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
|
||||
`endif `endif `endif `endif `endif `endif
|
||||
|
||||
`ifdef x16
|
||||
`ifdef sg187E
|
||||
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
||||
`else `ifdef sg25E
|
||||
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
||||
`else `ifdef sg25
|
||||
parameter TFAW = 45000; // tFAW ps Four Bank Activate window
|
||||
`else // sg3E, sg3, sg37E, sg5E
|
||||
parameter TFAW = 50000; // tFAW ps Four Bank Activate window
|
||||
`endif `endif `endif
|
||||
`else // x4, x8
|
||||
`ifdef sg187E
|
||||
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
||||
`else `ifdef sg25E
|
||||
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
||||
`else `ifdef sg25
|
||||
parameter TFAW = 35000; // tFAW ps Four Bank Activate window
|
||||
`else // sg3E, sg3, sg37E, sg5E
|
||||
parameter TFAW = 37500; // tFAW ps Four Bank Activate window
|
||||
`endif `endif `endif
|
||||
`endif
|
||||
|
||||
// Timing Parameters
|
||||
|
||||
// Mode Register
|
||||
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
|
||||
parameter AL_MAX = 6; // AL tCK Maximum Additive Latency
|
||||
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
|
||||
parameter CL_MAX = 7; // CL tCK Maximum CAS Latency
|
||||
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
|
||||
parameter WR_MAX = 8; // WR tCK Maximum Write Recovery
|
||||
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
|
||||
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
|
||||
// Clock
|
||||
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
|
||||
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
|
||||
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
|
||||
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
|
||||
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
|
||||
// Data
|
||||
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
|
||||
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
|
||||
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
|
||||
// Data Strobe
|
||||
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
|
||||
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
|
||||
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
|
||||
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
|
||||
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
|
||||
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
|
||||
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
|
||||
// Command and Address
|
||||
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
|
||||
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
|
||||
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
|
||||
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
|
||||
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
|
||||
parameter TWR = 15000; // tWR ps Write recovery time
|
||||
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter TDLLK = 200; // tDLLK tCK DLL locking time
|
||||
// Refresh
|
||||
parameter TRFC_MIN = 197500; // tRFC ps Refresh to Refresh Command interval minimum value
|
||||
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
|
||||
// Self Refresh
|
||||
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
|
||||
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
|
||||
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
|
||||
// ODT
|
||||
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
|
||||
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
|
||||
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
|
||||
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
|
||||
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
|
||||
// Power Down
|
||||
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
|
||||
`ifdef x4
|
||||
parameter ADDR_BITS = 15; // Address Bits
|
||||
parameter ROW_BITS = 15; // Number of Address bits
|
||||
parameter COL_BITS = 11; // Number of Column bits
|
||||
parameter DM_BITS = 1; // Number of Data Mask bits
|
||||
parameter DQ_BITS = 4; // Number of Data bits
|
||||
parameter DQS_BITS = 1; // Number of Dqs bits
|
||||
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
||||
`else `ifdef x8
|
||||
parameter ADDR_BITS = 15; // Address Bits
|
||||
parameter ROW_BITS = 15; // Number of Address bits
|
||||
parameter COL_BITS = 10; // Number of Column bits
|
||||
parameter DM_BITS = 1; // Number of Data Mask bits
|
||||
parameter DQ_BITS = 8; // Number of Data bits
|
||||
parameter DQS_BITS = 1; // Number of Dqs bits
|
||||
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
|
||||
`else `define x16
|
||||
parameter ADDR_BITS = 14; // Address Bits
|
||||
parameter ROW_BITS = 14; // Number of Address bits
|
||||
parameter COL_BITS = 10; // Number of Column bits
|
||||
parameter DM_BITS = 2; // Number of Data Mask bits
|
||||
parameter DQ_BITS = 16; // Number of Data bits
|
||||
parameter DQS_BITS = 2; // Number of Dqs bits
|
||||
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
|
||||
`endif `endif
|
||||
|
||||
`ifdef QUAD_RANK
|
||||
`define DUAL_RANK // also define DUAL_RANK
|
||||
parameter CS_BITS = 4; // Number of Chip Select Bits
|
||||
parameter RANKS = 4; // Number of Chip Select Bits
|
||||
`else `ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Number of Chip Select Bits
|
||||
parameter RANKS = 2; // Number of Chip Select Bits
|
||||
`else
|
||||
parameter CS_BITS = 2; // Number of Chip Select Bits
|
||||
parameter RANKS = 1; // Number of Chip Select Bits
|
||||
`endif `endif
|
||||
|
||||
// Size Parameters
|
||||
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits
|
||||
parameter MEM_BITS = 10; // Number of write data bursts can be stored in memory. The default is 2^10=1024.
|
||||
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
|
||||
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
|
||||
parameter BO_BITS = 2; // the number of Burst Order Bits
|
||||
|
||||
// Simulation parameters
|
||||
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
|
||||
parameter DEBUG = 1; // Turn on Debug messages
|
||||
parameter BUS_DELAY = 0; // delay in nanoseconds
|
||||
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
|
||||
parameter RANDOM_SEED = 711689044; //seed value for random generator.
|
||||
|
||||
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
|
||||
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
|
||||
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
|
||||
parameter RDQS_PST = 1; // DQS low time after last valid read strobe
|
||||
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
|
||||
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
|
||||
parameter WDQS_PRE = 1; // DQS half clock periods prior to first write strobe
|
||||
parameter WDQS_PST = 1; // DQS half clock periods after last valid write strobe
|
||||
190
sim/verilog/micron_2048Mb_ddr2/readme.txt
Normal file
190
sim/verilog/micron_2048Mb_ddr2/readme.txt
Normal file
@ -0,0 +1,190 @@
|
||||
Disclaimer of Warranty:
|
||||
-----------------------
|
||||
This software code and all associated documentation, comments or other
|
||||
information (collectively "Software") is provided "AS IS" without
|
||||
warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
limitation of liability for consequential or incidental damages, the
|
||||
above limitation may not apply to you.
|
||||
|
||||
Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
|
||||
Getting Started:
|
||||
----------------
|
||||
Unzip the included files to a folder.
|
||||
Compile ddr2.v, ddr2_mcp.v, and tb.v using a verilog simulator.
|
||||
Simulate the top level test bench tb.
|
||||
Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
|
||||
|
||||
File Descriptions:
|
||||
------------------
|
||||
ddr2.v -ddr2 model
|
||||
ddr2_mcp.v -structural wrapper for ddr2 - multi-chip package model
|
||||
ddr2_module.v -structural wrapper for ddr2 - module model
|
||||
ddr2_parameters.vh -file that contains all parameters used by the model
|
||||
readme.txt -this file
|
||||
tb.v -ddr2 model test bench
|
||||
subtest.vh -example test included by the test bench.
|
||||
tb.do -compiles and runs the ddr2 model and test bench
|
||||
|
||||
Defining the Speed Grade:
|
||||
-------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
multiple speed grades supported by the ddr2 model. Allowable speed
|
||||
grades are listed in the ddr2_parameters.vh file and begin with the
|
||||
letters "sg". The speed grade is used to select a set of timing
|
||||
parameters for the ddr2 model. The following are examples of defining
|
||||
the speed grade.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+sg5 ddr2.v
|
||||
NC-Verilog ncverilog +define+sg5 ddr2.v
|
||||
VCS vcs +define+sg5 ddr2.v
|
||||
|
||||
Defining the Organization:
|
||||
--------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
multiple organizations supported by the ddr2 model. Valid
|
||||
organizations include "x4", "x8", and x16, and are listed in the
|
||||
ddr2_parameters.vh file. The organization is used to select the amount
|
||||
of memory and the port sizes of the ddr2 model. The following are
|
||||
examples of defining the organization.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+x8 ddr2.v
|
||||
NC-Verilog ncverilog +define+x8 ddr2.v
|
||||
VCS vcs +define+x8 ddr2.v
|
||||
|
||||
All combinations of speed grade and organization are considered valid
|
||||
by the ddr2 model even though a Micron part may not exist for every
|
||||
combination.
|
||||
|
||||
Allocating Memory:
|
||||
------------------
|
||||
An associative array has been implemented to reduce the amount of
|
||||
static memory allocated by the ddr2 model. Each entry in the
|
||||
associative array is a burst length of eight in size. The number of
|
||||
entries in the associative array is controlled by the MEM_BITS
|
||||
parameter, and is equal to 2^MEM_BITS. For example, if the MEM_BITS
|
||||
parameter is equal to 10, the associative array will be large enough
|
||||
to store 1024 writes of burst length 8 to unique addresses. The
|
||||
following are examples of setting the MEM_BITS parameter to 8.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vsim -GMEM_BITS=8 ddr2
|
||||
NC-Verilog ncverilog +defparam+ddr2.MEM_BITS=8 ddr2.v
|
||||
VCS vcs -pvalue+MEM_BITS=8 ddr2.v
|
||||
|
||||
It is possible to allocate memory for every address supported by the
|
||||
ddr2 model by using the verilog compiler directive "`define MAX_MEM".
|
||||
This procedure will improve simulation performance at the expense of
|
||||
system memory. The following are examples of allocating memory for
|
||||
every address.
|
||||
|
||||
Simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+MAX_MEM ddr2.v
|
||||
NC-Verilog ncverilog +define+MAX_MEM ddr2.v
|
||||
VCS vcs +define+MAX_MEM ddr2.v
|
||||
|
||||
|
||||
**********************************************************************
|
||||
The following information is provided to assist the modeling engineer
|
||||
in creating multi-chip package (mcp) models. ddr2_mcp.v is a
|
||||
structural wrapper that instantiates ddr2 models. This wrapper can be
|
||||
used to create single, dual, or quad rank mcp models. From the
|
||||
perspective of the model, the only item that needs to be defined is the
|
||||
number of ranks.
|
||||
**********************************************************************
|
||||
|
||||
Defining the Number of Ranks in a multi-chip package:
|
||||
----------------------------------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
single, dual, and quad rank mcp configurations. The default is single
|
||||
rank if nothing is defined. Dual rank configuration can be selected by
|
||||
defining "DUAL_RANK" when the ddr2_mcp is compiled. Quad rank
|
||||
configuration can be selected by defining "QUAD_RANK" when the ddr2_mcp
|
||||
is compiled. The following are examples of defining a dual rank mcp
|
||||
configuration.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+DUAL_RANK ddr2.v ddr2_mcp.v
|
||||
NC-Verilog ncverilog +define+DUAL_RANK ddr2.v ddr2_mcp.v
|
||||
VCS vcs +define+DUAL_RANK ddr2.v ddr2_mcp.v
|
||||
|
||||
|
||||
**********************************************************************
|
||||
The following information is provided to assist the modeling engineer
|
||||
in creating DIMM models. ddr2_module.v is a structural wrapper that
|
||||
instantiates ddr2 models. This wrapper can be used to create UDIMM,
|
||||
RDIMM or SODIMM models. Other form factors are not supported
|
||||
(MiniDIMM, VLP DIMM, etc.). From the perspective of the model, the
|
||||
items that need to be defined are the number of ranks, the module
|
||||
type, and the presence of ECC. All combinations of ranks, module
|
||||
type, and ECC are considered valid by the ddr2_module model even
|
||||
though a Micron part may not exist for every combination.
|
||||
**********************************************************************
|
||||
|
||||
Defining the Number of Ranks on a module:
|
||||
----------------------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
single, dual, and quad rank module configurations. The default is single
|
||||
rank if nothing is defined. Dual rank configuration can be selected by
|
||||
defining "DUAL_RANK" when the ddr2_module is compiled. Quad rank
|
||||
configuration can be selected by defining "QUAD_RANK" when the ddr2_module
|
||||
is compiled. The following are examples of defining a dual rank module
|
||||
configuration.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+DUAL_RANK ddr2.v ddr2_module.v
|
||||
NC-Verilog ncverilog +define+DUAL_RANK ddr2.v ddr2_module.v
|
||||
VCS vcs +define+DUAL_RANK ddr2.v ddr2_module.v
|
||||
|
||||
Defining the Module Type:
|
||||
-----------------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
UDIMM, RDIMM, and SODIMM module configurations. The default is
|
||||
unregistered (UDIMM) if nothing is defined. SODIMM configuration can be
|
||||
selected by defining "SODIMM" when the ddr2_module is compiled. Registered
|
||||
configuration can be selected by defining "RDIMM" when the ddr2_module is
|
||||
compiled. The following are examples of defining a registered module
|
||||
configuration.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+RDIMM ddr2.v ddr2_module.v
|
||||
NC-Verilog ncverilog +define+RDIMM ddr2.v ddr2_module.v
|
||||
VCS vcs +define+RDIMM ddr2.v ddr2_module.v
|
||||
|
||||
Defining the ECC for a module:
|
||||
-----------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
ECC and nonECC module configurations. The default is nonECC if nothing
|
||||
is defined. ECC configuration can be selected by defining "ECC" when
|
||||
the ddr2_module is compiled. The following are examples of defining an
|
||||
ECC module configuration.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+ECC ddr2.v ddr2_module.v
|
||||
NC-Verilog ncverilog +define+ECC ddr2.v ddr2_module.v
|
||||
VCS vcs +define+ECC ddr2.v ddr2_module.v
|
||||
225
sim/verilog/micron_2048Mb_ddr2/subtest.vh
Normal file
225
sim/verilog/micron_2048Mb_ddr2/subtest.vh
Normal file
@ -0,0 +1,225 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: subtest.vh
|
||||
*
|
||||
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
|
||||
* This file is included by tb.v
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
initial begin : test
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b1;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
ba <= {BA_BITS{1'bz}};
|
||||
a <= {ADDR_BITS{1'bz}};
|
||||
odt <= 1'b0;
|
||||
dq_en <= 1'b0;
|
||||
dqs_en <= 1'b0;
|
||||
|
||||
cke <= 1'b1;
|
||||
|
||||
// POWERUP SECTION
|
||||
power_up;
|
||||
|
||||
// INITIALIZE SECTION
|
||||
precharge (0, 1); // Precharge all banks
|
||||
nop (trp);
|
||||
|
||||
load_mode (2, 0); // Extended Mode Register (2)
|
||||
nop (tmrd-1);
|
||||
|
||||
load_mode (3, 0); // Extended Mode Register (3)
|
||||
nop (tmrd-1);
|
||||
|
||||
load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable
|
||||
nop (tmrd-1);
|
||||
|
||||
load_mode (0, 13'b0_000_1_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
|
||||
nop (tmrd-1);
|
||||
|
||||
precharge (0, 1); // Precharge all banks
|
||||
nop (trp);
|
||||
|
||||
refresh;
|
||||
nop (trfc-1);
|
||||
|
||||
refresh;
|
||||
nop (trfc-1);
|
||||
|
||||
load_mode (0, 13'b0_000_0_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
|
||||
nop (tmrd-1);
|
||||
|
||||
load_mode (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default
|
||||
nop (tmrd-1);
|
||||
|
||||
load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit
|
||||
nop (tmrd-1);
|
||||
|
||||
// DLL RESET ENABLE - you will need 200 TCK before any read command.
|
||||
nop (200);
|
||||
|
||||
// WRITE SECTION
|
||||
activate (0, 0); // Activate Bank 0, Row 0
|
||||
nop (trcd-1);
|
||||
write (0, 4, 0, 0, 'h3210); // Write Bank 0, Col 0
|
||||
nop (tccd-1);
|
||||
write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0
|
||||
|
||||
activate (1, 0); // Activate Bank 1, Row 0
|
||||
nop (trcd-1);
|
||||
write (1, 0, 1, 0, 'h4567); // Write Bank 1, Col 0
|
||||
|
||||
activate (2, 0); // Activate Bank 2, Row 0
|
||||
nop (trcd-1);
|
||||
write (2, 0, 1, 0, 'h89AB); // Write Bank 2, Col 0
|
||||
|
||||
activate (3, 0); // Activate Bank 3, Row 0
|
||||
nop (trcd-1);
|
||||
write (3, 0, 1, 0, 'hCDEF); // Write Bank 3, Col 0
|
||||
|
||||
nop (cl - 1 + bl/2 + twtr-1);
|
||||
|
||||
nop (tras);
|
||||
|
||||
// READ SECTION
|
||||
activate (0, 0); // Activate Bank 0, Row 0
|
||||
nop (trrd-1);
|
||||
activate (1, 0); // Activate Bank 1, Row 0
|
||||
nop (trrd-1);
|
||||
activate (2, 0); // Activate Bank 2, Row 0
|
||||
nop (trrd-1);
|
||||
activate (3, 0); // Activate Bank 3, Row 0
|
||||
read (0, 0, 1); // Read Bank 0, Col 0
|
||||
nop (bl/2);
|
||||
read (1, 1, 1); // Read Bank 1, Col 1
|
||||
nop (bl/2);
|
||||
read (2, 2, 1); // Read Bank 2, Col 2
|
||||
nop (bl/2);
|
||||
read (3, 3, 1); // Read Bank 3, Col 3
|
||||
nop (rl + bl/2);
|
||||
|
||||
activate (0, 0); // Activate Bank 0, Row 0
|
||||
nop (trrd-1);
|
||||
activate (1, 0); // Activate Bank 1, Row 0
|
||||
nop (trcd-1);
|
||||
$display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time);
|
||||
read (0, 0, 0); // Read Bank 0, Col 0
|
||||
nop (bl/2-1);
|
||||
read (0, 4, 0); // Read Bank 0, Col 4
|
||||
nop (rl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time);
|
||||
read (0, 0, 0); // Read Bank 0, Col 0
|
||||
nop (bl/2);
|
||||
read (0, 4, 0); // Read Bank 0, Col 4
|
||||
nop (rl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 24: READ Interrupted by READ", $time);
|
||||
read (0, 0, 0); // Read Bank 0, Col 0
|
||||
nop (tccd-1);
|
||||
read (1, 0, 0); // Read Bank 0, Col 0
|
||||
nop (rl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time);
|
||||
read (0, 0, 0); // Read Bank 0, Col 0
|
||||
nop (al + bl/2 + trtp - 2);
|
||||
precharge (0, 0); // Precharge Bank 0
|
||||
nop (trp-1);
|
||||
|
||||
activate (0, 0); // Activate Bank 0, Row 0
|
||||
nop (trcd-1);
|
||||
$display ("%m at time %t: Figure 27: READ to WRITE", $time);
|
||||
read (0, 0, 0); // Read Bank 0, Col 0
|
||||
nop (rl + bl/2 - wl);
|
||||
write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2 + twr + trp-1);
|
||||
|
||||
activate (0, 0); // Activate Bank 0, Row 0
|
||||
nop (trcd-1);
|
||||
$display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time);
|
||||
write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (bl/2);
|
||||
write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 37: Random WRITE Cycles", $time);
|
||||
write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (bl/2-1);
|
||||
write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time);
|
||||
write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (tccd-1);
|
||||
write (1, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 39: WRITE to READ", $time);
|
||||
write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2 + twtr-1);
|
||||
read_verify (0, 0, 0, 0, 'h0123); // Read Bank 0, Col 0
|
||||
nop (rl + bl/2);
|
||||
|
||||
$display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time);
|
||||
write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
|
||||
nop (wl + bl/2 + twr-1);
|
||||
precharge (0, 1); // Precharge all banks
|
||||
nop (trp-1);
|
||||
|
||||
// odt Section
|
||||
$display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time);
|
||||
odt = 1'b1;
|
||||
nop (1);
|
||||
odt = 1'b0;
|
||||
nop (tanpd);
|
||||
|
||||
$display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time);
|
||||
cke = 1'b0;
|
||||
@(negedge ck);
|
||||
odt = 1'b1;
|
||||
@(negedge ck);
|
||||
odt = 1'b0;
|
||||
repeat(tanpd)@(negedge ck);
|
||||
nop (taxpd);
|
||||
|
||||
$display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time);
|
||||
odt = 1'b1;
|
||||
nop (tanpd);
|
||||
power_down (tcke);
|
||||
|
||||
// Self Refresh Section
|
||||
nop (taxpd);
|
||||
odt = 1'b0;
|
||||
nop (3); // taofd
|
||||
self_refresh (tcke);
|
||||
nop (tdllk);
|
||||
nop (tcke);
|
||||
|
||||
test_done;
|
||||
end
|
||||
31
sim/verilog/micron_2048Mb_ddr2/tb.do
Normal file
31
sim/verilog/micron_2048Mb_ddr2/tb.do
Normal file
@ -0,0 +1,31 @@
|
||||
#########################################################################################
|
||||
#
|
||||
# Disclaimer This software code and all associated documentation, comments or other
|
||||
# of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
# warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
# DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
# TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
# OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
# WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
# OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
# FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
# THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
# ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
# OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
# ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
# INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
# WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
# OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
# THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
# DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
# limitation of liability for consequential or incidental damages, the
|
||||
# above limitation may not apply to you.
|
||||
#
|
||||
# Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
#
|
||||
#########################################################################################
|
||||
|
||||
vlog -novopt ddr2.v tb.v
|
||||
vsim -novopt tb
|
||||
add wave -p sdramddr2/*
|
||||
run -all
|
||||
468
sim/verilog/micron_2048Mb_ddr2/tb.v
Normal file
468
sim/verilog/micron_2048Mb_ddr2/tb.v
Normal file
@ -0,0 +1,468 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: tb.v
|
||||
*
|
||||
* Dependencies: ddr2.v, ddr2_parameters.vh
|
||||
*
|
||||
* Description: Micron SDRAM DDR2 (Double Data Rate 2) test bench
|
||||
*
|
||||
* Note: -Set simulator resolution to "ps" accuracy
|
||||
* -Set Debug = 0 to disable $display messages
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// DO NOT CHANGE THE TIMESCALE
|
||||
|
||||
`timescale 1ps / 1ps
|
||||
|
||||
module tb;
|
||||
|
||||
`include "ddr2_parameters.vh"
|
||||
|
||||
// ports
|
||||
reg ck;
|
||||
wire ck_n = ~ck;
|
||||
reg cke;
|
||||
reg cs_n;
|
||||
reg ras_n;
|
||||
reg cas_n;
|
||||
reg we_n;
|
||||
reg [BA_BITS-1:0] ba;
|
||||
reg [ADDR_BITS-1:0] a;
|
||||
wire [DM_BITS-1:0] dm;
|
||||
wire [DQ_BITS-1:0] dq;
|
||||
wire [DQS_BITS-1:0] dqs;
|
||||
wire [DQS_BITS-1:0] dqs_n;
|
||||
wire [DQS_BITS-1:0] rdqs_n;
|
||||
reg odt;
|
||||
|
||||
// mode registers
|
||||
reg [ADDR_BITS-1:0] mode_reg0; //Mode Register
|
||||
reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register
|
||||
wire [2:0] cl = mode_reg0[6:4]; //CAS Latency
|
||||
wire bo = mode_reg0[3]; //Burst Order
|
||||
wire [7:0] bl = (1<<mode_reg0[2:0]); //Burst Length
|
||||
wire rdqs_en = mode_reg1[11]; //RDQS Enable
|
||||
wire dqs_n_en = ~mode_reg1[10]; //dqs# Enable
|
||||
wire [2:0] al = mode_reg1[5:3]; //Additive Latency
|
||||
wire [3:0] rl = al + cl; //Read Latency
|
||||
wire [3:0] wl = al + cl-1'b1; //Write Latency
|
||||
|
||||
// dq transmit
|
||||
reg dq_en;
|
||||
reg [DM_BITS-1:0] dm_out;
|
||||
reg [DQ_BITS-1:0] dq_out;
|
||||
reg dqs_en;
|
||||
reg [DQS_BITS-1:0] dqs_out;
|
||||
assign dm = dq_en ? dm_out : {DM_BITS{1'bz}};
|
||||
assign dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
|
||||
assign dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
|
||||
assign dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
|
||||
|
||||
// dq receive
|
||||
reg [DM_BITS-1:0] dm_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
|
||||
reg [DQ_BITS-1:0] dq_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
|
||||
wire [DQ_BITS-1:0] q0, q1, q2, q3;
|
||||
reg [1:0] burst_cntr;
|
||||
assign rdqs_n = {DQS_BITS{1'bz}};
|
||||
|
||||
// timing definition in tCK units
|
||||
real tck;
|
||||
wire [11:0] taa = ceil(CL_TIME/tck);
|
||||
wire [11:0] tanpd = TANPD;
|
||||
wire [11:0] taond = TAOND;
|
||||
wire [11:0] taofd = ceil(TAOFD);
|
||||
wire [11:0] taxpd = TAXPD;
|
||||
wire [11:0] tccd = TCCD;
|
||||
wire [11:0] tcke = TCKE;
|
||||
wire [11:0] tdllk = TDLLK;
|
||||
wire [11:0] tfaw = ceil(TFAW/tck);
|
||||
wire [11:0] tmod = ceil(TMOD/tck);
|
||||
wire [11:0] tmrd = TMRD;
|
||||
wire [11:0] tras = ceil(TRAS_MIN/tck);
|
||||
wire [11:0] trc = TRC;
|
||||
wire [11:0] trcd = ceil(TRCD/tck);
|
||||
wire [11:0] trfc = ceil(TRFC_MIN/tck);
|
||||
wire [11:0] trp = ceil(TRP/tck);
|
||||
wire [11:0] trrd = ceil(TRRD/tck);
|
||||
wire [11:0] trtp = ceil(TRTP/tck);
|
||||
wire [11:0] twr = ceil(TWR/tck);
|
||||
wire [11:0] twtr = ceil(TWTR/tck);
|
||||
wire [11:0] txard = TXARD;
|
||||
wire [11:0] txards = TXARDS;
|
||||
wire [11:0] txp = TXP;
|
||||
wire [11:0] txsnr = ceil(TXSNR/tck);
|
||||
wire [11:0] txsrd = TXSRD;
|
||||
|
||||
initial begin
|
||||
$timeformat (-9, 1, " ns", 1);
|
||||
`ifdef period
|
||||
tck <= `period;
|
||||
`else
|
||||
tck <= TCK_MIN;
|
||||
`endif
|
||||
ck <= 1'b1;
|
||||
end
|
||||
|
||||
// component instantiation
|
||||
ddr2 sdramddr2 (
|
||||
ck,
|
||||
ck_n,
|
||||
cke,
|
||||
cs_n,
|
||||
ras_n,
|
||||
cas_n,
|
||||
we_n,
|
||||
dm,
|
||||
ba,
|
||||
a,
|
||||
dq,
|
||||
dqs,
|
||||
dqs_n,
|
||||
rdqs_n,
|
||||
odt
|
||||
);
|
||||
|
||||
// clock generator
|
||||
always @(posedge ck) begin
|
||||
ck <= #(tck/2) 1'b0;
|
||||
ck <= #(tck) 1'b1;
|
||||
end
|
||||
|
||||
function integer ceil;
|
||||
input number;
|
||||
real number;
|
||||
if (number > $rtoi(number))
|
||||
ceil = $rtoi(number) + 1;
|
||||
else
|
||||
ceil = number;
|
||||
endfunction
|
||||
|
||||
function integer max;
|
||||
input arg1;
|
||||
input arg2;
|
||||
integer arg1;
|
||||
integer arg2;
|
||||
if (arg1 > arg2)
|
||||
max = arg1;
|
||||
else
|
||||
max = arg2;
|
||||
endfunction
|
||||
|
||||
task power_up;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
odt <= 1'b0;
|
||||
repeat(10) @(negedge ck);
|
||||
cke <= 1'b1;
|
||||
nop (400000/tck+1);
|
||||
end
|
||||
endtask
|
||||
|
||||
task load_mode;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [ADDR_BITS-1:0] addr;
|
||||
begin
|
||||
case (bank)
|
||||
0: mode_reg0 = addr;
|
||||
1: mode_reg1 = addr;
|
||||
endcase
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
a <= addr;
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task refresh;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task precharge;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input ap; //precharge all
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
a <= (ap<<10);
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task activate;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [ROW_BITS-1:0] row;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
ba <= bank;
|
||||
a <= row;
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
//write task supports burst lengths <= 8
|
||||
task write;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
input [8*DM_BITS-1:0] dm;
|
||||
input [8*DQ_BITS-1:0] dq;
|
||||
reg [ADDR_BITS-1:0] atemp [1:0];
|
||||
integer i;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
|
||||
atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
|
||||
a <= atemp[0] | atemp[1] | (ap<<10);
|
||||
for (i=0; i<=bl; i=i+1) begin
|
||||
|
||||
dqs_en <= #(wl*tck + i*tck/2) 1'b1;
|
||||
if (i%2 == 0) begin
|
||||
dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
|
||||
end else begin
|
||||
dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
|
||||
end
|
||||
|
||||
dq_en <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
|
||||
dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
|
||||
dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
|
||||
end
|
||||
dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
|
||||
dq_en <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
// read without data verification
|
||||
task read;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
reg [ADDR_BITS-1:0] atemp [1:0];
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
ba <= bank;
|
||||
atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
|
||||
atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
|
||||
a <= atemp[0] | atemp[1] | (ap<<10);
|
||||
@(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task nop;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task deselect;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b1;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task power_down;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b1;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task self_refresh;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
cs_n <= #(tck) 1'b1;
|
||||
ras_n <= #(tck) 1'b1;
|
||||
cas_n <= #(tck) 1'b1;
|
||||
we_n <= #(tck) 1'b1;
|
||||
repeat(count) @(negedge ck);
|
||||
end
|
||||
endtask
|
||||
|
||||
// read with data verification
|
||||
task read_verify;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
input [8*DM_BITS-1:0] dm; //Expected Data Mask
|
||||
input [8*DQ_BITS-1:0] dq; //Expected Data
|
||||
integer i;
|
||||
begin
|
||||
read (bank, col, ap);
|
||||
for (i=0; i<bl; i=i+1) begin
|
||||
dm_fifo[2*rl + i] = dm >> (i*DM_BITS);
|
||||
dq_fifo[2*rl + i] = dq >> (i*DQ_BITS);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
// receiver(s) for data_verify process
|
||||
dqrx dqrx[DQS_BITS-1:0] (dqs, dq, q0, q1, q2, q3);
|
||||
|
||||
// perform data verification as a result of read_verify task call
|
||||
always @(ck) begin:data_verify
|
||||
integer i;
|
||||
integer j;
|
||||
reg [DQ_BITS-1:0] bit_mask;
|
||||
reg [DM_BITS-1:0] dm_temp;
|
||||
reg [DQ_BITS-1:0] dq_temp;
|
||||
|
||||
for (i = !ck; (i < 2/(2.0 - !ck)); i=i+1) begin
|
||||
if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
|
||||
burst_cntr = 0;
|
||||
end else begin
|
||||
|
||||
dm_temp = dm_fifo[i];
|
||||
for (j=0; j<DQ_BITS; j=j+1) begin
|
||||
bit_mask[j] = !dm_temp[j/8];
|
||||
end
|
||||
|
||||
case (burst_cntr)
|
||||
0: dq_temp = q0;
|
||||
1: dq_temp = q1;
|
||||
2: dq_temp = q2;
|
||||
3: dq_temp = q3;
|
||||
endcase
|
||||
//if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
|
||||
// $display ("%m at time %t: INFO: Successful read data compare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
||||
if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
|
||||
$display ("%m at time %t: ERROR: Read data miscompare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
||||
|
||||
burst_cntr = burst_cntr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (ck) begin
|
||||
if (dm_fifo[2] === {DM_BITS{1'bx}}) begin
|
||||
dqrx[0%DQS_BITS].ptr <= 0; // v2k syntax
|
||||
dqrx[1%DQS_BITS].ptr <= 0; // v2k syntax
|
||||
dqrx[2%DQS_BITS].ptr <= 0; // v2k syntax
|
||||
dqrx[3%DQS_BITS].ptr <= 0; // v2k syntax
|
||||
end
|
||||
end else begin
|
||||
for (i=0; i<=(2*(AL_MAX+CL_MAX)+BL_MAX); i=i+1) begin
|
||||
dm_fifo[i] = dm_fifo[i+2];
|
||||
dq_fifo[i] = dq_fifo[i+2];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// End-of-test triggered in 'subtest.vh'
|
||||
task test_done;
|
||||
begin
|
||||
$display ("%m at time %t: INFO: Simulation is Complete", $time);
|
||||
$stop(0);
|
||||
end
|
||||
endtask
|
||||
|
||||
// Test included from external file
|
||||
`include "subtest.vh"
|
||||
|
||||
endmodule
|
||||
|
||||
module dqrx (
|
||||
dqs, dq, q0, q1, q2, q3
|
||||
);
|
||||
|
||||
`include "ddr2_parameters.vh"
|
||||
|
||||
input dqs;
|
||||
input [DQ_BITS/DQS_BITS-1:0] dq;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q0;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q1;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q2;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q3;
|
||||
|
||||
reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
|
||||
|
||||
assign q0 = q[0];
|
||||
assign q1 = q[1];
|
||||
assign q2 = q[2];
|
||||
assign q3 = q[3];
|
||||
|
||||
reg [1:0] ptr;
|
||||
reg dqs_q;
|
||||
|
||||
always @(dqs) begin
|
||||
if (dqs ^ dqs_q) begin
|
||||
#(TDQSQ + 1);
|
||||
q[ptr] <= dq;
|
||||
ptr <= (ptr + 1)%4;
|
||||
end
|
||||
dqs_q <= dqs;
|
||||
end
|
||||
|
||||
endmodule
|
||||
167
sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh
Normal file
167
sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh
Normal file
@ -0,0 +1,167 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2005 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
|
||||
* Added ROW_BITS & BA_BITS for compatibility w/our system.
|
||||
* Removed part size parameter.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with 1024Mb datasheet rev C (10/02/07)
|
||||
// 04.17.08 - Consolidated 1024Mb and T48M designs; Updated to rev E (03/08)
|
||||
// 12.10.08 - Updated to datasheet rev G (07/08)
|
||||
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg5 // Timing Parameters for -5 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 15.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 16.2; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 10.8; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 18.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 12.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
`else `define sg75 // Timing Parameters for -75 (CL = 3)
|
||||
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 22.5; // tRP ns Precharge command period
|
||||
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 15.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
`endif `endif `endif
|
||||
|
||||
parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
|
||||
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter tRFC = 110.0; // tRFC ns Refresh to Refresh Command interval time
|
||||
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command Note: model adds CL to this value
|
||||
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
parameter tCH_MAX = 0.55; // Clk high level width
|
||||
parameter tCH_MIN = 0.45; // Clk high level width
|
||||
parameter tCL_MAX = 0.55; // Clk low level width
|
||||
parameter tCL_MIN = 0.45; // Clk low level width
|
||||
parameter tCKE = 1.0 ; // Minimum tCKE High/Low time (in tCK's)
|
||||
parameter CL_MAX = 3 ; // Maximum CAS Latency
|
||||
parameter BL_MAX = 16 ;
|
||||
|
||||
|
||||
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
`ifdef x16
|
||||
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
|
||||
`else `define x32
|
||||
`ifdef RP // reduced page mode
|
||||
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else
|
||||
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`endif
|
||||
`endif
|
||||
|
||||
// For use with the Multi Chip Package
|
||||
`ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`else
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`endif
|
||||
|
||||
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_size = 1024; // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
|
||||
|
||||
|
||||
153
sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh
Normal file
153
sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh
Normal file
@ -0,0 +1,153 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2005 - 2006 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK - fixed.
|
||||
* Added ROW_BITS & BA_BITS for compatibility w/our system.
|
||||
* Also changed Col bits from 10 to 9 per spec.
|
||||
* Removed x32 option and part size parameter.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with 128Mb datasheet rev J (11/05)
|
||||
// 04.17.08 - Parameters current with 128Mb Data sheet rev A (04/08)
|
||||
|
||||
// Timing parameters based on Speed Grade
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg5 // Timing Parameters for -5 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 15.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 5.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 16.2; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 5.4; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.50; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 18.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `define sg75 // Timing Parameters for -75 (CL = 3)
|
||||
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 22.5; // tRP ns Precharge command period
|
||||
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`endif `endif `endif
|
||||
|
||||
parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
|
||||
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter tRFC = 80.0; // tRFC ns Refresh to Refresh Command interval time
|
||||
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb Parts)
|
||||
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb Parts)
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
`ifdef x16
|
||||
parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else `define x32
|
||||
parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`endif
|
||||
|
||||
// For use with the Multi Chip Package
|
||||
`ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`else
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`endif
|
||||
|
||||
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_size = 128; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
|
||||
parameter tCH_MAX = 0.55; // Clk high level width
|
||||
parameter tCH_MIN = 0.45; // Clk high level width
|
||||
parameter tCL_MAX = 0.55; // Clk low level width
|
||||
parameter tCL_MIN = 0.45; // Clk low level width
|
||||
parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
|
||||
parameter CL_MAX = 3; // Maximum CAS Latency
|
||||
parameter BL_MAX = 16 ;
|
||||
179
sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh
Normal file
179
sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh
Normal file
@ -0,0 +1,179 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2005 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
|
||||
* Added ROW_BITS & BA_BITS for compatibility w/our system.
|
||||
* Removed part size parameter.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with 2048Mb LPDDR SDRAM
|
||||
// 04.26.10 - Based on Rev 0.7 04/09EN (DDS)
|
||||
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg5 // Timing Parameters for -5 (CL = 3)
|
||||
parameter tAC3_max = 4.8; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 4.8; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 4.8; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 4.8; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 14.4; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 14.4; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
parameter tWR = 14.4; // tWR ns Write recovery time
|
||||
`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 16.2; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 18.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
`else `define sg75 // Timing Parameters for -75 (CL = 3)
|
||||
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 67.5; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 22.5; // tRP ns Precharge command period
|
||||
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 7.50; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
`endif `endif `endif
|
||||
|
||||
parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
|
||||
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
|
||||
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command Note: model adds CL to this value
|
||||
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command
|
||||
parameter tCH_MAX = 0.55; // Clk high level width
|
||||
parameter tCH_MIN = 0.45; // Clk high level width
|
||||
parameter tCL_MAX = 0.55; // Clk low level width
|
||||
parameter tCL_MIN = 0.45; // Clk low level width
|
||||
parameter tCKE = 1.0 ; // Minimum tCKE High/Low time (in tCK's)
|
||||
parameter CL_MAX = 3 ; // Maximum CAS Latency
|
||||
parameter BL_MAX = 16 ;
|
||||
|
||||
|
||||
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
`ifdef x16
|
||||
`ifdef RP
|
||||
parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
|
||||
`else
|
||||
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
|
||||
`endif
|
||||
`else `define x32
|
||||
`ifdef RP // reduced page mode
|
||||
parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else
|
||||
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`endif
|
||||
`endif
|
||||
|
||||
// For use with the Multi Chip Package
|
||||
`ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`else
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`endif
|
||||
|
||||
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_size = 2048; // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
|
||||
|
||||
|
||||
134
sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh
Normal file
134
sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh
Normal file
@ -0,0 +1,134 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2005 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
|
||||
* Added ROW_BITS & BA_BITS for compatibility w/our system.
|
||||
* Also changed x16 Col bits from 8 to 9 per spec.
|
||||
* Removed part size parameter.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with 256Mb datasheet rev E (05/07)
|
||||
// 04.17.08 - Parameters current with 256Mb Data sheet rev H (03/08)
|
||||
|
||||
// Timing parameters based on Speed Grade
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg6 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.50; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 18.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWR = 12.0; // tWR ns Write recovery time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd
|
||||
`else `define sg75 // Timing Parameters for -75 (CL = 3)
|
||||
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 22.5; // tRP ns Precharge command period
|
||||
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd
|
||||
`endif
|
||||
|
||||
parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
|
||||
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter tRFC = 70.0; // tRFC ns Refresh to Refresh Command interval time
|
||||
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
|
||||
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
`ifdef x16
|
||||
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else `define x32
|
||||
`ifdef RP
|
||||
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else
|
||||
parameter ADDR_BITS = 12; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 12; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`endif
|
||||
`endif
|
||||
|
||||
// For use with the Multi Chip Package
|
||||
`ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`else
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`endif
|
||||
|
||||
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_mem_bits = 10; // For fast sim load
|
||||
parameter part_size = 256; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
|
||||
parameter tCH_MAX = 0.55; // Clk high level width
|
||||
parameter tCH_MIN = 0.45; // Clk high level width
|
||||
parameter tCL_MAX = 0.55; // Clk low level width
|
||||
parameter tCL_MIN = 0.45; // Clk low level width
|
||||
parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
|
||||
parameter CL_MAX = 3; // Maximum CAS Latency
|
||||
parameter BL_MAX = 16;
|
||||
|
||||
|
||||
162
sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh
Normal file
162
sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh
Normal file
@ -0,0 +1,162 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2005 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
|
||||
* Added ROW_BITS & BA_BITS for compatibility w/our system.
|
||||
* Removed part size parameter.
|
||||
*
|
||||
****************************************************************************************/
|
||||
|
||||
// Parameters current with T47M datasheet rev M (07/07)
|
||||
// 04.17.08 - Paramters current with 512Mb Data sheet rev C (03/08)
|
||||
// Timing parameters based on Speed Grade
|
||||
|
||||
|
||||
// SYMBOL UNITS DESCRIPTION
|
||||
// ------ ----- -----------
|
||||
`ifdef sg5 // Timing Parameters for -5 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 15.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 59.4; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 16.2; // tRP ns Precharge command period
|
||||
parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 10.8; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
|
||||
parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.50; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 18.0; // tRP ns Precharge command period
|
||||
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`else `define sg75 // Timing Parameters for -75 (CL = 3)
|
||||
parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
|
||||
parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
|
||||
parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
|
||||
parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
|
||||
parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
|
||||
parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
|
||||
parameter tRP = 22.5; // tRP ns Precharge command period
|
||||
parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
|
||||
parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
|
||||
parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
|
||||
`endif `endif `endif
|
||||
|
||||
parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
|
||||
parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
|
||||
parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
|
||||
parameter tRFC = 97.5; // tRFC ns Refresh to Refresh Command interval time
|
||||
parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb Parts)
|
||||
parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb Parts)
|
||||
parameter tWR = 15.0; // tWR ns Write recovery time
|
||||
|
||||
// Size Parameters based on Part Width
|
||||
`ifdef x16
|
||||
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else `define x32
|
||||
`ifdef RP
|
||||
parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`else
|
||||
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
|
||||
parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
|
||||
parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
|
||||
parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
|
||||
parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
|
||||
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
|
||||
parameter BA_BITS = 2; // Bank bits
|
||||
`endif
|
||||
`endif
|
||||
|
||||
// For use with the Multi Chip Package
|
||||
`ifdef DUAL_RANK
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`else
|
||||
parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
|
||||
parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
|
||||
`endif
|
||||
|
||||
parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
|
||||
parameter part_size = 512; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
|
||||
parameter tCH_MAX = 0.55; // Clk high level width
|
||||
parameter tCH_MIN = 0.45; // Clk high level width
|
||||
parameter tCL_MAX = 0.55; // Clk low level width
|
||||
parameter tCL_MIN = 0.45; // Clk low level width
|
||||
parameter tCKE = 1.0; // Minimum tCKE High/Low time (in tCK's)
|
||||
parameter CL_MAX = 3; // Maximum CAS Latency
|
||||
parameter BL_MAX = 16 ;
|
||||
2126
sim/verilog/micron_mobile_ddr/mobile_ddr.v
Normal file
2126
sim/verilog/micron_mobile_ddr/mobile_ddr.v
Normal file
File diff suppressed because it is too large
Load Diff
84
sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v
Normal file
84
sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v
Normal file
@ -0,0 +1,84 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: mobile_ddr_mcp.v
|
||||
*
|
||||
* Dependencies: mobile_ddr.v, mobile_ddr_parameters.vh
|
||||
*
|
||||
* Description: Micron MOBILE DDR SDRAM multi-chip package model
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2008 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
****************************************************************************************/
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module mobile_ddr_mcp (
|
||||
Clk ,
|
||||
Clk_n ,
|
||||
Cke ,
|
||||
Cs_n ,
|
||||
Ras_n ,
|
||||
Cas_n ,
|
||||
We_n ,
|
||||
Addr ,
|
||||
Ba ,
|
||||
Dq ,
|
||||
Dqs ,
|
||||
Dm
|
||||
);
|
||||
|
||||
`include "mobile_ddr_parameters.vh"
|
||||
|
||||
// Declare Ports
|
||||
input Clk ;
|
||||
input Clk_n ;
|
||||
input [CS_BITS - 1 : 0] Cke ;
|
||||
input [CS_BITS - 1 : 0] Cs_n ;
|
||||
input Ras_n ;
|
||||
input Cas_n ;
|
||||
input We_n ;
|
||||
input [ADDR_BITS - 1 : 0] Addr ;
|
||||
input [1 : 0] Ba ;
|
||||
inout [DQ_BITS - 1 : 0] Dq ;
|
||||
inout [DQS_BITS - 1 : 0] Dqs ;
|
||||
input [DM_BITS - 1 : 0] Dm ;
|
||||
|
||||
wire [RANKS - 1 : 0] Cke_mcp = Cke ;
|
||||
wire [RANKS - 1 : 0] Cs_n_mcp = Cs_n ;
|
||||
|
||||
mobile_ddr rank [RANKS - 1:0] (
|
||||
.Clk ( Clk ) ,
|
||||
.Clk_n ( Clk_n ) ,
|
||||
.Cke ( Cke_mcp ) ,
|
||||
.Cs_n ( Cs_n_mcp ) ,
|
||||
.Ras_n ( Ras_n ) ,
|
||||
.Cas_n ( Cas_n ) ,
|
||||
.We_n ( We_n ) ,
|
||||
.Addr ( Addr ) ,
|
||||
.Ba ( Ba ) ,
|
||||
.Dq ( Dq ) ,
|
||||
.Dqs ( Dqs ) ,
|
||||
.Dm ( Dm )
|
||||
);
|
||||
|
||||
endmodule
|
||||
167
sim/verilog/micron_mobile_ddr/readme.txt
Normal file
167
sim/verilog/micron_mobile_ddr/readme.txt
Normal file
@ -0,0 +1,167 @@
|
||||
Disclaimer of Warranty:
|
||||
-----------------------
|
||||
This software code and all associated documentation, comments or other
|
||||
information (collectively "Software") is provided "AS IS" without
|
||||
warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
limitation of liability for consequential or incidental damages, the
|
||||
above limitation may not apply to you.
|
||||
|
||||
Copyright 2008 Micron Technology, Inc. All rights reserved.
|
||||
|
||||
Getting Started:
|
||||
----------------
|
||||
Unzip the included files to a folder.
|
||||
Compile mobile_ddr.v and tb.v using a verilog simulator.
|
||||
Simulate the top level test bench tb.
|
||||
Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
|
||||
|
||||
File Descriptions:
|
||||
------------------
|
||||
mobile_ddr.v --mobile ddr model
|
||||
mobile_ddr_mcp.v --structural wrapper for mobile_ddr multi-chip package model
|
||||
128Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
|
||||
256Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
|
||||
512Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
|
||||
1024Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
|
||||
2048Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
|
||||
readme.txt --This file
|
||||
tb.v --Test bench
|
||||
tb.do --File that compiles and runs the above files
|
||||
|
||||
Defining the Density (part size):
|
||||
-------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between on of the
|
||||
densities supported by the mobile ddr model. Allowable densities are listed in
|
||||
the *.vh file. The density is used to select a set of bank, row, column, and timing
|
||||
parameters for the mobile ddr model. The following are examples of defining
|
||||
the density.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+den512Mb mobile_ddr.v
|
||||
VCS vcs +define+den512Mb mobile_ddr.v
|
||||
NC-Verilog ncverilog +define+den512Mb mobile_ddr.v
|
||||
|
||||
|
||||
Defining the Speed Grade:
|
||||
-------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
multiple speed grades supported by the mobile ddr model. Allowable speed
|
||||
grades are listed in the mobile_ddr_parameters.vh file and begin with the
|
||||
letters "sg". The speed grade is used to select a set of timing
|
||||
parameters for the mobile ddr model. The following are examples of defining
|
||||
the speed grade.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+sg75 mobile_ddr.v
|
||||
VCS vcs +define+sg75 mobile_ddr.v
|
||||
NC-Verilog ncverilog +define+sg75 mobile_ddr.v
|
||||
|
||||
|
||||
Defining the Organization:
|
||||
--------------------------
|
||||
The verilog compiler directive "`define" may be used to choose between
|
||||
multiple organizations supported by the mobile ddr model. Valid
|
||||
organizations include "x16" and "x32", and are listed in the
|
||||
mobile_ddr_parameters.vh file. The organization is used to select the amount
|
||||
of memory and the port sizes of the mobile ddr model. The following are
|
||||
examples of defining the organization.
|
||||
|
||||
vlog +define+x16 mobile_ddr.v
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+x16 mobile_ddr.v
|
||||
VCS vcs +define+x16 mobile_ddr.v
|
||||
NC-Verilog ncverilog +define+x16 mobile_ddr.v
|
||||
|
||||
All combinations of speed grade and organization are considered valid
|
||||
by the mobile ddr model even though a Micron part may not exist for every
|
||||
combination.
|
||||
|
||||
Allocating Memory:
|
||||
------------------
|
||||
An associative array has been implemented to reduce the amount of
|
||||
static memory allocated by the mobile ddr model. The number of
|
||||
entries in the associative array is controlled by the part_mem_bits
|
||||
parameter, and is equal to 2^part_mem_bits. For example, if the
|
||||
part_mem_bits parameter is equal to 10, the associative array will be
|
||||
large enough to store 1024 write data transfers to unique addresses.
|
||||
The following are examples of setting the MEM_BITS parameter to 8.
|
||||
|
||||
simulator command line
|
||||
--------- ------------
|
||||
ModelSim vsim -Gpart_mem_bits=8 mobile_ddr
|
||||
VCS vcs -pvalue+part_mem_bits=8 mobile_ddr.v
|
||||
NC-Verilog ncverilog +defparam+mobile_ddr.part_mem_bits=8 mobile_ddr.v
|
||||
|
||||
It is possible to allocate memory for every address supported by the
|
||||
mobile ddr model by using the verilog compiler directive "`define FULL_MEM".
|
||||
This procedure will improve simulation performance at the expense of
|
||||
system memory. The following are examples of allocating memory for
|
||||
every address.
|
||||
|
||||
Simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+FULL_MEM mobile_ddr.v
|
||||
VCS vcs +define+FULL_MEM mobile_ddr.v
|
||||
NC-Verilog ncverilog +define+FULL_MEM mobile_ddr.v
|
||||
|
||||
|
||||
Reduced Page Mode:
|
||||
------------------
|
||||
Mobile DDR 256Mb, 512Mb, and 1024Mb part may be built with the reduced page size
|
||||
architecture. This part is accessed with the +define+RP designator. RP
|
||||
parts have one extra row bit and one less column bit effectively cutting
|
||||
the page size in half but doubling the number of rows keeping total part
|
||||
size the same.
|
||||
|
||||
Part Size Valid RP Designators
|
||||
--------- --------------------
|
||||
256Mb +define+RP
|
||||
512Mb +define+RP
|
||||
1024Mb +define+RP
|
||||
|
||||
Simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+RP mobile_ddr.v
|
||||
VCS vcs +define+RP mobile_ddr.v
|
||||
NC-Verilog ncverilog +define+RP mobile_ddr.v
|
||||
|
||||
Multi-Chip Package Model:
|
||||
-------------------------
|
||||
The 1024Mb model can be supported in a Multi Chip Package, that allows
|
||||
multiple die models in one structural package. The number of ranks and
|
||||
chip selects of the mcp can be configured by using the `DUAL_RANK define
|
||||
on the simulator call line. The currently supported configurations are
|
||||
listed below:
|
||||
|
||||
Package Configuration Valid MCP Designator
|
||||
--------------------- --------------------
|
||||
2 Chip Selects, 2 Die +define+DUAL_RANK
|
||||
2 Chip Selects, 1 Die (default)
|
||||
|
||||
The single rank mcp is the default. In order to simulate the DUAL_RANK
|
||||
model, the define needs to be added:
|
||||
|
||||
Simulator command line
|
||||
--------- ------------
|
||||
ModelSim vlog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
|
||||
VCS vcs +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
|
||||
NC-Verilog ncverilog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
|
||||
|
||||
32
sim/verilog/micron_mobile_ddr/subtest.vh
Normal file
32
sim/verilog/micron_mobile_ddr/subtest.vh
Normal file
@ -0,0 +1,32 @@
|
||||
initial begin:test
|
||||
//ck <= 1'b0;
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'bz;
|
||||
ras_n <= 1'bz;
|
||||
cas_n <= 1'bz;
|
||||
we_n <= 1'bz;
|
||||
a <= {ADDR_BITS{1'bz}};
|
||||
ba <= {BA_BITS{1'bz}};
|
||||
dq_en <= 1'b0;
|
||||
dqs_en <= 1'b0;
|
||||
power_up;
|
||||
nop (10); // wait 10 clocks intead of 200 us for simulation purposes
|
||||
precharge('h00000000, 1);
|
||||
nop(trp);
|
||||
refresh;
|
||||
nop(trfc);
|
||||
refresh;
|
||||
nop(trfc);
|
||||
load_mode('h0, 'h00000032);
|
||||
nop(tmrd);
|
||||
load_mode('h2, 'h00004000);
|
||||
nop(tmrd);
|
||||
activate('h00000000, 'h00000000);
|
||||
nop(trcd-1);
|
||||
write('h00000000, 'h00000000, 0, { {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}}, { 16'h3000, 16'h2000, 16'h1000, 16'h0});
|
||||
nop(bl/2+twr);
|
||||
read('h00000000, 'h00000000, 1);
|
||||
nop(bl/2-1);
|
||||
nop('h00000014);
|
||||
test_done;
|
||||
end
|
||||
39
sim/verilog/micron_mobile_ddr/tb.do
Normal file
39
sim/verilog/micron_mobile_ddr/tb.do
Normal file
@ -0,0 +1,39 @@
|
||||
#########################################################################################
|
||||
#
|
||||
# Disclaimer This software code and all associated documentation, comments or other
|
||||
# of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
# warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
# DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
# TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
# OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
# WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
# OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
# FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
# THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
# ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
# OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
# ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
# INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
# WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
# OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
# THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
# DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
# limitation of liability for consequential or incidental damages, the
|
||||
# above limitation may not apply to you.
|
||||
#
|
||||
# Copyright 2005 Micron Technology, Inc. All rights reserved.
|
||||
#
|
||||
#########################################################################################
|
||||
|
||||
vlib work
|
||||
vlog +define+den512Mb +define+sg75 +define+x16 mobile_ddr.v tb.v
|
||||
vsim tb
|
||||
add wave -p mobile_ddr/*
|
||||
run -a
|
||||
|
||||
# For Reduced Page Parts run the following and comment out the lines above :
|
||||
|
||||
#vlog +define+den512Mb +define+sg75 +define+x32 mobile_ddr.v tb.v
|
||||
#vsim tb
|
||||
#add wave -p mobile_ddr/*
|
||||
#run -a
|
||||
587
sim/verilog/micron_mobile_ddr/tb.v
Normal file
587
sim/verilog/micron_mobile_ddr/tb.v
Normal file
@ -0,0 +1,587 @@
|
||||
/****************************************************************************************
|
||||
*
|
||||
* File Name: tb.v
|
||||
* Version: 6.00
|
||||
* Model: BUS Functional
|
||||
*
|
||||
* Dependencies: mobile_ddr.v, mobile_ddr_parameters.vh, subtest.vh
|
||||
*
|
||||
* Description: Micron SDRAM DDR (Double Data Rate) test bench
|
||||
*
|
||||
* Note: -Set simulator resolution to "ps" accuracy
|
||||
* -Set Debug = 0 to disable $display messages
|
||||
*
|
||||
* Disclaimer This software code and all associated documentation, comments or other
|
||||
* of Warranty: information (collectively "Software") is provided "AS IS" without
|
||||
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
|
||||
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
|
||||
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
|
||||
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
|
||||
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
|
||||
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
|
||||
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
|
||||
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
|
||||
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
|
||||
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
|
||||
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
|
||||
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
|
||||
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGES. Because some jurisdictions prohibit the exclusion or
|
||||
* limitation of liability for consequential or incidental damages, the
|
||||
* above limitation may not apply to you.
|
||||
*
|
||||
* Copyright 2003 Micron Technology, Inc. All rights reserved.
|
||||
*
|
||||
* Rev Author Date Changes
|
||||
* --- ------ ---------- ---------------------------------------
|
||||
* 4.1 JMK 01/14/2001 -Grouped specify parameters by speed grade
|
||||
* -Fixed mem_sizes parameter
|
||||
* 2.1 SPH 03/19/2002 -Second Release
|
||||
* -Fix tWR and several incompatability
|
||||
* between different simulators
|
||||
* 3.0 TFK 02/18/2003 -Added tDSS and tDSH timing checks.
|
||||
* -Added tDQSH and tDQSL timing checks.
|
||||
* 3.1 CAH 05/28/2003 -update all models to release version 3.1
|
||||
* (no changes to this model)
|
||||
* 3.2 JMK 06/16/2003 -updated all DDR400 models to support CAS Latency 3
|
||||
* 3.3 JMK 09/11/2003 -Added initialization sequence checks.
|
||||
* 4.0 JMK 12/01/2003 -Grouped parameters into "ddr_parameters.v"
|
||||
* -Fixed tWTR check
|
||||
* 4.2 JMK 03/19/2004 -Fixed pulse width checking on dqs
|
||||
* 4.3 JMK 04/27/2004 -Changed bl wire size in tb module
|
||||
* -Changed Dq_buf size to [15:0]
|
||||
* 5.0 JMK 06/16/2004 -Added read to write checking.
|
||||
* -Added read with precharge truncation to write checking.
|
||||
* -Added associative memory array to reduce memory consumption.
|
||||
* -Added checking for required DQS edges during write.
|
||||
* 6.0 DMR 12/03/2004 -new density
|
||||
* 6.01 BAAB 05/18/2006 -assimilating into Minneapolis site organization
|
||||
* 3.11 BAS 10/18/2006 -added read_verify
|
||||
* 3.35 bas 02/28/07 -mobile_ddr.v file uses tAC correctly to calculate strobe/data launch
|
||||
* 3.36 bas 03/05/07 -fixed error messages for different banks interrupting
|
||||
reads/writes w/autoprecharge
|
||||
* 3.37 bas 03/21/07 -added T47M part for 512Mb in parameters file,
|
||||
modified tXP check to measure in tCLK for T47M
|
||||
* 3.60 clk 09/19/07 -fixed dm/dq verification fifo's
|
||||
* 3.60 clk 09/19/07 -fixed dqrx module delay statement
|
||||
* 3.80 clk 10/29/07 - Support for 1024Mb T48M
|
||||
* 4.00 clk 12/30/07 - Fixed Read terminated by precharge testcase
|
||||
* 4.70 clk 03/30/08 - Fixed typo in SRR code
|
||||
* 4.80 clk 04/03/08 - Disable clk checking during initialization
|
||||
* 4.90 clk 04/16/08 - Fixed tInit, added mpc support, updated t35m timing
|
||||
* 5.00 clk 05/14/08 - Fixed back to back auto precharge commands
|
||||
* 5.20 clk 05/21/08 - Fixed read interrupt by pre (BL8), fixed 1024Mb parameter file
|
||||
* 5.30 clk 05/22/08 - Fixed DM signal which cause false tWTR errors
|
||||
05/27/08 - Rewrote write and read pipelins, strobes
|
||||
* 5.40 clk 05/28/08 - Fixed Addressing problem in Burst Order logic
|
||||
* 5.50 clk 07/25/08 - Added T36N part type
|
||||
* 5.60 clk 09/05/08 - Fixed tXP in 256Mb part type
|
||||
* 5.70 clk 09/17/08 - Fixed burst term check for write w/ all DM active
|
||||
* 5.80 clk 11/18/08 - Fixed internally latched dq & mask widths
|
||||
* 5.90 clk 12/10/08 - Updated T36N parameters to latest datasheet
|
||||
* 6.00 clk 03/05/09 - Fixed DQS problem w/ CL = 2
|
||||
****************************************************************************************/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module tb;
|
||||
|
||||
`ifdef den128Mb
|
||||
`include "128Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den256Mb
|
||||
`include "256Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den512Mb
|
||||
`include "512Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den1024Mb
|
||||
`include "1024Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den2048Mb
|
||||
`include "2048Mb_mobile_ddr_parameters.vh"
|
||||
`else
|
||||
// NOTE: Intentionally cause a compile fail here to force the users
|
||||
// to select the correct component density before continuing
|
||||
ERROR: You must specify component density with +define+den____Mb.
|
||||
`endif
|
||||
|
||||
reg ck_tb ;
|
||||
reg ck_enable = 1'b1 ;
|
||||
// ports
|
||||
wire ck;
|
||||
wire ck_n = ~ck;
|
||||
reg cke = 1'b0;
|
||||
reg cs_n;
|
||||
reg ras_n;
|
||||
reg cas_n;
|
||||
reg we_n;
|
||||
reg [BA_BITS-1:0] ba;
|
||||
reg [ADDR_BITS-1:0] a;
|
||||
wire [DM_BITS-1:0] dm;
|
||||
wire [DQ_BITS-1:0] dq;
|
||||
wire [DQS_BITS-1:0] dqs;
|
||||
|
||||
// mode registers
|
||||
reg [ADDR_BITS-1:0] mode_reg0; //Mode Register
|
||||
reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register
|
||||
wire [2:0] cl = mode_reg0[6:4]; //CAS Latency
|
||||
wire bo = mode_reg0[3]; //Burst Order
|
||||
wire [7:0] bl = (1<<mode_reg0[2:0]); //Burst Length
|
||||
wire wl = 1; //Write Latency
|
||||
|
||||
// dq transmit
|
||||
reg dq_en;
|
||||
reg [DM_BITS-1:0] dm_out;
|
||||
reg [DQ_BITS-1:0] dq_out;
|
||||
reg dqs_en;
|
||||
reg [DQS_BITS-1:0] dqs_out;
|
||||
assign dm = dq_en ? dm_out : {DM_BITS{1'b0}};
|
||||
assign dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
|
||||
assign dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
|
||||
|
||||
// dq receive
|
||||
reg [DM_BITS-1:0] dm_fifo [2*CL_MAX+16:0];
|
||||
reg [DQ_BITS-1:0] dq_fifo [2*CL_MAX+16:0];
|
||||
wire [DQ_BITS-1:0] q0, q1, q2, q3;
|
||||
reg ptr_rst_n;
|
||||
reg [1:0] burst_cntr;
|
||||
|
||||
// timing definition in tCK units
|
||||
real tck;
|
||||
wire [11:0] trc = tRC;
|
||||
wire [11:0] trrd = ceil(tRRD/tck);
|
||||
wire [11:0] trcd = ceil(tRCD/tck);
|
||||
wire [11:0] tras = ceil(tRAS/tck);
|
||||
wire [11:0] twr = ceil(tWR/tck);
|
||||
wire [11:0] trp = ceil(tRP/tck);
|
||||
wire [11:0] tmrd = tMRD;
|
||||
wire [11:0] trfc = ceil(tRFC/tck);
|
||||
wire [11:0] tsrr = ceil(tSRR);
|
||||
wire [11:0] tsrc = ceil(tSRC);
|
||||
wire [11:0] tdqsq = tDQSQ;
|
||||
wire [11:0] twtr = tWTR;
|
||||
|
||||
initial begin
|
||||
$timeformat (-9, 1, " ns", 1);
|
||||
`ifdef period
|
||||
tck <= `period;
|
||||
`else
|
||||
tck <= tCK;
|
||||
`endif
|
||||
ck_tb <= 1'b1;
|
||||
dq_en <= 1'b0;
|
||||
dqs_en <= 1'b0;
|
||||
end
|
||||
|
||||
// component instantiation
|
||||
mobile_ddr mobile_ddr (
|
||||
.Clk ( ck ) ,
|
||||
.Clk_n ( ck_n ) ,
|
||||
.Cke ( cke ) ,
|
||||
.Cs_n ( cs_n ) ,
|
||||
.Ras_n ( ras_n ) ,
|
||||
.Cas_n ( cas_n ) ,
|
||||
.We_n ( we_n ) ,
|
||||
.Addr ( a ) ,
|
||||
.Ba ( ba ) ,
|
||||
.Dq ( dq ) ,
|
||||
.Dqs ( dqs ) ,
|
||||
.Dm ( dm )
|
||||
);
|
||||
|
||||
// clock generator
|
||||
assign ck = ck_enable & ck_tb ;
|
||||
always @(posedge ck_tb) begin
|
||||
ck_tb <= #(tck/2) 1'b0;
|
||||
ck_tb <= #(tck) 1'b1;
|
||||
end
|
||||
|
||||
function integer ceil;
|
||||
input number;
|
||||
real number;
|
||||
if (number > $rtoi(number))
|
||||
ceil = $rtoi(number) + 1;
|
||||
else
|
||||
ceil = number;
|
||||
endfunction
|
||||
|
||||
function integer max;
|
||||
input arg1;
|
||||
input arg2;
|
||||
integer arg1;
|
||||
integer arg2;
|
||||
if (arg1 > arg2)
|
||||
max = arg1;
|
||||
else
|
||||
max = arg2;
|
||||
endfunction
|
||||
|
||||
function [8*DQ_BITS-1:0] burst_order;
|
||||
input [8-1:0] col;
|
||||
input [8*DQ_BITS-1:0] dq;
|
||||
reg [3:0] i;
|
||||
reg [2:0] j;
|
||||
integer k;
|
||||
begin
|
||||
burst_order = dq;
|
||||
for (i=0; i<bl; i=i+1) begin
|
||||
j = ((col%bl) ^ i);
|
||||
if (!bo)
|
||||
j[1:0] = (col + i);
|
||||
for (k=0; k<DQ_BITS; k=k+1) begin
|
||||
burst_order[i*DQ_BITS + k] = dq[j*DQ_BITS + k];
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
task power_up;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b1;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
ba <= {BA_BITS{1'b0}};
|
||||
a <= {ADDR_BITS{1'b0}};
|
||||
repeat(10) @(negedge ck_tb);
|
||||
@ (negedge ck_tb) cke <= 1'b1;
|
||||
$display ("%m at time %t TB: A 200 us delay is required after cke is brought high.", $time);
|
||||
end
|
||||
endtask
|
||||
|
||||
task stop_clock_enter ;
|
||||
begin
|
||||
@ (negedge ck_tb);
|
||||
ck_enable = 1'b0 ;
|
||||
end
|
||||
endtask
|
||||
|
||||
task stop_clock_exit ;
|
||||
begin
|
||||
@ (negedge ck_tb);
|
||||
ck_enable = 1'b1 ;
|
||||
end
|
||||
endtask
|
||||
|
||||
task load_mode;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [ROW_BITS-1:0] row;
|
||||
begin
|
||||
case (bank)
|
||||
0: mode_reg0 = row;
|
||||
1: mode_reg1 = row;
|
||||
endcase
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
a <= row;
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task refresh;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task precharge;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input ap; //precharge all
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
a <= (ap<<10);
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task activate;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [ROW_BITS-1:0] row;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
ba <= bank;
|
||||
a <= row;
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
//write task supports burst lengths <= 8
|
||||
task write;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
input [16*DM_BITS-1:0] dm;
|
||||
input [16*DQ_BITS-1:0] dq;
|
||||
reg [ADDR_BITS-1:0] atemp [1:0];
|
||||
integer i;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b0;
|
||||
ba <= bank;
|
||||
atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
|
||||
atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
|
||||
a <= atemp[0] | atemp[1] | (ap<<10);
|
||||
for (i=0; i<=bl; i=i+1) begin
|
||||
dqs_en <= #(wl*tck + i*tck/2) 1'b1;
|
||||
if (i%2 == 0) begin
|
||||
dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
|
||||
end else begin
|
||||
dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
|
||||
end
|
||||
|
||||
dq_en <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
|
||||
dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
|
||||
dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
|
||||
end
|
||||
dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
|
||||
dq_en <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
// read without data verification
|
||||
task read;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
reg [ADDR_BITS-1:0] atemp [1:0];
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
ba <= bank;
|
||||
atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
|
||||
atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
|
||||
a <= atemp[0] | atemp[1] | (ap<<10);
|
||||
@(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task burst_term;
|
||||
integer i;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b0;
|
||||
@(negedge ck_tb);
|
||||
for (i=0; i<bl; i=i+1) begin
|
||||
dm_fifo[2*cl + i] <= {DM_BITS{1'bx}};
|
||||
dq_fifo[2*cl + i] <= {DQ_BITS{1'bx}};
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task nop;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task deselect;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b1;
|
||||
cs_n <= 1'b1;
|
||||
// ras_n <= 1'b1;
|
||||
// cas_n <= 1'b1;
|
||||
// we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task power_down;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b1;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task deep_power_down;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b1;
|
||||
cas_n <= 1'b1;
|
||||
we_n <= 1'b0;
|
||||
repeat(count) @(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
task self_refresh;
|
||||
input [31:0] count;
|
||||
begin
|
||||
cke <= 1'b0;
|
||||
cs_n <= 1'b0;
|
||||
ras_n <= 1'b0;
|
||||
cas_n <= 1'b0;
|
||||
we_n <= 1'b1;
|
||||
repeat(count) @(negedge ck_tb);
|
||||
end
|
||||
endtask
|
||||
|
||||
// read with data verification
|
||||
task read_verify;
|
||||
input [BA_BITS-1:0] bank;
|
||||
input [COL_BITS-1:0] col;
|
||||
input ap; //Auto Precharge
|
||||
input [16*DM_BITS-1:0] dm; //Expected Data Mask
|
||||
input [16*DQ_BITS-1:0] dq; //Expected Data
|
||||
integer i;
|
||||
begin
|
||||
read (bank, col, ap);
|
||||
for (i=0; i<bl; i=i+1) begin
|
||||
dm_fifo[2*cl + i] <= dm>>(i*DM_BITS);
|
||||
dq_fifo[2*cl + i] <= dq>>(i*DQ_BITS);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
// receiver(s) for data_verify process
|
||||
dqrx dqrx[DQS_BITS-1:0] (ptr_rst_n, dqs, dq, q0, q1, q2, q3);
|
||||
|
||||
// perform data verification as a result of read_verify task call
|
||||
reg [DQ_BITS-1:0] bit_mask;
|
||||
reg [DM_BITS-1:0] dm_temp;
|
||||
reg [DQ_BITS-1:0] dq_temp;
|
||||
always @(ck) begin:data_verify
|
||||
integer i;
|
||||
integer j;
|
||||
|
||||
for (i=!ck; (i<2/(2.0 - !ck)); i=i+1) begin
|
||||
if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
|
||||
burst_cntr = 0;
|
||||
end else begin
|
||||
|
||||
dm_temp = dm_fifo[i];
|
||||
for (j=0; j<DQ_BITS; j=j+1) begin
|
||||
bit_mask[j] = !dm_temp[j/(DQ_BITS/DM_BITS)];
|
||||
end
|
||||
|
||||
case (burst_cntr)
|
||||
0: dq_temp = q0;
|
||||
1: dq_temp = q1;
|
||||
2: dq_temp = q2;
|
||||
3: dq_temp = q3;
|
||||
endcase
|
||||
//if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
|
||||
// $display ("%m at time %t: INFO: Successful read data compare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
||||
if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
|
||||
$display ("%m at time %t: ERROR: Read data miscompare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
||||
|
||||
burst_cntr = burst_cntr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (ck_tb) begin
|
||||
ptr_rst_n <= (dm_fifo[4] !== {DM_BITS{1'bx}});
|
||||
end else begin
|
||||
//ptr_rst_n <= ptr_rst_n & (dm_fifo[6] !== {DM_BITS{1'bx}});
|
||||
for (i=0; i<=2*CL_MAX+16; i=i+1) begin
|
||||
dm_fifo[i] = dm_fifo[i+2];
|
||||
dq_fifo[i] = dq_fifo[i+2];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// End-of-test triggered in 'subtest.vh'
|
||||
task test_done;
|
||||
begin
|
||||
$display ("%m at time %t: INFO: Simulation is Complete", $time);
|
||||
$stop(0);
|
||||
end
|
||||
endtask
|
||||
|
||||
// Test included from external file
|
||||
`include "subtest.vh"
|
||||
|
||||
endmodule
|
||||
|
||||
module dqrx (
|
||||
ptr_rst_n, dqs, dq, q0, q1, q2, q3
|
||||
);
|
||||
|
||||
`ifdef den128Mb
|
||||
`include "128Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den256Mb
|
||||
`include "256Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den512Mb
|
||||
`include "512Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den1024Mb
|
||||
`include "1024Mb_mobile_ddr_parameters.vh"
|
||||
`elsif den2048Mb
|
||||
`include "2048Mb_mobile_ddr_parameters.vh"
|
||||
`else
|
||||
// NOTE: Intentionally cause a compile fail here to force the users
|
||||
// to select the correct component density before continuing
|
||||
ERROR: You must specify component density with +define+den____Mb.
|
||||
`endif
|
||||
|
||||
input ptr_rst_n;
|
||||
input dqs;
|
||||
input [DQ_BITS/DQS_BITS-1:0] dq;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q0;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q1;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q2;
|
||||
output [DQ_BITS/DQS_BITS-1:0] q3;
|
||||
|
||||
reg [1:0] ptr;
|
||||
reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
|
||||
|
||||
reg ptr_rst_dly_n;
|
||||
always @(posedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_min + tDQSQ) ptr_rst_n;
|
||||
always @(negedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_max + tDQSQ + 0.002) ptr_rst_n;
|
||||
|
||||
reg dqs_dly;
|
||||
always @(dqs) dqs_dly <= #(tDQSQ + 0.001) dqs;
|
||||
|
||||
always @(negedge ptr_rst_dly_n or posedge dqs_dly or negedge dqs_dly) begin
|
||||
if (!ptr_rst_dly_n) begin
|
||||
ptr <= 0;
|
||||
end else if (dqs_dly || ptr) begin
|
||||
q[ptr] <= dq;
|
||||
ptr <= ptr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
assign q0 = q[0];
|
||||
assign q1 = q[1];
|
||||
assign q2 = q[2];
|
||||
assign q3 = q[3];
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user