Commit Graph
29 Commits
Author SHA1 Message Date
SDD 1c0a9b2b64 docs: Ghidra decompiler unreliable for this ROM (~85% of sampled functions flagged); SLEIGH instruction coverage incomplete 2026-10-16 11:08:46 +03:00
SDD 77c918f15c docs: next level-1 gate is HOST PORT (window 0x6400000); evidence and approach recorded 2026-10-16 11:01:39 +03:00
SDD 49378827e8 fix(tms34010): drop addr32 &0xFFFFF, fix ADDI imm; rebuild .sla, repair program, validate 31691 sites 2026-10-16 10:59:40 +03:00
SDD 5000b8bc07 harness: level-1 VIDEO MEMORY test passes (video RAM mapped + REFCNT advances); next gate is HOST PORT 2026-10-16 10:57:06 +03:00
SDD 5ef8712960 harness: identify the level-1 video-memory test that raises code 0x100 (VIDEO MEMORY-22)
The dispatch status is 0x100 (printed as '22' in the message). A driver-side
transparent low-RAM write log (VT1200_LOWLOG) shows the slot at bit 0x16F0 is
written by the store at 3FDF9090 from a13(0x10), which L3FA7C050 sets to the
literal 0x100 when the memory test L3F2018B0 returns non-zero. L3F2018B0 is the
level-1 video-memory test (base bit 0x04000000, count 0x20000). Its failing
checks: the 16-bit walking-bit read-back at 0x04000000 (baseline, unmapped) and,
with video RAM mapped, the REFCNT (0xC00001F0) 'must change' check.
2026-10-16 10:55:44 +03:00
SDD f46b4a44a4 docs: root-cause Ghidra TMS34010 CALLA bug to addr32 & 0xFFFFF (empty call graph) 2026-10-16 10:48:02 +03:00
SDD 3a1d10e9bb docs: consolidate level-1 investigation state; stack walk reaches the framework not the test 2026-10-16 10:40:24 +03:00
SDD 8a00cef556 docs: Ghidra CALLA targets do not resolve (empty call graph); smart34010 is authoritative for call targets 2026-10-16 10:38:16 +03:00
SDD 9a2363a68f docs: level-1 errors are status-code dispatched; withdraw the unsound failing-address claim 2026-10-16 10:36:27 +03:00
SDD cca49dc27d harness: VRAM transparent logging proxy; video RAM test is a walking-bit test and still fails 2026-10-16 10:33:00 +03:00
SDD 07997022ad docs: the video RAM test draws characters then verifies; mapping alone cannot satisfy it 2026-10-16 10:30:52 +03:00
SDD 52744cbd03 harness: correct video memory to bit 0x04000000; log the failing address; level 1 still fails 2026-10-16 10:27:32 +03:00
SDD f49f9984bb harness: close the instrument disagreement -- catch-all trustworthy, off = bit>>4
Closed cross-check (single run): the catch-all and VT1200_CAL proxies are
directly comparable (both base 0) and resolve identically; last-wins holds
for same- and mismatched-width overlaps. The apparent conflict was a units
error: a .rw(FUNC(offs_t)) handler receives (bitaddr-base)>>4 (tms34010
Width=1, AddrShift=3), so the catch-all logs bitaddr>>4. Its 0x400000..0x40D7FF
is bit 0x04000000..0x040D7FF0 (bytes 0x800000..0x81AFFE), outside the declared
4 MiB RAM -- genuinely unmapped. The old 0x00400000 proxy was 16x too low.
Catch-all reproduces the committed log byte-for-byte and does not perturb
coverage (56 / PC=3F208950 with and without). Regression holds: PC=3FDCE400
samples=199. Report: harness/mame/XCROSS_REPORT.md
2026-10-16 10:25:17 +03:00
SDD 99ca146fe3 docs: address units resolved from MAME source (map is in BITS; bytes = bit>>3) + two corrections 2026-10-16 10:18:01 +03:00
SDD 93fb92d807 docs: record the instrument disagreement precisely; block video work on a closed cross-check 2026-10-16 10:11:59 +03:00
SDD b2e0448001 harness: map-precedence calibration (last-wins proven) + layered address probes 2026-10-16 10:11:47 +03:00
SDD 7030f2068d harness: record headless-watchpoint void + the unresolved address-unit blocker, with a calibration plan 2026-10-16 10:07:38 +03:00
SDD ccd03b8879 harness: capture the firmware console; it reports LEVEL1/2 VIDEO MEMORY error 22 and restarts 2026-10-16 10:03:51 +03:00
SDD fe978dee18 harness: locate video memory at 0x00400000 via an unmapped-access catch-all 2026-10-16 09:45:28 +03:00
SDD 170d07f0a2 docs: plan-1 outcome, rulings, and triaged findings (durable record before workspace cleanup) 2026-10-16 02:15:51 +03:00
SDD 66784de1aa docs: memory-space map from the spike; commit the plan amendment; ignore harness logs 2026-10-16 02:15:13 +03:00
SDD e23dadcfd4 harness: correct board-model docs (four windows, real callback trap, guessed DMA timing) 2026-10-16 02:15:05 +03:00
SDD 8e18d81cef harness: paste verbatim sweep/differential/INTENB evidence into BRINGUP_LOG 2026-10-16 02:07:05 +03:00
SDD 2d7747a20d harness: configurable board model busy timings + findings 2026-10-16 01:59:57 +03:00
SDD a2f19b2d29 harness: model the 0x5800000/0x5900000 DMA command/data pair 2026-10-16 01:54:37 +03:00
SDD 66fe15367b harness: per-window busy state machines for the big windows 2026-10-16 01:52:06 +03:00
SDD db2caa5558 harness: make board switch knob unambiguous and non-silent 2026-10-16 01:50:03 +03:00
SDD 43f69738f4 harness: extract VT1200 board register model, unit-tested 2026-10-16 01:45:01 +03:00
SDD acb92d3e44 checkpoint: VT1200 reverse-engineering workspace before board-model work 2026-10-16 01:37:50 +03:00