arti/vt1200
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Code Wiki Activity

Commit Graph

  • 1ca4817745 harness: model DUART2 by default (drop the VT1200_DUART2 gate) SDD 2026-10-16 13:59:09 +03:00
  • 6ce84b86f2 run.sh: skip mode also models DUART2 -- required for the OS (phantom ISR read at 0x06200005); reaches the Terminal Manager SDD 2026-10-16 13:40:21 +03:00
  • c06cf7096b harness: skip run is STUCK at the X11 weave -- wall is unmodelled DUART2 (phantom ISR read at 0x06200005); add multi-timestamp dumps + console string resolver SDD 2026-10-16 13:39:37 +03:00
  • 855f3e85e9 docs: the OS DOES paint -- skip run boots to a running X11 server (root weave confirmed in a frame dump); correct the claim I wrote SDD 2026-10-16 13:26:27 +03:00
  • b99b7de62e harness: add run.sh launcher (faithful/skip/pie/headless modes, verified end to end) SDD 2026-10-16 13:21:51 +03:00
  • c3faa7729d docs: correct stale README - DUARTs/VRAM are modelled, fix memory_access template args, add gate list and new baseline SDD 2026-10-16 13:19:25 +03:00
  • 5abf4f33be harness: promote the working VT1200 config to the default; retire settled env gates SDD 2026-10-16 13:18:14 +03:00
  • 9d912ae084 harness: l1patch.lua -- runtime level-1 host-port patch + test-map probe SDD 2026-10-16 13:09:45 +03:00
  • 55cf122edd docs: correct the stale 256 KiB RAM claim in BRINGUP_LOG SDD 2026-10-16 13:09:37 +03:00
  • db535c2adc harness: explicit monochrome palette (pen 0 black, pen 1 white) SDD 2026-10-16 13:02:50 +03:00
  • ac60ad2f89 docs: plan to retire the settled VT1200_* env gates (promote working config to default, delete finished experiments) SDD 2026-10-16 13:02:20 +03:00
  • 6cbb362bb9 harness: VT1200_DUART1_INT2 -- route DUART1's IRQ to INT2 (A/B knob) SDD 2026-10-16 13:01:40 +03:00
  • c19c603d77 harness: VT1200_DUART_IP3 -- drive DUART1 IP3 high to take the OS cold-start gate SDD 2026-10-16 12:55:36 +03:00
  • c69d2c295f reference: level-1 host-port test — can it be skipped? (analysis, no skip) SDD 2026-10-16 12:42:35 +03:00
  • 571850e564 harness: render the TMS34010 active scanlines from video RAM SDD 2026-10-16 12:42:33 +03:00
  • bcbd7924af docs: last authorised timing change tested (idle-path transmit start) -- real deviation, not the cause; reverted SDD 2026-10-16 12:26:01 +03:00
  • 88d006730a docs: identify the writers of +0x3c0/+0x3d0 (the DUART ISR) and what L3FA71BC0 checks SDD 2026-10-16 12:23:14 +03:00
  • d7725faa1e docs: enumerate the three remaining failing checks; record the transmit-start citation SDD 2026-10-16 12:21:16 +03:00
  • 03e6a88b22 docs: establish causally what raises HOST PORT - 15; resolve the sub-test polarity; rule out the loopback-clock deviation as the cause SDD 2026-10-16 12:18:30 +03:00
  • 70e2486d57 mc68681: revert the TxRDY edit (REFUTED by the fitted part's datasheet); keep the overrun edit SDD 2026-10-16 12:15:47 +03:00
  • 72a96862c7 docs: causality audit -- the host-port failure is pre-existing, not caused by the two MAME edits SDD 2026-10-16 12:13:39 +03:00
  • 031d30da67 reference: DUART datasheet verification of the two mc68681 edits (claim 1 refuted) SDD 2026-10-16 12:13:07 +03:00
  • 9902722165 harness: wire DUART IRQ to the TMS34010 (host-port test transmit); fix two DUART timing deviations SDD 2026-10-16 12:07:27 +03:00
  • 3fd1e13b2e docs: keyboard/mouse protocol spec — LK401 (LK201 protocol) + VSXXX-AA mouse, sources, MAME lk201 device SDD 2026-10-16 11:38:52 +03:00
  • 23e508f075 docs: level-1 test sequence, port tests vs device tests (keyboard/mouse device models needed for tests 26/27) SDD 2026-10-16 11:31:56 +03:00
  • b38da304c3 docs: correct DUART report - host port test is local loopback (service guide), wiring verified sound, missing THRA write is the real bug SDD 2026-10-16 11:27:11 +03:00
  • 2fd9286c1a harness: wire MAME SCN2681 at the DUART windows (host-port investigation) SDD 2026-10-16 11:22:56 +03:00
  • 1c0a9b2b64 docs: Ghidra decompiler unreliable for this ROM (~85% of sampled functions flagged); SLEIGH instruction coverage incomplete SDD 2026-10-16 11:08:46 +03:00
  • 77c918f15c docs: next level-1 gate is HOST PORT (window 0x6400000); evidence and approach recorded SDD 2026-10-16 11:01:39 +03:00
  • 49378827e8 fix(tms34010): drop addr32 &0xFFFFF, fix ADDI imm; rebuild .sla, repair program, validate 31691 sites SDD 2026-10-16 10:59:40 +03:00
  • 5000b8bc07 harness: level-1 VIDEO MEMORY test passes (video RAM mapped + REFCNT advances); next gate is HOST PORT SDD 2026-10-16 10:57:06 +03:00
  • 5ef8712960 harness: identify the level-1 video-memory test that raises code 0x100 (VIDEO MEMORY-22) SDD 2026-10-16 10:55:44 +03:00
  • f46b4a44a4 docs: root-cause Ghidra TMS34010 CALLA bug to addr32 & 0xFFFFF (empty call graph) SDD 2026-10-16 10:48:02 +03:00
  • 3a1d10e9bb docs: consolidate level-1 investigation state; stack walk reaches the framework not the test SDD 2026-10-16 10:40:24 +03:00
  • 8a00cef556 docs: Ghidra CALLA targets do not resolve (empty call graph); smart34010 is authoritative for call targets SDD 2026-10-16 10:38:16 +03:00
  • 9a2363a68f docs: level-1 errors are status-code dispatched; withdraw the unsound failing-address claim SDD 2026-10-16 10:36:27 +03:00
  • cca49dc27d harness: VRAM transparent logging proxy; video RAM test is a walking-bit test and still fails SDD 2026-10-16 10:33:00 +03:00
  • 07997022ad docs: the video RAM test draws characters then verifies; mapping alone cannot satisfy it SDD 2026-10-16 10:30:52 +03:00
  • 52744cbd03 harness: correct video memory to bit 0x04000000; log the failing address; level 1 still fails SDD 2026-10-16 10:27:32 +03:00
  • f49f9984bb harness: close the instrument disagreement -- catch-all trustworthy, off = bit>>4 SDD 2026-10-16 10:25:17 +03:00
  • 99ca146fe3 docs: address units resolved from MAME source (map is in BITS; bytes = bit>>3) + two corrections SDD 2026-10-16 10:18:01 +03:00
  • 93fb92d807 docs: record the instrument disagreement precisely; block video work on a closed cross-check SDD 2026-10-16 10:11:59 +03:00
  • b2e0448001 harness: map-precedence calibration (last-wins proven) + layered address probes SDD 2026-10-16 10:11:47 +03:00
  • 7030f2068d harness: record headless-watchpoint void + the unresolved address-unit blocker, with a calibration plan SDD 2026-10-16 10:07:38 +03:00
  • ccd03b8879 harness: capture the firmware console; it reports LEVEL1/2 VIDEO MEMORY error 22 and restarts SDD 2026-10-16 10:03:51 +03:00
  • fe978dee18 harness: locate video memory at 0x00400000 via an unmapped-access catch-all SDD 2026-10-16 09:45:28 +03:00
  • 170d07f0a2 docs: plan-1 outcome, rulings, and triaged findings (durable record before workspace cleanup) SDD 2026-10-16 02:15:51 +03:00
  • 66784de1aa docs: memory-space map from the spike; commit the plan amendment; ignore harness logs SDD 2026-10-16 02:15:13 +03:00
  • e23dadcfd4 harness: correct board-model docs (four windows, real callback trap, guessed DMA timing) SDD 2026-10-16 02:15:05 +03:00
  • 8e18d81cef harness: paste verbatim sweep/differential/INTENB evidence into BRINGUP_LOG SDD 2026-10-16 02:07:05 +03:00
  • 2d7747a20d harness: configurable board model busy timings + findings SDD 2026-10-16 01:59:57 +03:00
  • a2f19b2d29 harness: model the 0x5800000/0x5900000 DMA command/data pair SDD 2026-10-16 01:54:37 +03:00
  • 66fe15367b harness: per-window busy state machines for the big windows SDD 2026-10-16 01:52:06 +03:00
  • db2caa5558 harness: make board switch knob unambiguous and non-silent SDD 2026-10-16 01:50:03 +03:00
  • 43f69738f4 harness: extract VT1200 board register model, unit-tested SDD 2026-10-16 01:45:01 +03:00
  • acb92d3e44 checkpoint: VT1200 reverse-engineering workspace before board-model work SDD 2026-10-16 01:37:50 +03:00