opencode.siil.arti.ee

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Joined on 2026-11-11

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opencode.siil.art… opened issue arti/vt1200#1 2026-11-12 07:22:34 +02:00

docs: XMapWindow is 0x3FD64F60; 0x3FD645B0 is XRaiseWindow (ConfigureWindow opcode 12)

opencode.siil.art… pushed to m3 at opencode.siil.art…/llvm-tms34010 2026-11-11 22:30:42 +02:00

73c85350a4 tms34010: correct M3 encodings and narrow-load docs

opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 22:30:42 +02:00

24f877362b docs: finalize M3 limitations and M4 prerequisites

opencode.siil.art… pushed to m3 at opencode.siil.art…/llvm-tms34010 2026-11-11 22:07:00 +02:00

1968ccd39b docs: correct M3 milestone wording

opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 22:07:00 +02:00

2681be26c0 tests: anchor the M3 Xlib displacement checks

opencode.siil.art… pushed to m3 at opencode.siil.art…/llvm-tms34010 2026-11-11 21:56:22 +02:00

8d088c40df docs: M3 branches and Xlib window

afb4ad2eef tms34010: allow misaligned loads/stores

05762fceb8 tms34010: add integer comparisons, branches and ALU ops

bbc591b77c tms34010: add JAcc branches and GSPA-safe block labels

Compare 4 commits »

opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 21:56:22 +02:00

ed58040fbd docs: M3 control flow and first Xlib window

09db9e22e9 tests: M3 branches and first Xlib window in MAME

b34016a9f3 docs: correct M3 ROM bit displacements and unaligned-load carry-forward

2187f59b20 tests: M3 Xlib Display/Screen layout

Compare 4 commits »

opencode.siil.art… pushed to m3 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:54:03 +02:00

opencode.siil.art… created branch m3 in opencode.siil.art…/llvm-tms34010 2026-11-11 19:54:03 +02:00

opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:54:02 +02:00

d1ba1e4d86 docs: M3 control flow and first Xlib window plan

opencode.siil.art… created branch m3 in opencode.siil.art…/tms-c-compiler 2026-11-11 19:54:02 +02:00

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:36:20 +02:00

39512c272d tms34010: fix M2 data widths and FS0 after calls

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:36:20 +02:00

2d4919db36 docs: finalize M2 ABI and tail-call notes

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:15:48 +02:00

d7317305b9 tms34010: accept returned on call arguments and correct M2 docs

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:15:48 +02:00

f1a604d70e docs: correct M2 branch and epilogue guidance

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:05:34 +02:00

3a188b35fb docs: M2 TI ABI, ROM strlen and golden ABI check

fa00b8740b docs: finish the M2 loader and returned reconciliation

b614e70851 docs: reconcile M2 plan with JAUC, returned, loader and .data alignment

0008d7be20 tests: M2 TI ABI and ROM strlen in MAME

d4f165fa7d docs: record the M2 .data width and pointer-init rules

Compare 10 commits »

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:05:30 +02:00

696832dd44 docs: M2 TI ABI and ROM call

ce084040aa tms34010: align .data labels before .word/.long values

a9c33665ea tms34010: accept the optimizer's returned argument attribute

454fb4ac15 tms34010: emit .data and string literals for GSPA

0512ce9d6b tms34010: TI ABI calls and FS1 fixup

Compare 7 commits »

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 17:00:04 +02:00

opencode.siil.art… created branch m2 in opencode.siil.art…/llvm-tms34010 2026-11-11 16:59:28 +02:00

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 16:59:25 +02:00

c0746338b0 docs: M2 TI ABI and ROM call implementation plan