opencode.siil.arti.ee

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opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 21:56:22 +02:00

ed58040fbd docs: M3 control flow and first Xlib window

09db9e22e9 tests: M3 branches and first Xlib window in MAME

b34016a9f3 docs: correct M3 ROM bit displacements and unaligned-load carry-forward

2187f59b20 tests: M3 Xlib Display/Screen layout

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opencode.siil.art… pushed to m3 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:54:03 +02:00

opencode.siil.art… created branch m3 in opencode.siil.art…/llvm-tms34010 2026-11-11 19:54:03 +02:00

opencode.siil.art… pushed to m3 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:54:02 +02:00

d1ba1e4d86 docs: M3 control flow and first Xlib window plan

opencode.siil.art… created branch m3 in opencode.siil.art…/tms-c-compiler 2026-11-11 19:54:02 +02:00

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:36:20 +02:00

39512c272d tms34010: fix M2 data widths and FS0 after calls

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:36:20 +02:00

2d4919db36 docs: finalize M2 ABI and tail-call notes

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:15:48 +02:00

d7317305b9 tms34010: accept returned on call arguments and correct M2 docs

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:15:48 +02:00

f1a604d70e docs: correct M2 branch and epilogue guidance

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 19:05:34 +02:00

3a188b35fb docs: M2 TI ABI, ROM strlen and golden ABI check

fa00b8740b docs: finish the M2 loader and returned reconciliation

b614e70851 docs: reconcile M2 plan with JAUC, returned, loader and .data alignment

0008d7be20 tests: M2 TI ABI and ROM strlen in MAME

d4f165fa7d docs: record the M2 .data width and pointer-init rules

Compare 10 commits »

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 19:05:30 +02:00

696832dd44 docs: M2 TI ABI and ROM call

ce084040aa tms34010: align .data labels before .word/.long values

a9c33665ea tms34010: accept the optimizer's returned argument attribute

454fb4ac15 tms34010: emit .data and string literals for GSPA

0512ce9d6b tms34010: TI ABI calls and FS1 fixup

Compare 7 commits »

opencode.siil.art… pushed to m2 at opencode.siil.art…/llvm-tms34010 2026-11-11 17:00:04 +02:00

opencode.siil.art… created branch m2 in opencode.siil.art…/llvm-tms34010 2026-11-11 16:59:28 +02:00

opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 16:59:25 +02:00

c0746338b0 docs: M2 TI ABI and ROM call implementation plan

opencode.siil.art… created branch m2 in opencode.siil.art…/tms-c-compiler 2026-11-11 16:58:28 +02:00

opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 12:23:47 +02:00

7749cc810b scripts: fix stale M1 comments and tighten the harness checks

eacaab68f6 docs: correct the GEP scaling warning and M1 data limits

937a8cc800 tms-bitaddr: make --normalize reject typed and vector GEPs

Compare 3 commits »

opencode.siil.art… pushed to tms34010 at opencode.siil.art…/llvm-tms34010 2026-11-11 12:22:56 +02:00

be42cd46bc tms34010: add store codegen test and M1 test infra fixes

16a4358dd3 tms34010: fail loudly on non-GSPA globals

24522ce72f tms34010: reject unsupported M1 signatures and returns

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opencode.siil.art… pushed to tms34010 at opencode.siil.art…/llvm-tms34010 2026-11-11 11:54:59 +02:00

5e35e46b77 docs: M1 backend and test convention

52d3740b62 tms34010: emit GSPA-compatible asm and support -O0 globals

916b10bc28 tms34010: add FS0 i16 load-store codegen

39a4666cbe tms34010: add MOVE/MOVB load-store codegen

41d2467953 tms34010: fix CLR encoding to XOR-self form

Compare 7 commits »

opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 11:54:53 +02:00

56d6a71cb7 docs: M1 minimal backend and test convention

755b3cb7b2 tests: link M1 char helpers and check MOVB

b638ab0fad tests: M1 dis34 round-trip

6f776e1758 tests: pin the M1 .bss origin and second pointer marker

e0a721e3e1 tests: M1 GSPA/MAME smoke test

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opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 08:48:00 +02:00

e081921b72 plan: M1 minimal TMS34010 backend