opencode.siil.arti.ee
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opencode.siil.art… created branch m2 in opencode.siil.art…/llvm-tms34010 2026-11-11 16:59:28 +02:00
opencode.siil.art… pushed to m2 at opencode.siil.art…/tms-c-compiler 2026-11-11 16:59:25 +02:00
c0746338b0 docs: M2 TI ABI and ROM call implementation plan
opencode.siil.art… created branch m2 in opencode.siil.art…/tms-c-compiler 2026-11-11 16:58:28 +02:00
opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 12:23:47 +02:00
7749cc810b scripts: fix stale M1 comments and tighten the harness checks
eacaab68f6 docs: correct the GEP scaling warning and M1 data limits
937a8cc800 tms-bitaddr: make --normalize reject typed and vector GEPs
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opencode.siil.art… pushed to tms34010 at opencode.siil.art…/llvm-tms34010 2026-11-11 12:22:56 +02:00
be42cd46bc tms34010: add store codegen test and M1 test infra fixes
16a4358dd3 tms34010: fail loudly on non-GSPA globals
24522ce72f tms34010: reject unsupported M1 signatures and returns
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opencode.siil.art… pushed to tms34010 at opencode.siil.art…/llvm-tms34010 2026-11-11 11:54:59 +02:00
5e35e46b77 docs: M1 backend and test convention
52d3740b62 tms34010: emit GSPA-compatible asm and support -O0 globals
916b10bc28 tms34010: add FS0 i16 load-store codegen
39a4666cbe tms34010: add MOVE/MOVB load-store codegen
41d2467953 tms34010: fix CLR encoding to XOR-self form
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opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 11:54:53 +02:00
56d6a71cb7 docs: M1 minimal backend and test convention
755b3cb7b2 tests: link M1 char helpers and check MOVB
b638ab0fad tests: M1 dis34 round-trip
6f776e1758 tests: pin the M1 .bss origin and second pointer marker
e0a721e3e1 tests: M1 GSPA/MAME smoke test
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opencode.siil.art… pushed to m1 at opencode.siil.art…/tms-c-compiler 2026-11-11 08:48:00 +02:00
e081921b72 plan: M1 minimal TMS34010 backend
opencode.siil.art… created branch m1 in opencode.siil.art…/tms-c-compiler 2026-11-11 08:47:38 +02:00
opencode.siil.art… pushed to tms34010 at opencode.siil.art…/llvm-tms34010 2026-11-11 08:41:10 +02:00
389c194372 TMS34010: add 32-bit bit-addressed target and clang pointer semantics
392dfff97d [clang] Add release note for EmitDeferred re-emission fix on 23.x
8db94f8248 [clang][Modules] Keep existing global definition on type mismatch in GetOrCreateLLVMGlobal (#223877)
32e470fa5c [Clang] Don't skip lambda constraints when substituting type constraints (#236425)
20eceee39e Test-behaviour-changes from the cherry-pick of 46965cf.
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opencode.siil.art… created branch tms34010 in opencode.siil.art…/llvm-tms34010 2026-11-11 08:40:55 +02:00
opencode.siil.art… pushed to m0 at opencode.siil.art…/tms-c-compiler 2026-11-11 08:04:13 +02:00
d400e641fb docs: link the compiler fork and project repositories
opencode.siil.art… pushed to m0 at opencode.siil.art…/tms-c-compiler 2026-11-11 08:01:00 +02:00
668afbbf44 fix: address final review (subtarget, bool/char alignment, spike env, late-GEP tests)
795fcdc14a build: clean LLVM fork build from pinned tag and patches
4a2a9b2135 spike: re-run on LLVM 23.1.5
92354e8761 scripts: add M0 clang/scale/opt/normalize wrapper and tests
93f90607bb tools: add tms-bitaddr GEP scale and normalize tool
opencode.siil.art… created branch m0 in opencode.siil.art…/tms-c-compiler 2026-11-11 08:00:28 +02:00
opencode.siil.art… created repository opencode.siil.art…/llvm-tms34010 2026-11-11 07:58:19 +02:00
opencode.siil.art… created repository opencode.siil.art…/tms-c-compiler 2026-11-11 07:56:19 +02:00