1
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mirror of git://projects.qi-hardware.com/ben-blinkenlights.git synced 2024-12-25 09:43:00 +02:00

ubb-vga: added draft for "productized" design

- vga-ben.pro, vga-ben.sch, vga-ben.cmp, vga-ben.pro: similar to
  ubb-vga.sch, but with R and Y swapped (for better grounding), the VGA
  connector replaced by solder pads, and added pads for the shield
- Makefile (schp, brd): new targets for editing vga-ben
This commit is contained in:
Werner Almesberger 2011-05-04 12:46:34 -03:00
parent 01d33e28a7
commit 6f5a8ccf5a
5 changed files with 2097 additions and 1 deletions

View File

@ -5,7 +5,7 @@ CFLAGS=-Wall -g -O9 -march=mips32
LDFLAGS=-lm
OBJS=ubb-vga.o grabfb.o tstimg.o ppm.o ppmimg.o ccube.o physmem.o
.PHONY: all asm sch clean spotless
.PHONY: all asm sch schp brd clean spotless
all: ubb-vga ubb-vga-old
@ -17,6 +17,12 @@ asm: ubb-vga.c
sch:
eeschema `pwd`/ubb-vga.sch
schp:
eeschema `pwd`/vga-ben.sch
brd:
pcbnew `pwd`/vga-ben.brd
clean:
rm -f $(OBJS)

1416
ubb-vga/vga-ben.brd Normal file

File diff suppressed because it is too large Load Diff

164
ubb-vga/vga-ben.cmp Normal file
View File

@ -0,0 +1,164 @@
Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Wed May 4 05:35:31 2011
BeginCmp
TimeStamp = /4DB3AF38;
Reference = P1;
ValeurCmp = UBB;
IdModule = 8:10-card;
EndCmp
BeginCmp
TimeStamp = /4DC0FCC9;
Reference = P2;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FCA7;
Reference = P3;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FCBA;
Reference = P4;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FCC0;
Reference = P5;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FCD9;
Reference = P6;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FD3E;
Reference = P7;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FD45;
Reference = P8;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FD49;
Reference = P9;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FD4D;
Reference = P10;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FD51;
Reference = P11;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4DC0FDD2;
Reference = P12;
ValeurCmp = CONN_1;
IdModule = PAD_120x60;
EndCmp
BeginCmp
TimeStamp = /4DC0FDDD;
Reference = P13;
ValeurCmp = CONN_1;
IdModule = PAD_120x60;
EndCmp
BeginCmp
TimeStamp = /4DB5D0DD;
Reference = R1;
ValeurCmp = 1k;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D0DE;
Reference = R2;
ValeurCmp = 1k;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D0E0;
Reference = R3;
ValeurCmp = 1k;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D1BA;
Reference = R4;
ValeurCmp = 330;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB3AF49;
Reference = R5;
ValeurCmp = 470;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB3AF4B;
Reference = R6;
ValeurCmp = 470;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB3AF4D;
Reference = R7;
ValeurCmp = 470;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D125;
Reference = R8;
ValeurCmp = 82;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D129;
Reference = R9;
ValeurCmp = 82;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4DB5D12B;
Reference = R10;
ValeurCmp = 82;
IdModule = 0402;
EndCmp
EndListe

69
ubb-vga/vga-ben.pro Normal file
View File

@ -0,0 +1,69 @@
update=Wed May 4 12:46:08 2011
last_client=pcbnew
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=../../kicad-libs/components/8_10-card
LibName4=../../kicad-libs/components/vga
LibName5=conn
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=0
PadDimH=786
PadDimV=196
BoardThickness=630
SgPcb45=1
TxtPcbV=394
TxtPcbH=394
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=50
EdgeLar=50
TxtLar=79
MSegLar=150
LastNetListRead=vga-ben.net
[pcbnew/libraries]
LibDir=
LibName1=../../kicad-libs/modules/8_10-card
LibName2=../../kicad-libs/modules/pads
LibName3=../../kicad-libs/modules/stdpass

441
ubb-vga/vga-ben.sch Normal file
View File

@ -0,0 +1,441 @@
EESchema Schematic File Version 2 date Wed May 4 12:29:47 2011
LIBS:power
LIBS:device
LIBS:8_10-card
LIBS:vga
LIBS:conn
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 1 1
Title "Ben VGA Adapter"
Date "4 may 2011"
Rev "20110504"
Comp "Werner Almesberger"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
8550 3300 8550 2400
Wire Wire Line
8550 3300 9500 3300
Connection ~ 3750 5900
Wire Wire Line
3750 5900 3750 5850
Wire Wire Line
3750 5850 2850 5850
Connection ~ 3750 5650
Wire Wire Line
2850 5650 3750 5650
Connection ~ 3750 5450
Wire Wire Line
2850 5450 3750 5450
Wire Wire Line
3750 6050 3750 5250
Wire Wire Line
3750 5250 2850 5250
Wire Wire Line
2850 2100 7550 2100
Wire Wire Line
8150 4600 8150 4800
Connection ~ 8150 3400
Wire Wire Line
9500 3600 7550 3600
Wire Wire Line
7550 3600 7550 4800
Wire Notes Line
5700 4950 5700 5700
Wire Wire Line
6800 3700 7000 3700
Wire Wire Line
7000 3700 7000 3900
Wire Wire Line
7000 3900 9500 3900
Wire Wire Line
6300 3700 2850 3700
Connection ~ 5500 3300
Wire Wire Line
5500 3300 5500 3100
Connection ~ 5800 3500
Wire Wire Line
5800 3100 5800 3500
Connection ~ 6100 3700
Wire Wire Line
6100 3100 6100 3700
Connection ~ 6100 2400
Wire Wire Line
6100 2400 6100 2600
Wire Wire Line
5500 2600 5500 2400
Wire Wire Line
5500 2400 8550 2400
Wire Wire Line
5700 4400 5700 4600
Wire Wire Line
9300 4300 9300 3700
Wire Wire Line
9300 3700 9500 3700
Wire Wire Line
5400 4600 5400 4400
Wire Wire Line
6000 4400 6000 4600
Wire Wire Line
5800 2400 5800 2600
Connection ~ 5800 2400
Wire Wire Line
6000 3700 6000 3900
Connection ~ 6000 3700
Wire Wire Line
5700 3500 5700 3900
Connection ~ 5700 3500
Wire Wire Line
5400 3900 5400 3300
Connection ~ 5400 3300
Wire Wire Line
2850 3500 6300 3500
Wire Wire Line
6300 3300 2850 3300
Wire Wire Line
9500 3800 7100 3800
Wire Wire Line
7100 3800 7100 3500
Wire Wire Line
7100 3500 6800 3500
Wire Notes Line
5250 5100 6100 5100
Wire Wire Line
9500 3400 7550 3400
Wire Wire Line
7550 3400 7550 2100
Wire Wire Line
8150 4100 8150 3400
Wire Wire Line
7550 4800 2850 4800
Wire Wire Line
2850 5350 3750 5350
Connection ~ 3750 5350
Wire Wire Line
3750 5550 2850 5550
Connection ~ 3750 5550
Wire Wire Line
2850 5750 3750 5750
Connection ~ 3750 5750
Wire Wire Line
9500 3200 7100 3200
Wire Wire Line
7100 3200 7100 3300
Wire Wire Line
7100 3300 6800 3300
Text Label 3050 5850 0 60 ~ 0
SHIELD
Text Label 3050 5750 0 60 ~ 0
SHIELD
$Comp
L CONN_1 P13
U 1 1 4DC0FDDD
P 2700 5850
F 0 "P13" H 2780 5850 40 0000 L CNN
F 1 "CONN_1" H 2700 5905 30 0001 C CNN
1 2700 5850
-1 0 0 1
$EndComp
$Comp
L CONN_1 P12
U 1 1 4DC0FDD2
P 2700 5750
F 0 "P12" H 2780 5750 40 0000 L CNN
F 1 "CONN_1" H 2700 5805 30 0001 C CNN
1 2700 5750
-1 0 0 1
$EndComp
$Comp
L CONN_1 P11
U 1 1 4DC0FD51
P 2700 5650
F 0 "P11" H 2780 5650 40 0000 L CNN
F 1 "CONN_1" H 2700 5705 30 0001 C CNN
1 2700 5650
-1 0 0 1
$EndComp
$Comp
L CONN_1 P10
U 1 1 4DC0FD4D
P 2700 5550
F 0 "P10" H 2780 5550 40 0000 L CNN
F 1 "CONN_1" H 2700 5605 30 0001 C CNN
1 2700 5550
-1 0 0 1
$EndComp
$Comp
L CONN_1 P9
U 1 1 4DC0FD49
P 2700 5450
F 0 "P9" H 2780 5450 40 0000 L CNN
F 1 "CONN_1" H 2700 5505 30 0001 C CNN
1 2700 5450
-1 0 0 1
$EndComp
$Comp
L CONN_1 P8
U 1 1 4DC0FD45
P 2700 5350
F 0 "P8" H 2780 5350 40 0000 L CNN
F 1 "CONN_1" H 2700 5405 30 0001 C CNN
1 2700 5350
-1 0 0 1
$EndComp
$Comp
L CONN_1 P7
U 1 1 4DC0FD3E
P 2700 5250
F 0 "P7" H 2780 5250 40 0000 L CNN
F 1 "CONN_1" H 2700 5305 30 0001 C CNN
1 2700 5250
-1 0 0 1
$EndComp
$Comp
L CONN_1 P6
U 1 1 4DC0FCD9
P 2700 4800
F 0 "P6" H 2780 4800 40 0000 L CNN
F 1 "CONN_1" H 2700 4855 30 0001 C CNN
1 2700 4800
-1 0 0 1
$EndComp
$Comp
L CONN_1 P2
U 1 1 4DC0FCC9
P 2700 2100
F 0 "P2" H 2780 2100 40 0000 L CNN
F 1 "CONN_1" H 2700 2155 30 0001 C CNN
1 2700 2100
-1 0 0 1
$EndComp
$Comp
L CONN_1 P5
U 1 1 4DC0FCC0
P 2700 3700
F 0 "P5" H 2780 3700 40 0000 L CNN
F 1 "CONN_1" H 2700 3755 30 0001 C CNN
1 2700 3700
-1 0 0 1
$EndComp
$Comp
L CONN_1 P4
U 1 1 4DC0FCBA
P 2700 3500
F 0 "P4" H 2780 3500 40 0000 L CNN
F 1 "CONN_1" H 2700 3555 30 0001 C CNN
1 2700 3500
-1 0 0 1
$EndComp
$Comp
L CONN_1 P3
U 1 1 4DC0FCA7
P 2700 3300
F 0 "P3" H 2780 3300 40 0000 L CNN
F 1 "CONN_1" H 2700 3355 30 0001 C CNN
1 2700 3300
-1 0 0 1
$EndComp
$Comp
L GND #PWR01
U 1 1 4DB870FB
P 8150 4800
F 0 "#PWR01" H 8150 4800 30 0001 C CNN
F 1 "GND" H 8150 4730 30 0001 C CNN
1 8150 4800
1 0 0 -1
$EndComp
Text Label 3050 5550 0 60 ~ 0
VSYNC_GND
Text Label 3050 5650 0 60 ~ 0
HSYNC_GND
Text Label 3050 5450 0 60 ~ 0
BLUE_RTN
Text Label 3050 5350 0 60 ~ 0
GREEN_RTN
Text Label 3050 5250 0 60 ~ 0
RED_RTN
Text Notes 5250 5700 0 60 ~ 0
1 1 674 mV
Text Notes 5250 5550 0 60 ~ 0
1 0 250 mV
Text Notes 5250 5400 0 60 ~ 0
0 1 490 mV
Text Notes 5250 5250 0 60 ~ 0
0 0 0 mV
Text Notes 5250 5050 0 60 ~ 0
Y R/G/B Vout
Text Label 3050 4800 0 60 ~ 0
VSYNC
Text Label 3050 2100 0 60 ~ 0
HSYNC
Text Notes 7850 5050 0 60 ~ 0
Pull-down for R1 response start bit\n
Text Label 8850 3300 0 60 ~ 0
Y
$Comp
L R R4
U 1 1 4DB5D1BA
P 8150 4350
F 0 "R4" V 8230 4350 50 0000 C CNN
F 1 "330" V 8150 4350 50 0000 C CNN
1 8150 4350
-1 0 0 1
$EndComp
$Comp
L R R10
U 1 1 4DB5D12B
P 6000 4150
F 0 "R10" V 6080 4150 50 0000 C CNN
F 1 "82" V 6000 4150 50 0000 C CNN
1 6000 4150
-1 0 0 1
$EndComp
$Comp
L R R9
U 1 1 4DB5D129
P 5700 4150
F 0 "R9" V 5780 4150 50 0000 C CNN
F 1 "82" V 5700 4150 50 0000 C CNN
1 5700 4150
-1 0 0 1
$EndComp
$Comp
L R R8
U 1 1 4DB5D125
P 5400 4150
F 0 "R8" V 5480 4150 50 0000 C CNN
F 1 "82" V 5400 4150 50 0000 C CNN
1 5400 4150
-1 0 0 1
$EndComp
NoConn ~ 9500 3500
$Comp
L R R3
U 1 1 4DB5D0E0
P 6100 2850
F 0 "R3" V 6180 2850 50 0000 C CNN
F 1 "1k" V 6100 2850 50 0000 C CNN
1 6100 2850
-1 0 0 1
$EndComp
$Comp
L R R2
U 1 1 4DB5D0DE
P 5800 2850
F 0 "R2" V 5880 2850 50 0000 C CNN
F 1 "1k" V 5800 2850 50 0000 C CNN
1 5800 2850
-1 0 0 1
$EndComp
$Comp
L R R1
U 1 1 4DB5D0DD
P 5500 2850
F 0 "R1" V 5580 2850 50 0000 C CNN
F 1 "1k" V 5500 2850 50 0000 C CNN
1 5500 2850
-1 0 0 1
$EndComp
Text Label 8850 3600 0 60 ~ 0
VSYNC
Text Label 8850 3400 0 60 ~ 0
HSYNC
Text Label 8850 3900 0 60 ~ 0
B
Text Label 8850 3800 0 60 ~ 0
G
Text Label 8850 3200 0 60 ~ 0
R
Text Label 3050 3700 0 60 ~ 0
BLUE
Text Label 3050 3500 0 60 ~ 0
GREEN
Text Label 3050 3300 0 60 ~ 0
RED
$Comp
L GND #PWR02
U 1 1 4DB3B0C4
P 3750 6050
F 0 "#PWR02" H 3750 6050 30 0001 C CNN
F 1 "GND" H 3750 5980 30 0001 C CNN
1 3750 6050
1 0 0 -1
$EndComp
$Comp
L GND #PWR03
U 1 1 4DB3B04B
P 6000 4600
F 0 "#PWR03" H 6000 4600 30 0001 C CNN
F 1 "GND" H 6000 4530 30 0001 C CNN
1 6000 4600
1 0 0 -1
$EndComp
$Comp
L GND #PWR04
U 1 1 4DB3B04A
P 5700 4600
F 0 "#PWR04" H 5700 4600 30 0001 C CNN
F 1 "GND" H 5700 4530 30 0001 C CNN
1 5700 4600
1 0 0 -1
$EndComp
$Comp
L GND #PWR05
U 1 1 4DB3B048
P 5400 4600
F 0 "#PWR05" H 5400 4600 30 0001 C CNN
F 1 "GND" H 5400 4530 30 0001 C CNN
1 5400 4600
1 0 0 -1
$EndComp
$Comp
L GND #PWR06
U 1 1 4DB3AFED
P 9300 4300
F 0 "#PWR06" H 9300 4300 30 0001 C CNN
F 1 "GND" H 9300 4230 30 0001 C CNN
1 9300 4300
1 0 0 -1
$EndComp
$Comp
L R R7
U 1 1 4DB3AF4D
P 6550 3700
F 0 "R7" V 6630 3700 50 0000 C CNN
F 1 "470" V 6550 3700 50 0000 C CNN
1 6550 3700
0 -1 -1 0
$EndComp
$Comp
L R R6
U 1 1 4DB3AF4B
P 6550 3500
F 0 "R6" V 6630 3500 50 0000 C CNN
F 1 "470" V 6550 3500 50 0000 C CNN
1 6550 3500
0 -1 -1 0
$EndComp
$Comp
L R R5
U 1 1 4DB3AF49
P 6550 3300
F 0 "R5" V 6630 3300 50 0000 C CNN
F 1 "470" V 6550 3300 50 0000 C CNN
1 6550 3300
0 -1 -1 0
$EndComp
$Comp
L 8:10-CARD P1
U 1 1 4DB3AF38
P 9800 3500
F 0 "P1" H 9600 4050 60 0000 C CNN
F 1 "UBB" H 9850 2900 60 0000 C CNN
1 9800 3500
1 0 0 -1
$EndComp
$EndSCHEMATC