Combine two pcie patches (2nd patch undid the 1st patch) together
and refresh the other affected patches
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34132 3c298f89-4303-0410-b956-a3cf2f4a3e73
Many Laguna products have on-board GPS with Pulse-per-second (PPS)
support. This patch adds kernel support (statically) and adds
the platform data in laguna board support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34115 3c298f89-4303-0410-b956-a3cf2f4a3e73
ARM Linux PCI/PCIe hardware intialization needs to occur before device_init
as it does not support hotplug. I have modeled the cns3xxx PCIe init after
other ARM platforms. Registering it early resolves resource issues occuring
during bus enumeration that occur when a device driver is linked static in
the kernel.
Instead of passing in a bitmask to enable the 2 available ports, link detect
is used to enable ports that have a valid link.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34044 3c298f89-4303-0410-b956-a3cf2f4a3e73
Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33827 3c298f89-4303-0410-b956-a3cf2f4a3e73
level monitoring and control of Gateworks boards. It is used on several
product families spanning several different target architectures (ixp4xx,
cns3xxx, davinci).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33720 3c298f89-4303-0410-b956-a3cf2f4a3e73
Resolves crashes when probing multiple serial devices
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33719 3c298f89-4303-0410-b956-a3cf2f4a3e73
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33684 3c298f89-4303-0410-b956-a3cf2f4a3e73
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33683 3c298f89-4303-0410-b956-a3cf2f4a3e73
Resolves an issue where isochronouse USB would cause the driver to hang as
well as scheduling issues.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33579 3c298f89-4303-0410-b956-a3cf2f4a3e73
For cns3xxx SCU_CONFIGURATION always shows multipe cores but SCU_CPU_STATUS
shows which ones are active.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33566 3c298f89-4303-0410-b956-a3cf2f4a3e73
