sie-ceimtun/Examples/Beta1/logic/build/project_r.twr

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Release 12.2 Trace  (lin64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 25
project_r.ncd project.pcf

Design file:              project_r.ncd
Physical constraint file: project.pcf
Device,package,speed:     xc3s500e,vq100,-4 (PRODUCTION 1.27 2010-06-22)
Report level:             verbose report, limited to 25 items per constraint

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
addr<0>     |    4.669(F)|   -0.795(F)|clk_BUFGP         |   0.000|
addr<1>     |    4.669(F)|   -0.795(F)|clk_BUFGP         |   0.000|
addr<2>     |    4.652(F)|   -0.775(F)|clk_BUFGP         |   0.000|
addr<3>     |    4.652(F)|   -0.775(F)|clk_BUFGP         |   0.000|
addr<4>     |    4.648(F)|   -0.771(F)|clk_BUFGP         |   0.000|
addr<5>     |    4.648(F)|   -0.771(F)|clk_BUFGP         |   0.000|
addr<6>     |    4.650(F)|   -0.772(F)|clk_BUFGP         |   0.000|
addr<7>     |    4.693(F)|   -0.823(F)|clk_BUFGP         |   0.000|
addr<8>     |    4.693(F)|   -0.823(F)|clk_BUFGP         |   0.000|
addr<9>     |    4.669(F)|   -0.795(F)|clk_BUFGP         |   0.000|
addr<10>    |    4.666(F)|   -0.791(F)|clk_BUFGP         |   0.000|
addr<11>    |    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
addr<12>    |    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
ncs         |    4.667(F)|   -0.793(F)|clk_BUFGP         |   0.000|
nwe         |    4.666(F)|   -0.791(F)|clk_BUFGP         |   0.000|
quadA       |    4.665(R)|   -0.791(R)|clk_BUFGP         |   0.000|
quadB       |    4.665(R)|   -0.791(R)|clk_BUFGP         |   0.000|
quadC       |    4.667(R)|   -0.793(R)|clk_BUFGP         |   0.000|
quadD       |    4.669(R)|   -0.795(R)|clk_BUFGP         |   0.000|
reset       |    3.577(R)|   -0.297(R)|clk_BUFGP         |   0.000|
            |    4.083(F)|    0.032(F)|clk_BUFGP         |   0.000|
sram_data<0>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<1>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<2>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<3>|    4.664(F)|   -0.789(F)|clk_BUFGP         |   0.000|
sram_data<4>|    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
sram_data<5>|    4.667(F)|   -0.792(F)|clk_BUFGP         |   0.000|
sram_data<6>|    4.651(F)|   -0.774(F)|clk_BUFGP         |   0.000|
sram_data<7>|    4.651(F)|   -0.774(F)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
hbridge<0>  |   11.827(R)|clk_BUFGP         |   0.000|
            |   11.992(F)|clk_BUFGP         |   0.000|
hbridge<1>  |   11.508(R)|clk_BUFGP         |   0.000|
            |   11.284(F)|clk_BUFGP         |   0.000|
hbridge<2>  |   11.647(R)|clk_BUFGP         |   0.000|
            |   11.564(F)|clk_BUFGP         |   0.000|
hbridge<3>  |   11.465(R)|clk_BUFGP         |   0.000|
            |   11.334(F)|clk_BUFGP         |   0.000|
sram_data<0>|   12.695(F)|clk_BUFGP         |   0.000|
sram_data<1>|   13.050(F)|clk_BUFGP         |   0.000|
sram_data<2>|   12.938(F)|clk_BUFGP         |   0.000|
sram_data<3>|   12.388(F)|clk_BUFGP         |   0.000|
sram_data<4>|   12.405(F)|clk_BUFGP         |   0.000|
sram_data<5>|   12.539(F)|clk_BUFGP         |   0.000|
sram_data<6>|   13.285(F)|clk_BUFGP         |   0.000|
sram_data<7>|   13.367(F)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    5.315|    4.587|    4.326|    9.106|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ncs            |sram_data<0>   |    9.780|
ncs            |sram_data<1>   |    9.525|
ncs            |sram_data<2>   |    9.790|
ncs            |sram_data<3>   |    9.796|
ncs            |sram_data<4>   |   10.045|
ncs            |sram_data<5>   |    9.192|
ncs            |sram_data<6>   |   10.035|
ncs            |sram_data<7>   |   10.294|
noe            |sram_data<0>   |    8.726|
noe            |sram_data<1>   |    8.471|
noe            |sram_data<2>   |    8.736|
noe            |sram_data<3>   |    8.742|
noe            |sram_data<4>   |    8.991|
noe            |sram_data<5>   |    8.138|
noe            |sram_data<6>   |    8.981|
noe            |sram_data<7>   |    9.240|
---------------+---------------+---------+


Analysis completed Sat Oct 30 21:34:04 2010 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 239 MB