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wernermisc/labsw/labsw.cmp

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labsw/: added partially populated DIP6 sockets since DIP4 is hard to source
2011-09-30 10:03:08 +03:00
Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Fri Sep 30 03:49:48 2011
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
BeginCmp
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
TimeStamp = /4E55CABB;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = C1;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 4.7uF;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
TimeStamp = /4E55CAB9;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = C2;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 100nF;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E6BE90B;
Reference = C3;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 4.7uF;
IdModule = 0603;
EndCmp
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
BeginCmp
TimeStamp = /4E6BE909;
Reference = C4;
ValeurCmp = 100nF;
IdModule = 0603;
EndCmp
labsw/: added low-pass filters to button input (with help from Joerg Reisenweber)
2011-09-11 02:35:23 +03:00
BeginCmp
TimeStamp = /4E55BEC4/4E6BF245;
Reference = C5;
ValeurCmp = 1nF;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E6BF247;
Reference = C6;
ValeurCmp = 1nF;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E6BF249;
Reference = C7;
ValeurCmp = 1nF;
IdModule = 0603;
EndCmp
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
BeginCmp
TimeStamp = /4E534734;
Reference = CON1;
ValeurCmp = MINI_USB_B;
IdModule = miniUSB_B;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEE6;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = D1;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
ValeurCmp = DS;
labsw/: changed flyback diodes to SOT-323 (BAS16WT or similar)
2011-08-28 00:24:02 +03:00
IdModule = SOT-323;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEE5;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = D2;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
ValeurCmp = DS;
labsw/: changed flyback diodes to SOT-323 (BAS16WT or similar)
2011-08-28 00:24:02 +03:00
IdModule = SOT-323;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEEF;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = K1;
ValeurCmp = CONN_3;
IdModule = HDR-3x1-200mil;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEF0;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = K2;
ValeurCmp = CONN_3;
IdModule = HDR-3x1-200mil;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEED;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = K3;
ValeurCmp = SPDT-C;
IdModule = RELAY;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEEE;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = K4;
ValeurCmp = SPDT-C;
IdModule = RELAY;
EndCmp
BeginCmp
TimeStamp = /4E55CC1E;
Reference = P1;
ValeurCmp = CONN_4;
IdModule = HDR-4x1-100mil;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E55BEC4/4E55C01D;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = P2;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
ValeurCmp = CONN_6X2;
labsw/: redesigned rear connections to pair in/out by "near" potential Also separated front opto-coupler connections.
2011-09-27 17:55:57 +03:00
IdModule = HDR-6x2-100mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: redesigned rear connections to pair in/out by "near" potential Also separated front opto-coupler connections.
2011-09-27 17:55:57 +03:00
TimeStamp = /4E6BEDF0/4E8089C8;
Reference = P5;
ValeurCmp = CONN_1;
IdModule = HDR-1x1-100mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: redesigned rear connections to pair in/out by "near" potential Also separated front opto-coupler connections.
2011-09-27 17:55:57 +03:00
TimeStamp = /4E6BEDF0/4E8089CC;
Reference = P6;
ValeurCmp = CONN_1;
IdModule = HDR-1x1-100mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: redesigned rear connections to pair in/out by "near" potential Also separated front opto-coupler connections.
2011-09-27 17:55:57 +03:00
TimeStamp = /4E55BED6/4E8082C6;
Reference = P7;
ValeurCmp = CONN_2X2;
IdModule = HDR-2x2-100mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E8082CA;
Reference = P8;
ValeurCmp = CONN_2X2;
IdModule = HDR-2x2-100mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E8082CD;
Reference = P9;
ValeurCmp = CONN_2X2;
IdModule = HDR-2x2-100mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E8082CC;
Reference = P10;
ValeurCmp = CONN_2X2;
IdModule = HDR-2x2-100mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEEC;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = Q1;
ValeurCmp = NPN;
IdModule = SOT-323-CW;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEEB;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = Q2;
ValeurCmp = NPN;
IdModule = SOT-323-CW;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E55BEC4/4E6BEF4C;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = R1;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
ValeurCmp = 10k;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E55BEC4/4E6BEF4F;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = R2;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
ValeurCmp = 10k;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E55BEC4/4E6BEF55;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = R3;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E571DE7;
Reference = R4;
ValeurCmp = 100;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E571DE9;
Reference = R5;
ValeurCmp = 100;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E571DEB;
Reference = R6;
ValeurCmp = 100;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E6BECC3;
Reference = R7;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E6BECC7;
Reference = R8;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E6BECEB;
Reference = R9;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E6BECF1;
Reference = R10;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFB3;
Reference = R11;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFB2;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R12;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFB1;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R13;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFB0;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R14;
labsw/: power bypassing is now the way SiLabs recommend
2011-09-11 02:00:05 +03:00
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFAF;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R15;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 2512;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFAE;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R16;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 2512;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFAD;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R17;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 2512;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E55BFAC;
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
Reference = R18;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 2512;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEF3;
Reference = R19;
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEF2;
Reference = R20;
ValeurCmp = 150;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
IdModule = 0603;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEE8;
Reference = R21;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 0603;
EndCmp
BeginCmp
labsw/ changed internal pull-ups to external to remove sneak current path
2011-09-11 02:23:59 +03:00
TimeStamp = /4E6BEDF0/4E6BEEE7;
Reference = R22;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
ValeurCmp = 1k;
IdModule = 0603;
EndCmp
labsw/: added low-pass filters to button input (with help from Joerg Reisenweber)
2011-09-11 02:35:23 +03:00
BeginCmp
TimeStamp = /4E55BEC4/4E6BF237;
Reference = R23;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E6BF23E;
Reference = R24;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55BEC4/4E6BF242;
Reference = R25;
ValeurCmp = 10k;
IdModule = 0603;
EndCmp
labsw/: added hardware revision indication
2011-09-11 02:42:00 +03:00
BeginCmp
TimeStamp = /4E6BF476;
Reference = R26;
ValeurCmp = NC;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E6BF47E;
Reference = R27;
ValeurCmp = 0;
IdModule = 0603;
EndCmp
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
BeginCmp
TimeStamp = /4E5344A0;
Reference = U1;
ValeurCmp = C8051F320;
IdModule = LQFP32;
EndCmp
BeginCmp
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
TimeStamp = /4E55BED6/4E81E398;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = U2;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
ValeurCmp = OPTO-TRANS-2X4R;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
IdModule = DIP-8-300mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
TimeStamp = /4E55BED6/4E81E391;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = U3;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
ValeurCmp = OPTO-TRANS-2X4R;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
IdModule = DIP-8-300mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
TimeStamp = /4E55BED6/4E81E39B;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = U4;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
ValeurCmp = OPTO-TRANS-2X4R;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
IdModule = DIP-8-300mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
TimeStamp = /4E55BED6/4E81E39D;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = U5;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
ValeurCmp = OPTO-TRANS-2X4R;
labsw/: grouped opto-couplers for socketing; improved clearance of inputs
2011-08-28 16:46:02 +03:00
IdModule = DIP-8-300mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
TimeStamp = /4E6BEDF0/4E854A0D;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
Reference = U6;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
ValeurCmp = OPTO-TRANS-4;
labsw/: added partially populated DIP6 sockets since DIP4 is hard to source
2011-09-30 10:03:08 +03:00
IdModule = DIP-4/6-300mil;
labsw/: re-layout for the various design changes (including potential separation)
2011-09-30 09:06:10 +03:00
EndCmp
BeginCmp
TimeStamp = /4E6BEDF0/4E854A18;
Reference = U7;
ValeurCmp = OPTO-TRANS-4;
labsw/: added partially populated DIP6 sockets since DIP4 is hard to source
2011-09-30 10:03:08 +03:00
IdModule = DIP-4/6-300mil;
labsw/: schematics, layout, and header.fpd update (in progress)
2011-08-26 07:34:12 +03:00
EndCmp
BeginCmp
TimeStamp = /4E55CA29;
Reference = VR1;
ValeurCmp = VR;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55CA26;
Reference = VR2;
ValeurCmp = VR;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4E55CA27;
Reference = VR3;
ValeurCmp = VR;
IdModule = 0603;
EndCmp
EndListe
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