qi-hardware/xburst-tools
1
0
Fork 0
mirror of git://projects.qi-hardware.com/xburst-tools.git synced 2024-12-22 17:58:58 +02:00
Code

[xbboot] now xbboot can auto detect ingenic device cpu type by USB Product ID

Browse Source 
Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
Xiangfu Liu 2010-06-10 23:11:29 +08:00
parent 1176e151ab
commit 031b54c699
5 changed files with 30 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
xbboot/host-app/host_main.c
View File

@ -46,6 +46,8 @@
#define STAGE1_ADDRESS ("0x80002000")
uint8_t xburst_interface = 0;
uint8_t option_upload = 0;
uint16_t xburst_cpu = INGENIC_XBURST_JZ4760;
struct usb_dev_handle* open_xburst_device();
void close_xburst_device(struct usb_dev_handle* xburst_h);
@ -78,6 +80,7 @@ int main(int argc, char** argv)
goto xquit;
}
option_upload = 1;
struct timespec timx,tim1;
tim1.tv_sec = 1;
@ -173,6 +176,7 @@ struct usb_dev_handle* open_xburst_device()
goto xout;
}
xburst_dev = usb_dev;
xburst_cpu = usb_dev->descriptor.idProduct;
// keep searching to make sure there is only 1 XBurst device
}
}
@ -395,6 +399,12 @@ int send_request(struct usb_dev_handle* xburst_h, char* request, char* str_param
free(file_data);
goto xout_xburst_interface;
}
{
if(option_upload) {
memcpy(file_data + 8, &xburst_cpu, sizeof(unsigned int));
option_upload = 0;
}
}
usb_status = usb_bulk_write(xburst_h,
/* endpoint */ INGENIC_OUT_ENDPOINT,
/* bytes */ file_data,

2
xbboot/target-common/serial.c
View File

@ -7,8 +7,8 @@
// 3 of the License, or (at your option) any later version.
//
#include "serial.h"
#include "jz4740.h"
#include "serial.h"
void serial_putc(char c)
{

2
xbboot/target-stage1/board-jz4740.c
View File

@ -13,6 +13,8 @@ void gpio_init_4740()
{
__gpio_as_nand();
__gpio_as_sdram_32bit();
/* enable the TP4, TP5 as UART0 */
REG_GPIO_PXSELS(2) = 0x80000000;
__gpio_as_uart0();
__gpio_as_lcd_18bit();
__gpio_as_msc();

19
xbboot/target-stage1/board-jz4760.c
View File

@ -10,6 +10,11 @@
#include "jz4760.h"
#include "board-jz4760.h"
void nand_init_4760()
{
REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1;
}
void cpm_start_all_4760()
{
__cpm_start_all();
@ -46,7 +51,7 @@ void gpio_init_4760()
while(i--);
}
#endif
__gpio_as_nand_8bit(1);
__gpio_as_nand_16bit(1);
}
#define MHZ (1000 * 1000)
@ -529,11 +534,9 @@ for(times = 0; times < banks; times++) {
REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */
if(err == 0) {
// serial_puts("pass\n");
serial_puts("passed:");
serial_put_hex(times);
}
else {
// serial_puts("failed\n");
} else {
serial_put_hex(times);
}
@ -563,12 +566,10 @@ void ddr_mem_init(int msel, int hl, int tsel, int arg)
cpu_clk = ARG_CPU_SPEED;
#if defined(CONFIG_SDRAM_DDR2) // ddr2
serial_puts("\nddr2-\n");
ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10
| (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
| ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32;
#elif defined(CONFIG_SDRAM_DDR1) // ddr1
serial_puts("\nddr1-\n");
ddrc_cfg_reg = DDRC_CFG_BTRUN |DDRC_CFG_TYPE_DDR1
| (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
| ((DDR_CL_HALF?(DDR_CL&~0x8):((DDR_CL-1)|0x8))<<2)
@ -981,7 +982,7 @@ void sdram_init_4760(void)
#define MAX_DELAY_VALUES 16 /* quars (2) * hls (2) * msels (4) */
int j, index, quar;
int mem_index[MAX_DELAY_VALUES];
#if 1 // probe
#if 0 // probe
jzmemset(mem_index, 0, MAX_DELAY_VALUES);
for (i = 1; i < MAX_TSEL_VALUE; i ++) {
tsel = i;
@ -1041,7 +1042,6 @@ void sdram_init_4760(void)
{
int result = 0;
serial_puts("ddr test:");
result = ddr_dma_test(0);
if(result != 0)
serial_puts("FAIL!\n");
@ -1140,7 +1140,6 @@ void sdram_init_4760(void)
/* Wait for number of auto-refresh cycles */
tmp_cnt = (cpu_clk / 1000000) * 10;
while (tmp_cnt--);
ddr_dma_test(0);
if(testall)
testallmem();
}

12
xbboot/target-stage1/stage1.c
View File

@ -21,10 +21,10 @@ extern void pll_init_4760();
extern void cpm_start_all_4760();
extern void serial_init_4760(int uart);
extern void sdram_init_4760();
extern void nand_init_4760();
void load_args_4740()
{
ARG_CPU_ID = 0x4740;
ARG_EXTAL = 12 * 1000000;
ARG_CPU_SPEED = 21 * ARG_EXTAL;
ARG_PHM_DIV = 3;
@ -37,7 +37,6 @@ void load_args_4740()
void load_args_4760()
{
ARG_CPU_ID = 0x4760;
ARG_EXTAL = 12 * 1000000;
ARG_CPU_SPEED = 12 * ARG_EXTAL;
ARG_PHM_DIV = 3;
@ -51,28 +50,33 @@ void load_args_4760()
void c_main(void)
{
load_args_4740();
ARG_CPU_ID = * (int *)0x80002008;
switch (ARG_CPU_ID) {
case 0x4740:
load_args_4740();
gpio_init_4740();
serial_init_4740(0);
pll_init_4740();
sdram_init_4740();
nand_init_4740();
serial_puts("Ben NanoNote\n");
break;
case 0x4760:
load_args_4760();
gpio_init_4760();
cpm_start_all_4760();
serial_init_4760(1);
pll_init_4760();
sdram_init_4760();
nand_init_4760();
serial_puts("JZ4760 EVB lepus\n");
break;
default:
return;
}
serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup\n"
serial_puts("GPIO, clocks, SDRAM, UART setup\n"
"now jump back to BOOT ROM...\n");
if (ARG_CPU_ID == 0x4760) {