mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-22 07:39:42 +02:00
[xbboot] now xbboot can auto detect ingenic device cpu type by USB Product ID
Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
parent
1176e151ab
commit
031b54c699
@ -46,6 +46,8 @@
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#define STAGE1_ADDRESS ("0x80002000")
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#define STAGE1_ADDRESS ("0x80002000")
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uint8_t xburst_interface = 0;
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uint8_t xburst_interface = 0;
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uint8_t option_upload = 0;
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uint16_t xburst_cpu = INGENIC_XBURST_JZ4760;
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struct usb_dev_handle* open_xburst_device();
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struct usb_dev_handle* open_xburst_device();
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void close_xburst_device(struct usb_dev_handle* xburst_h);
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void close_xburst_device(struct usb_dev_handle* xburst_h);
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@ -78,6 +80,7 @@ int main(int argc, char** argv)
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goto xquit;
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goto xquit;
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}
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}
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option_upload = 1;
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struct timespec timx,tim1;
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struct timespec timx,tim1;
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tim1.tv_sec = 1;
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tim1.tv_sec = 1;
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@ -173,6 +176,7 @@ struct usb_dev_handle* open_xburst_device()
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goto xout;
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goto xout;
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}
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}
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xburst_dev = usb_dev;
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xburst_dev = usb_dev;
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xburst_cpu = usb_dev->descriptor.idProduct;
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// keep searching to make sure there is only 1 XBurst device
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// keep searching to make sure there is only 1 XBurst device
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}
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}
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}
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}
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@ -395,6 +399,12 @@ int send_request(struct usb_dev_handle* xburst_h, char* request, char* str_param
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free(file_data);
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free(file_data);
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goto xout_xburst_interface;
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goto xout_xburst_interface;
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}
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}
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{
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if(option_upload) {
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memcpy(file_data + 8, &xburst_cpu, sizeof(unsigned int));
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option_upload = 0;
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}
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}
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usb_status = usb_bulk_write(xburst_h,
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usb_status = usb_bulk_write(xburst_h,
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/* endpoint */ INGENIC_OUT_ENDPOINT,
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/* endpoint */ INGENIC_OUT_ENDPOINT,
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/* bytes */ file_data,
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/* bytes */ file_data,
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@ -7,8 +7,8 @@
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// 3 of the License, or (at your option) any later version.
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// 3 of the License, or (at your option) any later version.
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//
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//
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#include "serial.h"
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#include "jz4740.h"
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#include "jz4740.h"
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#include "serial.h"
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void serial_putc(char c)
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void serial_putc(char c)
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{
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{
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@ -13,6 +13,8 @@ void gpio_init_4740()
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{
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{
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__gpio_as_nand();
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__gpio_as_nand();
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__gpio_as_sdram_32bit();
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__gpio_as_sdram_32bit();
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/* enable the TP4, TP5 as UART0 */
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REG_GPIO_PXSELS(2) = 0x80000000;
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__gpio_as_uart0();
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__gpio_as_uart0();
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__gpio_as_lcd_18bit();
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__gpio_as_lcd_18bit();
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__gpio_as_msc();
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__gpio_as_msc();
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@ -10,6 +10,11 @@
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#include "jz4760.h"
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#include "jz4760.h"
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#include "board-jz4760.h"
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#include "board-jz4760.h"
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void nand_init_4760()
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{
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REG_NEMC_NFCSR |= NEMC_NFCSR_NFE1 | NEMC_NFCSR_NFCE1;
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}
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void cpm_start_all_4760()
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void cpm_start_all_4760()
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{
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{
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__cpm_start_all();
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__cpm_start_all();
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@ -46,7 +51,7 @@ void gpio_init_4760()
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while(i--);
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while(i--);
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}
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}
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#endif
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#endif
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__gpio_as_nand_8bit(1);
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__gpio_as_nand_16bit(1);
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}
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}
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#define MHZ (1000 * 1000)
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#define MHZ (1000 * 1000)
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@ -529,11 +534,9 @@ for(times = 0; times < banks; times++) {
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REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */
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REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */
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if(err == 0) {
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if(err == 0) {
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// serial_puts("pass\n");
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serial_puts("passed:");
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serial_put_hex(times);
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serial_put_hex(times);
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}
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} else {
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else {
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// serial_puts("failed\n");
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serial_put_hex(times);
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serial_put_hex(times);
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}
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}
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@ -563,12 +566,10 @@ void ddr_mem_init(int msel, int hl, int tsel, int arg)
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = ARG_CPU_SPEED;
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#if defined(CONFIG_SDRAM_DDR2) // ddr2
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#if defined(CONFIG_SDRAM_DDR2) // ddr2
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serial_puts("\nddr2-\n");
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ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10
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ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10
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| (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
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| (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
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| ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32;
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| ((DDR_CL-1) | 0x8)<<2 | DDR_BANK8<<1 | DDR_DW32;
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#elif defined(CONFIG_SDRAM_DDR1) // ddr1
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#elif defined(CONFIG_SDRAM_DDR1) // ddr1
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serial_puts("\nddr1-\n");
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ddrc_cfg_reg = DDRC_CFG_BTRUN |DDRC_CFG_TYPE_DDR1
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ddrc_cfg_reg = DDRC_CFG_BTRUN |DDRC_CFG_TYPE_DDR1
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| (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
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| (DDR_ROW-12)<<10 | (DDR_COL-8)<<8 | DDR_CS1EN<<7 | DDR_CS0EN<<6
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| ((DDR_CL_HALF?(DDR_CL&~0x8):((DDR_CL-1)|0x8))<<2)
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| ((DDR_CL_HALF?(DDR_CL&~0x8):((DDR_CL-1)|0x8))<<2)
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@ -981,7 +982,7 @@ void sdram_init_4760(void)
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#define MAX_DELAY_VALUES 16 /* quars (2) * hls (2) * msels (4) */
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#define MAX_DELAY_VALUES 16 /* quars (2) * hls (2) * msels (4) */
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int j, index, quar;
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int j, index, quar;
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int mem_index[MAX_DELAY_VALUES];
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int mem_index[MAX_DELAY_VALUES];
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#if 1 // probe
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#if 0 // probe
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jzmemset(mem_index, 0, MAX_DELAY_VALUES);
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jzmemset(mem_index, 0, MAX_DELAY_VALUES);
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for (i = 1; i < MAX_TSEL_VALUE; i ++) {
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for (i = 1; i < MAX_TSEL_VALUE; i ++) {
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tsel = i;
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tsel = i;
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@ -1041,7 +1042,6 @@ void sdram_init_4760(void)
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{
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{
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int result = 0;
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int result = 0;
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serial_puts("ddr test:");
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result = ddr_dma_test(0);
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result = ddr_dma_test(0);
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if(result != 0)
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if(result != 0)
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serial_puts("FAIL!\n");
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serial_puts("FAIL!\n");
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@ -1140,7 +1140,6 @@ void sdram_init_4760(void)
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/* Wait for number of auto-refresh cycles */
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/* Wait for number of auto-refresh cycles */
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tmp_cnt = (cpu_clk / 1000000) * 10;
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tmp_cnt = (cpu_clk / 1000000) * 10;
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while (tmp_cnt--);
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while (tmp_cnt--);
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ddr_dma_test(0);
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if(testall)
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if(testall)
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testallmem();
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testallmem();
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}
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}
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@ -21,10 +21,10 @@ extern void pll_init_4760();
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extern void cpm_start_all_4760();
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extern void cpm_start_all_4760();
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extern void serial_init_4760(int uart);
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extern void serial_init_4760(int uart);
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extern void sdram_init_4760();
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extern void sdram_init_4760();
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extern void nand_init_4760();
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void load_args_4740()
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void load_args_4740()
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{
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{
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ARG_CPU_ID = 0x4740;
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ARG_EXTAL = 12 * 1000000;
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ARG_EXTAL = 12 * 1000000;
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ARG_CPU_SPEED = 21 * ARG_EXTAL;
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ARG_CPU_SPEED = 21 * ARG_EXTAL;
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ARG_PHM_DIV = 3;
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ARG_PHM_DIV = 3;
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@ -37,7 +37,6 @@ void load_args_4740()
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void load_args_4760()
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void load_args_4760()
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{
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{
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ARG_CPU_ID = 0x4760;
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ARG_EXTAL = 12 * 1000000;
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ARG_EXTAL = 12 * 1000000;
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ARG_CPU_SPEED = 12 * ARG_EXTAL;
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ARG_CPU_SPEED = 12 * ARG_EXTAL;
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ARG_PHM_DIV = 3;
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ARG_PHM_DIV = 3;
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@ -51,28 +50,33 @@ void load_args_4760()
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void c_main(void)
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void c_main(void)
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{
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{
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load_args_4740();
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ARG_CPU_ID = * (int *)0x80002008;
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switch (ARG_CPU_ID) {
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switch (ARG_CPU_ID) {
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case 0x4740:
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case 0x4740:
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load_args_4740();
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gpio_init_4740();
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gpio_init_4740();
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serial_init_4740(0);
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serial_init_4740(0);
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pll_init_4740();
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pll_init_4740();
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sdram_init_4740();
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sdram_init_4740();
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nand_init_4740();
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nand_init_4740();
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serial_puts("Ben NanoNote\n");
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break;
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break;
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case 0x4760:
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case 0x4760:
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load_args_4760();
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gpio_init_4760();
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gpio_init_4760();
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cpm_start_all_4760();
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cpm_start_all_4760();
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serial_init_4760(1);
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serial_init_4760(1);
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pll_init_4760();
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pll_init_4760();
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sdram_init_4760();
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sdram_init_4760();
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nand_init_4760();
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serial_puts("JZ4760 EVB lepus\n");
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break;
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break;
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default:
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default:
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return;
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return;
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}
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}
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serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup\n"
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serial_puts("GPIO, clocks, SDRAM, UART setup\n"
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"now jump back to BOOT ROM...\n");
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"now jump back to BOOT ROM...\n");
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if (ARG_CPU_ID == 0x4760) {
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if (ARG_CPU_ID == 0x4760) {
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