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we have git repos keep u-boot
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xiangfu
parent
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commit
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@ -1,77 +0,0 @@
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*********************************************************************
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Steps to build the u-boot:
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Download and install the cross toolchain gcc version 4:
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$ cd /opt
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$ tar xjf mipseltools-gcc412-glibc261.tar.bz2
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$ export PATH=/opt/mipseltools-gcc412-glibc261/bin:$PATH
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Download the u-boot tarball u-boot-1.1.6.tar.bz2 and unpack it:
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$ tar xjf u-boot-1.1.6.tar.bz2
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Download the latest u-boot patch and patch it to the u-boot tree:
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$ cd u-boot-1.1.6
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$ gzip -cd ../u-boot-1.1.6-jz-yyyymmdd.patch.gz | patch -p1
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Make defconfig of the JZSOC based platform, eg:
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$ make apus_nand_config (NAND boot for JZ4750 APUS board)
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$ make pavo_config (NOR boot for JZ4740 PAVO board)
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or
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$ make pavo_nand_config (NAND boot for JZ4740 PAVO board)
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$ make pmpv2_config (NOR boot for JZ4730 PMP Ver 2.x board)
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or
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$ make pmpv2_nand_config (NAND boot for JZ4730 PMP Ver 2.x board)
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Build the u-boot:
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$ make
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Then burn the u-boot-nand.bin (for NAND flash) or u-boot.bin (for NOR flash)
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to the target board by using JDI or USB boot tool.
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*********************************************************************
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u-boot-1.1.6-jz-20090306.patch.gz
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* Nand driver was modified to support using nandwrite_mlc utils in linux to
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write uImage:
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nandwrite_mlc -a -p /dev/mtd2 uImage
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u-boot-1.1.6-jz-20090216.patch.gz
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* Support Jz4750
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* Support NAND of 4KB pagesize
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* The ECC position in NAND oob could be modified by defining CFG_NAND_ECC_POS
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in include/configs/xxx.h
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u-boot-1.1.6-jz-20080530.patch.gz:
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* Added Jz4725 DIPPER Board Support.
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* Added FOXCONN_PT035TN01 LCD panel support for PAVO board.
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* Modify jz4740_nand.c to optimize the RS correction algorithm.
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u-boot-1.1.6-jz-20080414.patch.gz:
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* nand_spl/nand_boot_jz4740.c: fixed a fatal bug of nand_load(), which will
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fail to load u-boot when meeting a bad block.
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* Modify the nand read/write/erase commands to enable the bad block handling.
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u-boot-1.1.6-jz-20080226.patch.gz:
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* Fixed method to test NAND bad block.
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u-boot-1.1.6-jz-20071205.patch.gz:
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* Add Jz4720 virgo board.
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* Add SD 2.0 (SDHC) card support.
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* Fix the nand wirte command.
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u-boot-1.1.6-jz-20071026.patch.gz:
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* Full package support for Jz4730 and Jz4740.
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@ -1,34 +0,0 @@
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From 64f6690dbfb512c7c55060f7b7ed1b5c085c3240 Mon Sep 17 00:00:00 2001
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From: xiangfu <xiangfu.z@gmail.com>
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Date: Mon, 13 Apr 2009 21:57:26 +0800
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Subject: [PATCH] change CPU speed
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---
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include/configs/pavo.h | 4 ++--
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1 files changed, 2 insertions(+), 2 deletions(-)
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diff --git a/include/configs/pavo.h b/include/configs/pavo.h
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index 432a6f8..9f4d4ad 100644
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--- a/include/configs/pavo.h
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+++ b/include/configs/pavo.h
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@@ -50,7 +50,7 @@
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#define JZ4740_NORBOOT_CFG JZ4740_NORBOOT_16BIT /* NOR Boot config code */
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#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
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-#define CFG_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
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+#define CFG_CPU_SPEED 252000000 /* CPU clock: 252 MHz */
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#define CFG_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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#define CFG_HZ (CFG_EXTAL/256) /* incrementer freq */
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@@ -104,7 +104,7 @@
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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-#define CFG_PROMPT "PAVO # " /* Monitor Command Prompt */
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+#define CFG_PROMPT "PI # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args*/
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--
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1.6.0.4
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@ -1,76 +0,0 @@
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From e8b5d16e1b6ece6a4821efa0b54d19d076306fdd Mon Sep 17 00:00:00 2001
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From: xiangfu <xiangfu.z@gmail.com>
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Date: Tue, 14 Apr 2009 11:55:07 +0800
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Subject: [PATCH] we don't find the RXD on the Pi's PCB. so I make the u-boot driectly boot kernel.
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change some config base on GGV's nandboot.
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---
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common/main.c | 3 ++-
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include/configs/pavo.h | 10 ++++++----
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2 files changed, 8 insertions(+), 5 deletions(-)
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diff --git a/common/main.c b/common/main.c
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index cc4b50f..7b90e3b 100644
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--- a/common/main.c
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+++ b/common/main.c
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@@ -404,7 +404,8 @@ void main_loop (void)
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debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
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- if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
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+ //if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
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+ if (s) {
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# ifdef CONFIG_AUTOBOOT_KEYED
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int prev = disable_ctrlc(1); /* disable Control C checking */
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# endif
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diff --git a/include/configs/pavo.h b/include/configs/pavo.h
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index 9f4d4ad..93f0a35 100644
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--- a/include/configs/pavo.h
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+++ b/include/configs/pavo.h
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@@ -25,13 +25,15 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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+#define DEBUG
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+#define CONFIG_DEBUG
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_JzRISC 1 /* JzRISC core */
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#define CONFIG_JZSOC 1 /* Jz SoC */
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#define CONFIG_JZ4740 1 /* Jz4740 SoC */
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#define CONFIG_PAVO 1 /* PAVO validation board */
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-#define CONFIG_LCD /* LCD support */
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+//#define CONFIG_LCD /* LCD support */
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//#define CONFIG_SLCD /* LCD support */
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#ifndef CONFIG_SLCD /* LCD support */
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@@ -83,7 +85,7 @@
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#define CONFIG_BOOTFILE "uImage" /* file to load */
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#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw"
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#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x300000;bootm"
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-#define CFG_AUTOLOAD "n" /* No autoload */
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+#define CFG_AUTOLOAD "y" /* No autoload */
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//#define CONFIG_NET_MULTI
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@@ -206,7 +208,7 @@
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#define CONFIG_NR_DRAM_BANKS 1
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// SDRAM paramters
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-#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
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+#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
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#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define SDRAM_ROW 13 /* Row address: 11 to 13 */
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#define SDRAM_COL 9 /* Column address: 8 to 12 */
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@@ -217,7 +219,7 @@
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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-#define SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
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+#define SDRAM_TREF 15625 /* Refresh period: 8192 refresh cycles/64ms */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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--
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1.6.0.4
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