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git://projects.qi-hardware.com/xburst-tools.git
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[xbboot] fix the jz4760 compile error
Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
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0a13a84800
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@ -4,8 +4,22 @@
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#ifndef __JZ4760_H__
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#define __JZ4760_H__
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#ifndef __ASSEMBLY__
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#if 0 /* if 0, for spl program */
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#define UCOS_CSP 0
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#if UCOS_CSP
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#define __KERNEL__
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#include <bsp.h>
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#include <types.h>
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#include <sysdefs.h>
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#include <cacheops.h>
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#define KSEG0 KSEG0BASE
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#else
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#endif
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#define cache_unroll(base,op) \
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__asm__ __volatile__(" \
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.set noreorder; \
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@ -79,7 +93,6 @@ static inline u32 jz_readl(u32 address)
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return *((volatile u32 *)address);
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}
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#endif
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#endif /* !ASSEMBLY */
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//----------------------------------------------------------------------
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// Boot ROM Specification
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@ -17,7 +17,7 @@ CFLAGS = -O2 -fno-unit-at-a-time -fno-zero-initialized-in-bss -mips32 -fno-pic \
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LDFLAGS = -nostdlib -EL -T target.ld
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VPATH = ../target-common
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OBJS = head.o stage1.o serial.o board-jz4740.o #board-jz4760.o
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OBJS = head.o stage1.o serial.o board-jz4740.o board-jz4760.o
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all: stage1.bin
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@ -6,9 +6,16 @@
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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*/
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#include "common.h"
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#include "jz4760.h"
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#include "configs.h"
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#include "board_4760.h"
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#include "board-jz4760.h"
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#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
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void cpm_start_all()
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{
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__cpm_start_all();
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}
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/*
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* SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT#
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@ -332,7 +339,7 @@ static int ddr_dma_test(int print_flag) {
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REG_DMAC_DMADCKE(1) = 0x3f;
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#ifndef CONFIG_DDRC
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banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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@ -688,8 +695,6 @@ void testallmem()
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}
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#define DMAC_BASE MDMAC_BASE
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#define DDR_DMA_BASE (0xa0000000) /*un-cached*/
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void dma_data_move(int dma_chan, int dma_src_addr, int dma_dst_addr, int size, int burst)
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@ -749,7 +754,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) {
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int channel;
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#ifndef CONFIG_DDRC
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banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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@ -1190,7 +1195,7 @@ void sdram_init_4760(void)
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(ARG_BANK_ADDR_2BIT<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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@ -1253,7 +1258,7 @@ void sdram_init_4760(void)
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}
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#endif
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void serial_setbrg_4760(void)
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static void serial_setbrg(void)
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{
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volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
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volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
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@ -1274,3 +1279,31 @@ void serial_setbrg_4760(void)
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tmp &= ~UART_LCR_DLAB;
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*uart_lcr = tmp;
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}
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void serial_init_4760(int uart)
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{
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UART_BASE = UART0_BASE + uart * UART_OFF;
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volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
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volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
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volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
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volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
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/* Disable port interrupts while changing hardware */
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*uart_ier = 0;
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/* Disable UART unit function */
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*uart_fcr = ~UART_FCR_UUE;
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/* Set both receiver and transmitter in UART mode (not SIR) */
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*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
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/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
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/* Set baud rate */
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serial_setbrg();
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/* Enable UART unit, enable and clear FIFO */
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*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
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}
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@ -12,9 +12,9 @@
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//#define CONFIG_FPGA
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//#define DEBUG
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//#define CONFIG_SDRAM_MDDR
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#define CONFIG_SDRAM_MDDR
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//#define CONFIG_SDRAM_DDR1
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#define CONFIG_SDRAM_DDR2
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//#define CONFIG_SDRAM_DDR2
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//#define CONFIG_LOAD_UBOOT /* if not defined, load zImage */
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@ -43,7 +43,7 @@ void load_args_4760()
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ARG_PHM_DIV = 3;
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ARG_UART_BAUD = 57600;
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ARG_BUS_WIDTH_16 = * (int *)0x80002014;
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ARG_BANK_ADDR_2BIT = 1;
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ARG_BANK_ADDR_2BIT = 4;
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ARG_ROW_ADDR = 12;
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ARG_COL_ADDR = 9;
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}
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@ -62,6 +62,16 @@ void c_main(void)
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nand_init_4740();
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break;
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case 0x4760:
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gpio_init_4760();
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cpm_start_all();
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serial_init_4760(1);
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pll_init_4760();
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sdram_init_4760();
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__asm__ (
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"li $31, 0xbfc012e0 \n\t"
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"jr $31 \n\t "
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);
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break;
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default:
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return;
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