mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-01 10:22:48 +02:00
[xbboot] fix the jz4760 compile error
Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
parent
0a13a84800
commit
35c0b21b65
@ -4,8 +4,22 @@
|
|||||||
#ifndef __JZ4760_H__
|
#ifndef __JZ4760_H__
|
||||||
#define __JZ4760_H__
|
#define __JZ4760_H__
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#if 0 /* if 0, for spl program */
|
#if 0 /* if 0, for spl program */
|
||||||
|
#define UCOS_CSP 0
|
||||||
|
|
||||||
|
#if UCOS_CSP
|
||||||
|
#define __KERNEL__
|
||||||
|
#include <bsp.h>
|
||||||
|
#include <types.h>
|
||||||
|
|
||||||
|
#include <sysdefs.h>
|
||||||
|
#include <cacheops.h>
|
||||||
|
#define KSEG0 KSEG0BASE
|
||||||
|
#else
|
||||||
|
#include <asm/addrspace.h>
|
||||||
|
#include <asm/cacheops.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
#define cache_unroll(base,op) \
|
#define cache_unroll(base,op) \
|
||||||
__asm__ __volatile__(" \
|
__asm__ __volatile__(" \
|
||||||
.set noreorder; \
|
.set noreorder; \
|
||||||
@ -79,7 +93,6 @@ static inline u32 jz_readl(u32 address)
|
|||||||
return *((volatile u32 *)address);
|
return *((volatile u32 *)address);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
#endif /* !ASSEMBLY */
|
|
||||||
|
|
||||||
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
||||||
// Boot ROM Specification
|
// Boot ROM Specification
|
||||||
|
@ -17,7 +17,7 @@ CFLAGS = -O2 -fno-unit-at-a-time -fno-zero-initialized-in-bss -mips32 -fno-pic \
|
|||||||
LDFLAGS = -nostdlib -EL -T target.ld
|
LDFLAGS = -nostdlib -EL -T target.ld
|
||||||
VPATH = ../target-common
|
VPATH = ../target-common
|
||||||
|
|
||||||
OBJS = head.o stage1.o serial.o board-jz4740.o #board-jz4760.o
|
OBJS = head.o stage1.o serial.o board-jz4740.o board-jz4760.o
|
||||||
|
|
||||||
all: stage1.bin
|
all: stage1.bin
|
||||||
|
|
||||||
|
@ -6,9 +6,16 @@
|
|||||||
* Copyright (C) 2006 Ingenic Semiconductor Inc.
|
* Copyright (C) 2006 Ingenic Semiconductor Inc.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
#include "common.h"
|
||||||
#include "jz4760.h"
|
#include "jz4760.h"
|
||||||
#include "configs.h"
|
#include "board-jz4760.h"
|
||||||
#include "board_4760.h"
|
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
|
||||||
|
|
||||||
|
void cpm_start_all()
|
||||||
|
{
|
||||||
|
__cpm_start_all();
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT#
|
* SD0 ~ SD7, SA0 ~ SA5, CS2#, RD#, WR#, WAIT#
|
||||||
@ -332,7 +339,7 @@ static int ddr_dma_test(int print_flag) {
|
|||||||
REG_DMAC_DMADCKE(1) = 0x3f;
|
REG_DMAC_DMADCKE(1) = 0x3f;
|
||||||
|
|
||||||
#ifndef CONFIG_DDRC
|
#ifndef CONFIG_DDRC
|
||||||
banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
|
banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
|
||||||
#else
|
#else
|
||||||
banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
|
banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
|
||||||
#endif
|
#endif
|
||||||
@ -688,8 +695,6 @@ void testallmem()
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#define DMAC_BASE MDMAC_BASE
|
|
||||||
|
|
||||||
#define DDR_DMA_BASE (0xa0000000) /*un-cached*/
|
#define DDR_DMA_BASE (0xa0000000) /*un-cached*/
|
||||||
|
|
||||||
void dma_data_move(int dma_chan, int dma_src_addr, int dma_dst_addr, int size, int burst)
|
void dma_data_move(int dma_chan, int dma_src_addr, int dma_dst_addr, int size, int burst)
|
||||||
@ -749,7 +754,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) {
|
|||||||
int channel;
|
int channel;
|
||||||
|
|
||||||
#ifndef CONFIG_DDRC
|
#ifndef CONFIG_DDRC
|
||||||
banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
|
banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
|
||||||
#else
|
#else
|
||||||
banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
|
banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
|
||||||
#endif
|
#endif
|
||||||
@ -1190,7 +1195,7 @@ void sdram_init_4760(void)
|
|||||||
/* Basic DMCR value */
|
/* Basic DMCR value */
|
||||||
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
|
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
|
||||||
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
|
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
|
||||||
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
|
(ARG_BANK_ADDR_2BIT<<EMC_DMCR_BA_BIT) |
|
||||||
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
||||||
EMC_DMCR_EPIN |
|
EMC_DMCR_EPIN |
|
||||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||||
@ -1253,7 +1258,7 @@ void sdram_init_4760(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void serial_setbrg_4760(void)
|
static void serial_setbrg(void)
|
||||||
{
|
{
|
||||||
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||||
volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
|
volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
|
||||||
@ -1274,3 +1279,31 @@ void serial_setbrg_4760(void)
|
|||||||
tmp &= ~UART_LCR_DLAB;
|
tmp &= ~UART_LCR_DLAB;
|
||||||
*uart_lcr = tmp;
|
*uart_lcr = tmp;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void serial_init_4760(int uart)
|
||||||
|
{
|
||||||
|
UART_BASE = UART0_BASE + uart * UART_OFF;
|
||||||
|
|
||||||
|
volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
|
||||||
|
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||||
|
volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
|
||||||
|
volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
|
||||||
|
|
||||||
|
/* Disable port interrupts while changing hardware */
|
||||||
|
*uart_ier = 0;
|
||||||
|
|
||||||
|
/* Disable UART unit function */
|
||||||
|
*uart_fcr = ~UART_FCR_UUE;
|
||||||
|
|
||||||
|
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||||
|
*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
|
||||||
|
|
||||||
|
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
|
||||||
|
*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
|
||||||
|
|
||||||
|
/* Set baud rate */
|
||||||
|
serial_setbrg();
|
||||||
|
|
||||||
|
/* Enable UART unit, enable and clear FIFO */
|
||||||
|
*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
|
||||||
|
}
|
||||||
|
@ -12,9 +12,9 @@
|
|||||||
//#define CONFIG_FPGA
|
//#define CONFIG_FPGA
|
||||||
//#define DEBUG
|
//#define DEBUG
|
||||||
|
|
||||||
//#define CONFIG_SDRAM_MDDR
|
#define CONFIG_SDRAM_MDDR
|
||||||
//#define CONFIG_SDRAM_DDR1
|
//#define CONFIG_SDRAM_DDR1
|
||||||
#define CONFIG_SDRAM_DDR2
|
//#define CONFIG_SDRAM_DDR2
|
||||||
|
|
||||||
//#define CONFIG_LOAD_UBOOT /* if not defined, load zImage */
|
//#define CONFIG_LOAD_UBOOT /* if not defined, load zImage */
|
||||||
|
|
||||||
|
@ -43,7 +43,7 @@ void load_args_4760()
|
|||||||
ARG_PHM_DIV = 3;
|
ARG_PHM_DIV = 3;
|
||||||
ARG_UART_BAUD = 57600;
|
ARG_UART_BAUD = 57600;
|
||||||
ARG_BUS_WIDTH_16 = * (int *)0x80002014;
|
ARG_BUS_WIDTH_16 = * (int *)0x80002014;
|
||||||
ARG_BANK_ADDR_2BIT = 1;
|
ARG_BANK_ADDR_2BIT = 4;
|
||||||
ARG_ROW_ADDR = 12;
|
ARG_ROW_ADDR = 12;
|
||||||
ARG_COL_ADDR = 9;
|
ARG_COL_ADDR = 9;
|
||||||
}
|
}
|
||||||
@ -62,6 +62,16 @@ void c_main(void)
|
|||||||
nand_init_4740();
|
nand_init_4740();
|
||||||
break;
|
break;
|
||||||
case 0x4760:
|
case 0x4760:
|
||||||
|
gpio_init_4760();
|
||||||
|
cpm_start_all();
|
||||||
|
serial_init_4760(1);
|
||||||
|
pll_init_4760();
|
||||||
|
sdram_init_4760();
|
||||||
|
__asm__ (
|
||||||
|
"li $31, 0xbfc012e0 \n\t"
|
||||||
|
"jr $31 \n\t "
|
||||||
|
);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return;
|
return;
|
||||||
|
Loading…
Reference in New Issue
Block a user