add usb_boot.cfg file

flash-tool/usb_boot.cfg

@@ -0,0 +1,57 @@
+/*
+ * create nand flash image for pavo board
+ *
+ * Copyright (C) 2009 xiangfu <xiangfu@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+# [PLL]
+EXTCLK = 12	#Define the external crystal in MHz
+CPUSPEED = 252	#Define the PLL output frequency
+PHMDIV = 3	#Define the frequency divider ratio of PLL=CCLK:PCLK=HCLK=MCLK
+BOUDRATE = 57600	#Define the uart boudrate
+USEUART = 0	#Use which uart, 0/1 for jz4740,0/1/2/3 for jz4750
+
+# [SDRAM]
+BUSWIDTH = 16	#The bus width of the SDRAM in bits (16|32)
+BANKS = 4	#The bank number (2|4)
+ROWADDR = 13	#Row address width in bits (11-13)
+COLADDR = 9	#Column address width in bits (8-12)
+ISMOBILE = 0	#Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,1:yes 0:no
+ISBUSSHARE = 1	#Define whether SDRAM bus share with NAND 1:shared 0:unshared
+
+# [NAND]
+BUSWIDTH = 8	#The width of the NAND flash chip in bits (8|16|32)
+ROWCYCLES = 3	#The row address cycles (2|3)
+PAGESIZE = 2048	#The page size of the NAND chip in bytes(512|2048|4096)
+PAGEPERBLOCK = 128 	#The page number per block
+FORCEERASE = 1	#The force to erase flag (0|1)
+OOBSIZE = 64	#oob size in byte
+ECCPOS          = 6	#Specify the ECC offset inside the oob data (0-[oobsize-1])
+BADBLACKPOS      = 0	#Specify the badblock flag offset inside the oob (0-[oobsize-1])
+BADBLACKPAGE     = 127   	#Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
+PLANENUM = 1	#The planes number of target nand flash
+BCHBIT = 4	#Specify the hardware BCH algorithm for 4750 (4|8)
+WPPIN = 0	#Specify the write protect pin number
+BLOCKPERCHIP = 0	#Specify the block number per chip,0 means ignore
+
+# [END]
+
+#The program will calculate the total SDRAM size by : size = 2^(ROWADDR + COLADDR) * BANKNUM * (SDRAMWIDTH / 4)
+#The CPUSPEED has restriction as: ( CPUSPEED % EXTCLK == 0 ) && ( CPUSPEED % 12 == 0 )
+#For jz4750, the program just init BANK0(DSC0).
+#Beware all variables must be set correct!

flash-tool/usb_boot_defines.h

@@ -0,0 +1,135 @@
+#ifndef __JZ4740_USBDEFINES__H_
+#define __JZ4740_USBDEFINES__H_
+
+/* #define dprintf(x...) printf(x) */
+#define SDRAM_SIZE ( 16 * 1024 * 1024 )
+#define CODE_SIZE  ( 4 * 1024 * 1024 )
+/* #define START_ADDR ( 0x80000000 + SDRAM_SIZE - CODE_SIZE ) */
+
+#define MAX_COMMAND_LENGTH 100
+#define COMMAND_NUM 31
+#define NAND_MAX_BLK_NUM  10000000	/* ((Hand.nand_pn / Hand.nand_ppb) + 1) */
+#define NAND_MAX_PAGE_NUM 1073740824	/*Hand.nand_pn */
+#define NAND_SECTION_NUM 23
+#define MAX_TRANSFER_SIZE 0x100000
+#define MAX_LOAD_SIZE 0x3000
+#define NAND_MAX_BYTE_NUM (Hand.nand_pn * Hand.nand_ps)
+#define	IOCTL_INBUF_SIZE	512
+#define	IOCTL_OUTBUF_SIZE	512
+#define MAX_DEV_NUM 16 
+
+enum CPUTYPE 
+{
+	JZ4740,
+	JZ4750,
+};
+
+enum USB_Boot_State 
+{
+	DISCONNECT,
+	CONNECT,
+	BOOT,
+	UNBOOT
+};
+
+enum OPTION
+{
+	OOB_ECC,
+	OOB_NO_ECC,
+	NO_OOB,
+};
+
+enum NOR_OPS_TYPE
+{
+	NOR_INIT = 0,
+	NOR_QUERY,
+	NOR_WRITE,
+	NOR_ERASE_CHIP,
+	NOR_ERASE_SECTOR
+};
+
+enum NOR_FLASH_TYPE
+{
+	NOR_AM29 = 0,
+	NOR_SST28,
+	NOR_SST39x16,
+	NOR_SST39x8
+};
+
+enum NAND_OPS_TYPE
+{
+	NAND_QUERY = 0,
+	NAND_INIT,
+	NAND_MARK_BAD,
+	NAND_READ_OOB,
+	NAND_READ_RAW,
+	NAND_ERASE,
+	NAND_READ,
+	NAND_PROGRAM,
+	NAND_READ_TO_RAM
+};
+
+enum SDRAM_OPS_TYPE
+{
+	SDRAM_LOAD,
+};
+
+enum DATA_STRUCTURE_OB
+{
+	DS_flash_info ,
+	DS_hand
+};
+
+typedef struct {
+	/* CPU ID */
+	unsigned int  cpu_id;
+	/* PLL args */
+	unsigned char ext_clk;
+	unsigned char cpu_speed;
+	unsigned char phm_div;
+	unsigned char use_uart;
+	unsigned int  boudrate;
+
+	/* SDRAM args */
+	unsigned char bus_width;
+	unsigned char bank_num;
+	unsigned char row_addr;
+	unsigned char col_addr;
+	unsigned char is_mobile;
+	unsigned char is_busshare;
+
+	/* debug args */
+	unsigned char debug_ops;
+	unsigned char pin_num;
+	unsigned int  start;
+	unsigned int  size;
+
+	/* for align */
+	/* unsigned char align1; */
+	/* unsigned char align2; */
+}fw_args_t;
+
+typedef struct {
+
+	/* nand flash info */
+	int pt;             	/* cpu type */
+	int nand_bw;		/* bus width */
+	int nand_rc;		/* row cycle */
+	int nand_ps;		/* page size */
+	int nand_ppb;		/* page number per block */
+	int nand_force_erase;
+	int nand_pn;		/* page number in total */
+	int nand_os;		/* oob size */
+	int nand_eccpos;
+	int nand_bbpage;
+	int nand_bbpos;
+	int nand_plane;
+	int nand_bchbit;
+	int nand_wppin;
+	int nand_bpc;		/* block number per chip */
+
+	fw_args_t fw_args;
+
+} hand_t;
+
+#endif	/* __JZ4740_USBDEFINES__H_ */