mirror of
git://projects.qi-hardware.com/xburst-tools.git
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add-glamo-init.patch
We have to init PLLs and memory and other assets in Glamo before we can use SD Card stuff. Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green
Andy Green
parent
ee7de6d4ab
commit
9759d4e910
1
qiboot/include/glamo-init.h
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1
qiboot/include/glamo-init.h
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extern void glamo_core_init(void);
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459
qiboot/include/glamo_regs.h
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459
qiboot/include/glamo_regs.h
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#ifndef _GLAMO_REGS_H
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#define _GLAMO_REGS_H
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/* Smedia Glamo 336x/337x driver
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*
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* (C) 2007 by OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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enum glamo_regster_offsets {
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GLAMO_REGOFS_GENERIC = 0x0000,
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GLAMO_REGOFS_HOSTBUS = 0x0200,
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GLAMO_REGOFS_MEMORY = 0x0300,
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GLAMO_REGOFS_VIDCAP = 0x0400,
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GLAMO_REGOFS_ISP = 0x0500,
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GLAMO_REGOFS_JPEG = 0x0800,
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GLAMO_REGOFS_MPEG = 0x0c00,
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GLAMO_REGOFS_LCD = 0x1100,
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GLAMO_REGOFS_MMC = 0x1400,
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GLAMO_REGOFS_MPROC0 = 0x1500,
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GLAMO_REGOFS_MPROC1 = 0x1580,
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GLAMO_REGOFS_CMDQUEUE = 0x1600,
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GLAMO_REGOFS_RISC = 0x1680,
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GLAMO_REGOFS_2D = 0x1700,
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GLAMO_REGOFS_3D = 0x1b00,
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};
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enum glamo_register_generic {
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GLAMO_REG_GCONF1 = 0x0000,
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GLAMO_REG_GCONF2 = 0x0002,
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#define GLAMO_REG_DEVICE_ID GLAMO_REG_GCONF2
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GLAMO_REG_GCONF3 = 0x0004,
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#define GLAMO_REG_REVISION_ID GLAMO_REG_GCONF3
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GLAMO_REG_IRQ_GEN1 = 0x0006,
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#define GLAMO_REG_IRQ_ENABLE GLAMO_REG_IRQ_GEN1
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GLAMO_REG_IRQ_GEN2 = 0x0008,
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#define GLAMO_REG_IRQ_SET GLAMO_REG_IRQ_GEN2
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GLAMO_REG_IRQ_GEN3 = 0x000a,
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#define GLAMO_REG_IRQ_CLEAR GLAMO_REG_IRQ_GEN3
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GLAMO_REG_IRQ_GEN4 = 0x000c,
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#define GLAMO_REG_IRQ_STATUS GLAMO_REG_IRQ_GEN4
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GLAMO_REG_CLOCK_HOST = 0x0010,
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GLAMO_REG_CLOCK_MEMORY = 0x0012,
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GLAMO_REG_CLOCK_LCD = 0x0014,
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GLAMO_REG_CLOCK_MMC = 0x0016,
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GLAMO_REG_CLOCK_ISP = 0x0018,
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GLAMO_REG_CLOCK_JPEG = 0x001a,
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GLAMO_REG_CLOCK_3D = 0x001c,
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GLAMO_REG_CLOCK_2D = 0x001e,
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GLAMO_REG_CLOCK_RISC1 = 0x0020, /* 3365 only? */
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GLAMO_REG_CLOCK_RISC2 = 0x0022, /* 3365 only? */
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GLAMO_REG_CLOCK_MPEG = 0x0024,
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GLAMO_REG_CLOCK_MPROC = 0x0026,
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GLAMO_REG_CLOCK_GEN5_1 = 0x0030,
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GLAMO_REG_CLOCK_GEN5_2 = 0x0032,
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GLAMO_REG_CLOCK_GEN6 = 0x0034,
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GLAMO_REG_CLOCK_GEN7 = 0x0036,
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GLAMO_REG_CLOCK_GEN8 = 0x0038,
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GLAMO_REG_CLOCK_GEN9 = 0x003a,
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GLAMO_REG_CLOCK_GEN10 = 0x003c,
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GLAMO_REG_CLOCK_GEN11 = 0x003e,
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GLAMO_REG_PLL_GEN1 = 0x0040,
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GLAMO_REG_PLL_GEN2 = 0x0042,
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GLAMO_REG_PLL_GEN3 = 0x0044,
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GLAMO_REG_PLL_GEN4 = 0x0046,
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GLAMO_REG_PLL_GEN5 = 0x0048,
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GLAMO_REG_GPIO_GEN1 = 0x0050,
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GLAMO_REG_GPIO_GEN2 = 0x0052,
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GLAMO_REG_GPIO_GEN3 = 0x0054,
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GLAMO_REG_GPIO_GEN4 = 0x0056,
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GLAMO_REG_GPIO_GEN5 = 0x0058,
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GLAMO_REG_GPIO_GEN6 = 0x005a,
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GLAMO_REG_GPIO_GEN7 = 0x005c,
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GLAMO_REG_GPIO_GEN8 = 0x005e,
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GLAMO_REG_GPIO_GEN9 = 0x0060,
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GLAMO_REG_GPIO_GEN10 = 0x0062,
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GLAMO_REG_DFT_GEN1 = 0x0070,
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GLAMO_REG_DFT_GEN2 = 0x0072,
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GLAMO_REG_DFT_GEN3 = 0x0074,
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GLAMO_REG_DFT_GEN4 = 0x0076,
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GLAMO_REG_PLL_GEN6 = 0x01e0,
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GLAMO_REG_PLL_GEN7 = 0x01f0,
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};
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enum glamo_reg_mem_dram1 {
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GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),
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GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
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};
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enum glamo_reg_mem_dram2 {
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GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12),
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};
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enum glamo_reg_clock51 {
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GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001,
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GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002,
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GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004,
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GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008,
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GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010,
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GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020,
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GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040,
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GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080,
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/* FIXME: higher bits */
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};
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enum glamo_reg_hostbus2 {
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GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001,
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GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002,
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GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004,
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GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008,
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GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010,
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GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020,
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GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040,
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GLAMO_HOSTBUS2_MMIO_EN_CQ = 0x0080,
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GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100,
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GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200,
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GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400,
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};
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#define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2))
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#define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x))
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#define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2))
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enum glamo_register_mem {
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GLAMO_REG_MEM_TYPE = REG_MEM(0x00),
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GLAMO_REG_MEM_GEN = REG_MEM(0x02),
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GLAMO_REG_MEM_TIMING1 = REG_MEM(0x04),
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GLAMO_REG_MEM_TIMING2 = REG_MEM(0x06),
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GLAMO_REG_MEM_TIMING3 = REG_MEM(0x08),
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GLAMO_REG_MEM_TIMING4 = REG_MEM(0x0a),
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GLAMO_REG_MEM_TIMING5 = REG_MEM(0x0c),
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GLAMO_REG_MEM_TIMING6 = REG_MEM(0x0e),
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GLAMO_REG_MEM_TIMING7 = REG_MEM(0x10),
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GLAMO_REG_MEM_TIMING8 = REG_MEM(0x12),
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GLAMO_REG_MEM_TIMING9 = REG_MEM(0x14),
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GLAMO_REG_MEM_TIMING10 = REG_MEM(0x16),
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GLAMO_REG_MEM_TIMING11 = REG_MEM(0x18),
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GLAMO_REG_MEM_POWER1 = REG_MEM(0x1a),
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GLAMO_REG_MEM_POWER2 = REG_MEM(0x1c),
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GLAMO_REG_MEM_LCD_BUF1 = REG_MEM(0x1e),
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GLAMO_REG_MEM_LCD_BUF2 = REG_MEM(0x20),
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GLAMO_REG_MEM_LCD_BUF3 = REG_MEM(0x22),
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GLAMO_REG_MEM_LCD_BUF4 = REG_MEM(0x24),
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GLAMO_REG_MEM_BIST1 = REG_MEM(0x26),
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GLAMO_REG_MEM_BIST2 = REG_MEM(0x28),
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GLAMO_REG_MEM_BIST3 = REG_MEM(0x2a),
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GLAMO_REG_MEM_BIST4 = REG_MEM(0x2c),
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GLAMO_REG_MEM_BIST5 = REG_MEM(0x2e),
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GLAMO_REG_MEM_MAH1 = REG_MEM(0x30),
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GLAMO_REG_MEM_MAH2 = REG_MEM(0x32),
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GLAMO_REG_MEM_DRAM1 = REG_MEM(0x34),
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GLAMO_REG_MEM_DRAM2 = REG_MEM(0x36),
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GLAMO_REG_MEM_CRC = REG_MEM(0x38),
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};
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enum glamo_irq {
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GLAMO_IRQ_HOSTBUS = 0x0001,
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GLAMO_IRQ_JPEG = 0x0002,
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GLAMO_IRQ_MPEG = 0x0004,
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GLAMO_IRQ_MPROC1 = 0x0008,
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GLAMO_IRQ_MPROC0 = 0x0010,
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GLAMO_IRQ_CMDQUEUE = 0x0020,
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GLAMO_IRQ_2D = 0x0040,
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GLAMO_IRQ_MMC = 0x0080,
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GLAMO_IRQ_RISC = 0x0100,
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};
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enum glamo_reg_clock_host {
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GLAMO_CLOCK_HOST_DG_BCLK = 0x0001,
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GLAMO_CLOCK_HOST_DG_M0CLK = 0x0004,
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GLAMO_CLOCK_HOST_RESET = 0x1000,
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};
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enum glamo_reg_clock_mem {
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GLAMO_CLOCK_MEM_DG_M1CLK = 0x0001,
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GLAMO_CLOCK_MEM_EN_M1CLK = 0x0002,
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GLAMO_CLOCK_MEM_DG_MOCACLK = 0x0004,
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GLAMO_CLOCK_MEM_EN_MOCACLK = 0x0008,
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GLAMO_CLOCK_MEM_RESET = 0x1000,
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GLAMO_CLOCK_MOCA_RESET = 0x2000,
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};
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enum glamo_reg_clock_lcd {
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GLAMO_CLOCK_LCD_DG_DCLK = 0x0001,
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GLAMO_CLOCK_LCD_EN_DCLK = 0x0002,
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GLAMO_CLOCK_LCD_DG_DMCLK = 0x0004,
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GLAMO_CLOCK_LCD_EN_DMCLK = 0x0008,
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//
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GLAMO_CLOCK_LCD_EN_DHCLK = 0x0020,
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GLAMO_CLOCK_LCD_DG_M5CLK = 0x0040,
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GLAMO_CLOCK_LCD_EN_M5CLK = 0x0080,
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GLAMO_CLOCK_LCD_RESET = 0x1000,
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};
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enum glamo_reg_clock_mmc {
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GLAMO_CLOCK_MMC_DG_TCLK = 0x0001,
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GLAMO_CLOCK_MMC_EN_TCLK = 0x0002,
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GLAMO_CLOCK_MMC_DG_M9CLK = 0x0004,
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GLAMO_CLOCK_MMC_EN_M9CLK = 0x0008,
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GLAMO_CLOCK_MMC_RESET = 0x1000,
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};
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enum glamo_reg_clock_isp {
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GLAMO_CLOCK_ISP_DG_I1CLK = 0x0001,
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GLAMO_CLOCK_ISP_EN_I1CLK = 0x0002,
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GLAMO_CLOCK_ISP_DG_CCLK = 0x0004,
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GLAMO_CLOCK_ISP_EN_CCLK = 0x0008,
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//
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GLAMO_CLOCK_ISP_EN_SCLK = 0x0020,
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GLAMO_CLOCK_ISP_DG_M2CLK = 0x0040,
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GLAMO_CLOCK_ISP_EN_M2CLK = 0x0080,
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GLAMO_CLOCK_ISP_DG_M15CLK = 0x0100,
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GLAMO_CLOCK_ISP_EN_M15CLK = 0x0200,
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GLAMO_CLOCK_ISP1_RESET = 0x1000,
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GLAMO_CLOCK_ISP2_RESET = 0x2000,
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};
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enum glamo_reg_clock_jpeg {
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GLAMO_CLOCK_JPEG_DG_JCLK = 0x0001,
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GLAMO_CLOCK_JPEG_EN_JCLK = 0x0002,
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GLAMO_CLOCK_JPEG_DG_M3CLK = 0x0004,
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GLAMO_CLOCK_JPEG_EN_M3CLK = 0x0008,
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GLAMO_CLOCK_JPEG_RESET = 0x1000,
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};
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enum glamo_reg_clock_3d {
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GLAMO_CLOCK_3D_DG_GCLK = 0x0001,
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GLAMO_CLOCK_3D_EN_GCLK = 0x0002,
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GLAMO_CLOCK_3D_DG_M7CLK = 0x0004,
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GLAMO_CLOCK_3D_EN_M7CLK = 0x0008,
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GLAMO_CLOCK_3D_DG_M6CLK = 0x0010,
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GLAMO_CLOCK_3D_EN_M6CLK = 0x0020,
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GLAMO_CLOCK_3D_2D_RESET = 0x1000,
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GLAMO_CLOCK_3D_CQ_RESET = 0x2000,
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};
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enum glamo_reg_clock_mpeg {
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GLAMO_CLOCK_MPEG_DG_X0CLK = 0x0001,
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GLAMO_CLOCK_MPEG_EN_X0CLK = 0x0002,
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GLAMO_CLOCK_MPEG_DG_X1CLK = 0x0004,
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GLAMO_CLOCK_MPEG_EN_X1CLK = 0x0008,
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GLAMO_CLOCK_MPEG_DG_X2CLK = 0x0010,
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GLAMO_CLOCK_MPEG_EN_X2CLK = 0x0020,
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GLAMO_CLOCK_MPEG_DG_X3CLK = 0x0040,
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GLAMO_CLOCK_MPEG_EN_X3CLK = 0x0080,
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GLAMO_CLOCK_MPEG_DG_X4CLK = 0x0100,
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GLAMO_CLOCK_MPEG_EN_X4CLK = 0x0200,
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GLAMO_CLOCK_MPEG_DG_X6CLK = 0x0400,
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GLAMO_CLOCK_MPEG_EN_X6CLK = 0x0800,
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GLAMO_CLOCK_MPEG_ENC_RESET = 0x1000,
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GLAMO_CLOCK_MPEG_DEC_RESET = 0x2000,
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};
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/* LCD Controller */
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#define REG_LCD(x) (x)
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enum glamo_reg_lcd {
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GLAMO_REG_LCD_MODE1 = REG_LCD(0x00),
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GLAMO_REG_LCD_MODE2 = REG_LCD(0x02),
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GLAMO_REG_LCD_MODE3 = REG_LCD(0x04),
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GLAMO_REG_LCD_WIDTH = REG_LCD(0x06),
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GLAMO_REG_LCD_HEIGHT = REG_LCD(0x08),
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GLAMO_REG_LCD_POLARITY = REG_LCD(0x0a),
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GLAMO_REG_LCD_A_BASE1 = REG_LCD(0x0c),
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GLAMO_REG_LCD_A_BASE2 = REG_LCD(0x0e),
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GLAMO_REG_LCD_B_BASE1 = REG_LCD(0x10),
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GLAMO_REG_LCD_B_BASE2 = REG_LCD(0x12),
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GLAMO_REG_LCD_C_BASE1 = REG_LCD(0x14),
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GLAMO_REG_LCD_C_BASE2 = REG_LCD(0x16),
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GLAMO_REG_LCD_PITCH = REG_LCD(0x18),
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/* RES */
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GLAMO_REG_LCD_HORIZ_TOTAL = REG_LCD(0x1c),
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/* RES */
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GLAMO_REG_LCD_HORIZ_RETR_START = REG_LCD(0x20),
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/* RES */
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GLAMO_REG_LCD_HORIZ_RETR_END = REG_LCD(0x24),
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/* RES */
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GLAMO_REG_LCD_HORIZ_DISP_START = REG_LCD(0x28),
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/* RES */
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GLAMO_REG_LCD_HORIZ_DISP_END = REG_LCD(0x2c),
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/* RES */
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GLAMO_REG_LCD_VERT_TOTAL = REG_LCD(0x30),
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/* RES */
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GLAMO_REG_LCD_VERT_RETR_START = REG_LCD(0x34),
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/* RES */
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GLAMO_REG_LCD_VERT_RETR_END = REG_LCD(0x38),
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/* RES */
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GLAMO_REG_LCD_VERT_DISP_START = REG_LCD(0x3c),
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/* RES */
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GLAMO_REG_LCD_VERT_DISP_END = REG_LCD(0x40),
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/* RES */
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GLAMO_REG_LCD_POL = REG_LCD(0x44),
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GLAMO_REG_LCD_DATA_START = REG_LCD(0x46),
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GLAMO_REG_LCD_FRATE_CONTRO = REG_LCD(0x48),
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GLAMO_REG_LCD_DATA_CMD_HDR = REG_LCD(0x4a),
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GLAMO_REG_LCD_SP_START = REG_LCD(0x4c),
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GLAMO_REG_LCD_SP_END = REG_LCD(0x4e),
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GLAMO_REG_LCD_CURSOR_BASE1 = REG_LCD(0x50),
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GLAMO_REG_LCD_CURSOR_BASE2 = REG_LCD(0x52),
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GLAMO_REG_LCD_CURSOR_PITCH = REG_LCD(0x54),
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GLAMO_REG_LCD_CURSOR_X_SIZE = REG_LCD(0x56),
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GLAMO_REG_LCD_CURSOR_Y_SIZE = REG_LCD(0x58),
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GLAMO_REG_LCD_CURSOR_X_POS = REG_LCD(0x5a),
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GLAMO_REG_LCD_CURSOR_Y_POS = REG_LCD(0x5c),
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GLAMO_REG_LCD_CURSOR_PRESET = REG_LCD(0x5e),
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GLAMO_REG_LCD_CURSOR_FG_COLOR = REG_LCD(0x60),
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/* RES */
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GLAMO_REG_LCD_CURSOR_BG_COLOR = REG_LCD(0x64),
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/* RES */
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GLAMO_REG_LCD_CURSOR_DST_COLOR = REG_LCD(0x68),
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/* RES */
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GLAMO_REG_LCD_STATUS1 = REG_LCD(0x80),
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GLAMO_REG_LCD_STATUS2 = REG_LCD(0x82),
|
||||
GLAMO_REG_LCD_STATUS3 = REG_LCD(0x84),
|
||||
GLAMO_REG_LCD_STATUS4 = REG_LCD(0x86),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_COMMAND1 = REG_LCD(0xa0),
|
||||
GLAMO_REG_LCD_COMMAND2 = REG_LCD(0xa2),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_WFORM_DELAY1 = REG_LCD(0xb0),
|
||||
GLAMO_REG_LCD_WFORM_DELAY2 = REG_LCD(0xb2),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_GAMMA_CORR = REG_LCD(0x100),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_GAMMA_R_ENTRY01 = REG_LCD(0x110),
|
||||
GLAMO_REG_LCD_GAMMA_R_ENTRY23 = REG_LCD(0x112),
|
||||
GLAMO_REG_LCD_GAMMA_R_ENTRY45 = REG_LCD(0x114),
|
||||
GLAMO_REG_LCD_GAMMA_R_ENTRY67 = REG_LCD(0x116),
|
||||
GLAMO_REG_LCD_GAMMA_R_ENTRY8 = REG_LCD(0x118),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_GAMMA_G_ENTRY01 = REG_LCD(0x130),
|
||||
GLAMO_REG_LCD_GAMMA_G_ENTRY23 = REG_LCD(0x132),
|
||||
GLAMO_REG_LCD_GAMMA_G_ENTRY45 = REG_LCD(0x134),
|
||||
GLAMO_REG_LCD_GAMMA_G_ENTRY67 = REG_LCD(0x136),
|
||||
GLAMO_REG_LCD_GAMMA_G_ENTRY8 = REG_LCD(0x138),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_GAMMA_B_ENTRY01 = REG_LCD(0x150),
|
||||
GLAMO_REG_LCD_GAMMA_B_ENTRY23 = REG_LCD(0x152),
|
||||
GLAMO_REG_LCD_GAMMA_B_ENTRY45 = REG_LCD(0x154),
|
||||
GLAMO_REG_LCD_GAMMA_B_ENTRY67 = REG_LCD(0x156),
|
||||
GLAMO_REG_LCD_GAMMA_B_ENTRY8 = REG_LCD(0x158),
|
||||
/* RES */
|
||||
GLAMO_REG_LCD_SRAM_DRIVING1 = REG_LCD(0x160),
|
||||
GLAMO_REG_LCD_SRAM_DRIVING2 = REG_LCD(0x162),
|
||||
GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164),
|
||||
};
|
||||
|
||||
|
||||
enum glamo_reg_lcd_mode1 {
|
||||
GLAMO_LCD_MODE1_PWRSAVE = 0x0001,
|
||||
GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002,
|
||||
GLAMO_LCD_MODE1_HWFLIP = 0x0004,
|
||||
GLAMO_LCD_MODE1_LCD2 = 0x0008,
|
||||
/* RES */
|
||||
GLAMO_LCD_MODE1_PARTIAL_MODE = 0x0020,
|
||||
GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
|
||||
GLAMO_LCD_MODE1_PARTIAL_ENABLE = 0x0080,
|
||||
GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
|
||||
GLAMO_LCD_MODE1_HSYNC_HIGH_ACT = 0x0200,
|
||||
GLAMO_LCD_MODE1_VSYNC_HIGH_ACT = 0x0400,
|
||||
GLAMO_LCD_MODE1_HSYNC_FLIP = 0x0800,
|
||||
GLAMO_LCD_MODE1_GAMMA_COR_EN = 0x1000,
|
||||
GLAMO_LCD_MODE1_DITHER_EN = 0x2000,
|
||||
GLAMO_LCD_MODE1_CURSOR_EN = 0x4000,
|
||||
GLAMO_LCD_MODE1_ROTATE_EN = 0x8000,
|
||||
};
|
||||
|
||||
enum glamo_reg_lcd_mode2 {
|
||||
GLAMO_LCD_MODE2_CRC_CHECK_EN = 0x0001,
|
||||
GLAMO_LCD_MODE2_DCMD_PER_LINE = 0x0002,
|
||||
GLAMO_LCD_MODE2_NOUSE_BDEF = 0x0004,
|
||||
GLAMO_LCD_MODE2_OUT_POS_MODE = 0x0008,
|
||||
GLAMO_LCD_MODE2_FRATE_CTRL_EN = 0x0010,
|
||||
GLAMO_LCD_MODE2_SINGLE_BUFFER = 0x0020,
|
||||
GLAMO_LCD_MODE2_SER_LSB_TO_MSB = 0x0040,
|
||||
/* FIXME */
|
||||
};
|
||||
|
||||
enum glamo_reg_lcd_mode3 {
|
||||
/* LCD color source data format */
|
||||
GLAMO_LCD_SRC_RGB565 = 0x0000,
|
||||
GLAMO_LCD_SRC_ARGB1555 = 0x4000,
|
||||
GLAMO_LCD_SRC_ARGB4444 = 0x8000,
|
||||
/* interface type */
|
||||
GLAMO_LCD_MODE3_LCD = 0x1000,
|
||||
GLAMO_LCD_MODE3_RGB = 0x0800,
|
||||
GLAMO_LCD_MODE3_CPU = 0x0000,
|
||||
/* mode */
|
||||
GLAMO_LCD_MODE3_RGB332 = 0x0000,
|
||||
GLAMO_LCD_MODE3_RGB444 = 0x0100,
|
||||
GLAMO_LCD_MODE3_RGB565 = 0x0200,
|
||||
GLAMO_LCD_MODE3_RGB666 = 0x0300,
|
||||
/* depth */
|
||||
GLAMO_LCD_MODE3_6BITS = 0x0000,
|
||||
GLAMO_LCD_MODE3_8BITS = 0x0010,
|
||||
GLAMO_LCD_MODE3_9BITS = 0x0020,
|
||||
GLAMO_LCD_MODE3_16BITS = 0x0030,
|
||||
GLAMO_LCD_MODE3_18BITS = 0x0040,
|
||||
};
|
||||
|
||||
enum glamo_lcd_cmd_type {
|
||||
GLAMO_LCD_CMD_TYPE_DISP = 0x0000,
|
||||
GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000,
|
||||
GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000,
|
||||
GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
|
||||
};
|
||||
#define GLAMO_LCD_CMD_TYPE_MASK 0xc000
|
||||
|
||||
enum glamo_lcd_cmds {
|
||||
GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00,
|
||||
GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */
|
||||
/* switch to command mode, no display */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
|
||||
/* display until VSYNC, switch to command */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11,
|
||||
/* display until HSYNC, switch to command */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12,
|
||||
/* display until VSYNC, 1 black frame, VSYNC, switch to command */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
|
||||
/* don't care about display and switch to command */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */
|
||||
/* don't care about display, keep data display but disable data,
|
||||
* and switch to command */
|
||||
GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */
|
||||
};
|
||||
|
||||
enum glamo_reg_clock_2d {
|
||||
GLAMO_CLOCK_2D_DG_GCLK = 0x0001,
|
||||
GLAMO_CLOCK_2D_EN_GCLK = 0x0002,
|
||||
GLAMO_CLOCK_2D_DG_M7CLK = 0x0004,
|
||||
GLAMO_CLOCK_2D_EN_M7CLK = 0x0008,
|
||||
GLAMO_CLOCK_2D_DG_M6CLK = 0x0010,
|
||||
GLAMO_CLOCK_2D_EN_M6CLK = 0x0020,
|
||||
GLAMO_CLOCK_2D_RESET = 0x1000,
|
||||
GLAMO_CLOCK_2D_CQ_RESET = 0x2000,
|
||||
};
|
||||
|
||||
#endif /* _GLAMO_REGS_H */
|
||||
103
qiboot/src/drivers/glamo-init.c
Normal file
103
qiboot/src/drivers/glamo-init.c
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* (C) Copyright 2007 by OpenMoko, Inc.
|
||||
* Author: Harald Welte <laforge@openmoko.org>
|
||||
* Andy Green <andy@openmoko.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <qi.h>
|
||||
#include <glamo-regs.h>
|
||||
|
||||
#define GLAMO_REG(x) (*(volatile unsigned short *)(0x08000000 + x))
|
||||
|
||||
static void glamo_reg_write(u16 reg, u16 val)
|
||||
{
|
||||
GLAMO_REG(reg) = val;
|
||||
}
|
||||
|
||||
static u16 glamo_reg_read(u16 reg)
|
||||
{
|
||||
return GLAMO_REG(reg);
|
||||
}
|
||||
|
||||
|
||||
static u16 u16a_gen_init_0x0000[] = {
|
||||
0x2020, 0x3650, 0x0002, 0x01FF, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x000D, 0x000B, 0x00EE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x1839, 0x0000, 0x2000, 0x0001, 0x0100, 0x0000, 0x0000, 0x0000,
|
||||
0x05DB, 0x5231, 0x09C3, 0x8261, 0x0003, 0x0000, 0x0000, 0x0000,
|
||||
0x000F, 0x101E, 0xC0C3, 0x101E, 0x000F, 0x0001, 0x030F, 0x020F,
|
||||
0x080F, 0x0F0F
|
||||
};
|
||||
|
||||
static u16 u16a_gen_init_0x0200[] = {
|
||||
0x0EF0, 0x07FF, 0x0000, 0x0080, 0x0344, 0x0600, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x4000, 0xF00E, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
|
||||
0x0873, 0xAFAF, 0x0108, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x1002, 0x6006, 0x00FF, 0x0001, 0x0020, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x3210, 0x5432, 0xE100, 0x01D6
|
||||
};
|
||||
|
||||
|
||||
void glamo_core_init(void)
|
||||
{
|
||||
int bp;
|
||||
|
||||
/* power up PLL1 and PLL2 */
|
||||
glamo_reg_write(GLAMO_REG_PLL_GEN7, 0x0000);
|
||||
glamo_reg_write(GLAMO_REG_PLL_GEN3, 0x0400);
|
||||
|
||||
/* enable memory clock and get it out of deep pwrdown */
|
||||
glamo_reg_write(GLAMO_REG_CLOCK_MEMORY,
|
||||
glamo_reg_read(GLAMO_REG_CLOCK_MEMORY) | 8);
|
||||
glamo_reg_write(GLAMO_REG_MEM_DRAM2,
|
||||
glamo_reg_read(GLAMO_REG_MEM_DRAM2) & (~(1 << 12)));
|
||||
glamo_reg_write(GLAMO_REG_MEM_DRAM1,
|
||||
glamo_reg_read(GLAMO_REG_MEM_DRAM1) & (~(1 << 12)));
|
||||
/*
|
||||
* we just fill up the general hostbus and LCD register sets
|
||||
* with magic values taken from the Linux framebuffer init action
|
||||
*/
|
||||
for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0000); bp++)
|
||||
glamo_reg_write(0x0 | (bp << 1),
|
||||
u16a_gen_init_0x0000[bp]);
|
||||
|
||||
for (bp = 0; bp < ARRAY_SIZE(u16a_gen_init_0x0200); bp++)
|
||||
glamo_reg_write(0x200 | (bp << 1),
|
||||
u16a_gen_init_0x0200[bp]);
|
||||
|
||||
/* spin until PLL1 lock */
|
||||
while (!(glamo_reg_read(GLAMO_REG_PLL_GEN5) & 1))
|
||||
;
|
||||
}
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#include <ports-s3c24xx.h>
|
||||
#include <i2c-bitbang-s3c24xx.h>
|
||||
#include <pcf50633.h>
|
||||
#include <glamo-init.h>
|
||||
|
||||
#define GTA02_DEBUG_UART 2
|
||||
|
||||
@ -197,6 +198,12 @@ void port_init_gta02(void)
|
||||
/* configure MPLL */
|
||||
*MPLLCON = ((42 << 12) + (1 << 4) + 0);
|
||||
|
||||
/* we're going to use Glamo for SD Card access, so we need to init the
|
||||
* evil beast
|
||||
*/
|
||||
glamo_core_init();
|
||||
|
||||
/* get debug UART working at 115kbps */
|
||||
serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 50 /* 50MHz PCLK */);
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user