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add jz4760 support to xburst_stage1

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Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
Xiangfu Liu 2010-06-18 14:33:47 +08:00
parent 046a7e7cbd
commit bcc23ae567
9 changed files with 3450 additions and 1124 deletions
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11
usbboot/xburst_include/target/configs.h
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@ -25,6 +25,7 @@
/* Once your system configration change, just modify the file */
#include "target/xburst_types.h"
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
/* SDRAM Timings, unit: ns */
@ -34,7 +35,6 @@
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
extern volatile u32 CPU_ID;
extern volatile u8 SDRAM_BW16;
extern volatile u8 SDRAM_BANK4;
@ -48,13 +48,4 @@ extern volatile u32 CONFIG_BAUDRATE;
extern volatile u32 UART_BASE;
extern volatile u8 CONFIG_MOBILE_SDRAM;
extern volatile u8 IS_SHARE;
extern void gpio_init_4740(void);
extern void sdram_init_4740(void);
extern void pll_init_4740(void);
extern void gpio_init_4760(void);
extern void sdram_init_4760(void);
extern void pll_init_4760(void);
#endif

2821
usbboot/xburst_include/target/jz4750.h → usbboot/xburst_include/target/jz4760.h
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File diff suppressed because it is too large Load Diff

2
usbboot/xburst_stage1/Makefile
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@ -18,7 +18,7 @@ CFLAGS := -O2 -fno-unit-at-a-time -fno-zero-initialized-in-bss -mips32 -fno-pic
-mno-abicalls -I$(INFLASH_SRC_PATH) -I$(XBURST_INCLUDE_PATH)
LDFLAGS := -nostdlib -EL -T target.ld
OBJS = head.o main.o common.o board_4740.o board_4750.o debug.o
OBJS = head.o main.o common.o board_4740.o board-jz4760.o debug.o
all: xburst_stage1.bin

1263
usbboot/xburst_stage1/board-jz4760.c Normal file
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File diff suppressed because it is too large Load Diff

165
usbboot/xburst_stage1/board-jz4760.h Normal file
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@ -0,0 +1,165 @@
/*
* JZ4760 board definitions.
*
* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
*/
#ifndef __BOARD_JZ4760_H__
#define __BOARD_JZ4760_H__
//#define DEBUG
//#define CONFIG_FPGA
//#define CFG_DIV 2 /* for FPGA */
#define CFG_EXTAL 12000000
#define CFG_CPU_SPEED 144000000 /* CPU clock */
#define CONFIG_DDRC
#define CONFIG_SDRAM_DDR2
//#define CONFIG_SDRAM_MDDR
//#define CONFIG_SDRAM_DDR1
//#define CONFIG_MOBILE_SDRAM
#if (!defined(CONFIG_SDRAM_MDDR) && !defined(CONFIG_SDRAM_DDR1) && !defined(CONFIG_SDRAM_DDR2))
/*-----------------------------------------------------------------------
* SDRAM Info.
*/
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
#ifndef CONFIG_MOBILE_SDRAM
// SDRAM paramters
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 9 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
// SDRAM Timings, unit: ns
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */
#else /* Mobile SDRAM */
// SDRAM paramters
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 9 /* Column address: 8 to 12 */
#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
// SDRAM Timings, unit: ns
#define SDRAM_TRAS 50 /* RAS# Active Time */
#define SDRAM_RCD 18 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 7812 /* Refresh period: 4096 refresh cycles/64ms */
#endif /* CONFIG_MOBILE_SDRAM */
#else /* CONFIG_DDRC */
/*--------------------------------------------------------------------------------
* DDR2 info
*/
/* Chip Select */
#define DDR_CS1EN 0 // CSEN : whether a ddr chip exists 0 - un-used, 1 - used
#define DDR_CS0EN 1
#define DDR_DW32 1 /* 0 - 16-bit data width, 1 - 32-bit data width */
/* SDRAM paramters */
#if defined(CONFIG_SDRAM_DDR2) // ddr2
#define DDR_ROW 13 /* ROW : 12 to 14 row address */
#define DDR_COL 10 /* COL : 8 to 10 column address */
#define DDR_BANK8 1 /* Banks each chip: 0-4bank, 1-8bank */
#define DDR_CL 3 /* CAS latency: 1 to 7 */
/*
* ddr2 controller timing1 register
*/
#define DDR_tRAS 45 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */
#define DDR_tRTP 8 /* 7.5ns READ to PRECHARGE command period. */
#define DDR_tRP 42 /* tRP: PRECHARGE command period to the same bank */
#define DDR_tRCD 42 /* ACTIVE to READ or WRITE command period to the same bank. */
#define DDR_tRC 60 /* ACTIVE to ACTIVE command period to the same bank.*/
#define DDR_tRRD 8 /* ACTIVE bank A to ACTIVE bank B command period. */
#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */
#define DDR_tWTR 2 /* unit: tCK. WRITE to READ command delay. */
/*
* ddr2 controller timing2 register
*/
#define DDR_tRFC 128 /* ns, AUTO-REFRESH command period. */
#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */
#define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */
#define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */
/*
* ddr2 controller refcnt register
*/
#define DDR_tREFI 7800 /* Refresh period: ns */
#elif defined(CONFIG_SDRAM_MDDR) // ddr1 and mddr
#define DDR_ROW 14 /* ROW : 12 to 14 row address */
#define DDR_COL 10 /* COL : 8 to 10 column address */
#define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */
#define DDR_CL 3 /* CAS latency: 1 to 7 */
/*
* ddr2 controller timing1 register
*/
#define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */
#define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */
#define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */
#define DDR_tRCD 20 /* ACTIVE to READ or WRITE command period to the same bank. */
#define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/
#define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */
#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */
#define DDR_tWTR 2 /* WRITE to READ command delay. */
/*
* ddr2 controller timing2 register
*/
#define DDR_tRFC 90 /* ns, AUTO-REFRESH command period. */
#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */
#define DDR_tXP 1 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */
#define DDR_tMRD 2 /* unit: tCK Load-Mode-Register to next valid command period: 1 to 4 tCK */
/*
* ddr2 controller refcnt register
*/
#define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */
#elif defined(CONFIG_SDRAM_DDR1) // ddr1 and mddr
#define DDR_ROW 13 /* ROW : 12 to 14 row address */
#define DDR_COL 10 /* COL : 8 to 10 column address */
#define DDR_BANK8 0 /* Banks each chip: 0-4bank, 1-8bank */
#define DDR_CL 3 /* CAS latency: 1 to 7 */
#define DDR_CL_HALF 0 /*Only for DDR1, Half CAS latency: 0 or 1 */
/*
* ddr2 controller timing1 register
*/
#define DDR_tRAS 40 /*tRAS: ACTIVE to PRECHARGE command period to the same bank. */
#define DDR_tRTP 12 /* 7.5ns READ to PRECHARGE command period. */
#define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank */
#define DDR_tRCD 15 /* ACTIVE to READ or WRITE command period to the same bank. */
#define DDR_tRC 55 /* ACTIVE to ACTIVE command period to the same bank.*/
#define DDR_tRRD 10 /* ACTIVE bank A to ACTIVE bank B command period. */
#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory */
#define DDR_tWTR 2 /* WRITE to READ command delay 2*tCK */
/*
* ddr2 controller timing2 register
*/
#define DDR_tRFC 70 /* ns, AUTO-REFRESH command period. */
#define DDR_tMINSR 6 /* Minimum Self-Refresh / Deep-Power-Down */
#define DDR_tXP 2 /* EXIT-POWER-DOWN to next valid command period: 1 to 8 tCK. */
#define DDR_tMRD 2 /* unit: tCK. Load-Mode-Register to next valid command period: 1 to 4 tCK */
/*
* ddr2 controller refcnt register
*/
#define DDR_tREFI 7800 /* Refresh period: 4096 refresh cycles/64ms */
#endif
#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh
* cnt_clk = memclk/(16*(2^DDR_CLK_DIV))
*/
#endif /* CONFIG_DDRC */
#endif /* __BOARD_JZ4760_H__ */

228
usbboot/xburst_stage1/board_4750.c
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@ -1,228 +0,0 @@
/*
* Board init routines.
*
* Copyright 2009 (C) Qi Hardware Inc.,
* Author: Xiangfu Liu <xiangfu@qi-hardware.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 3 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA
*/
#include <stdint.h>
#include "target/jz4750.h"
#include "target/configs.h"
void gpio_init_4750(void)
{
__gpio_as_sdram_32bit();
__gpio_as_uart1();
__gpio_as_uart0();
__gpio_as_uart2();
__gpio_as_uart3();
__gpio_as_nand_8bit();
}
void ccpll_init_4750(void)
{
register unsigned int cfcr, plcr1;
int n2FR[33] = {
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
9
};
// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
int nf, pllout2;
cfcr = ~CPM_CPCCR_ECS &
(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
CPM_CPPCR_PLLEN; /* enable PLL */
/* init PLL */
REG_CPM_CPCCR = cfcr;
REG_CPM_CPPCR = plcr1;
}
int nf, pllout2;
void pll_init_4750(void)
{
register unsigned int cfcr, plcr1,tmp;
int n2FR[33] = {
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
9
};
int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
cfcr = CPM_CPCCR_PCS |
(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
if (CFG_EXTAL > 16000000)
cfcr |= CPM_CPCCR_ECS;
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
/* Init USB Host clock, pllout2 must be n*48MHz */
// REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
CPM_CPPCR_PLLEN; /* enable PLL */
cfcr |= CPM_CPCCR_UCS; /* set PLL as UDC PHY*/
tmp = pllout2 / 1000000 / 12 - 1;
cfcr |= (tmp << CPM_CPCCR_UDIV_BIT); /* set UDC DIV*/
/* init PLL */
REG_CPM_CPCCR = cfcr;
REG_CPM_CPPCR = plcr1;
}
void sdram_init_4750(void)
{
register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
register unsigned int sdemode; /*SDRAM Extended Mode*/
unsigned int cas_latency_sdmr[2] = {
EMC_SDMR_CAS_2,
EMC_SDMR_CAS_3,
};
unsigned int cas_latency_dmcr[2] = {
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
};
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
cpu_clk = CFG_CPU_SPEED;
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
/* set REG_EMC_DMAR0 for supporting 128MB sdram on DCS0 */
REG_EMC_DMAR0 = EMC_DMAR0_BASE | EMC_DMAR_MASK_128_128;
REG_EMC_BCR = 0; /* Disable bus release */
REG_EMC_RTCSR = 0; /* Disable clock for counting */
/* Basic DMCR value */
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
EMC_DMCR_EPIN |
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
/* SDRAM timimg */
ns = 1000000000 / mem_clk;
tmp = SDRAM_TRAS/ns;
if (tmp < 4) tmp = 4;
if (tmp > 11) tmp = 11;
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
tmp = SDRAM_RCD/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
tmp = SDRAM_TPC/ns;
if (tmp > 7) tmp = 7;
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
tmp = SDRAM_TRWL/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
if (tmp > 14) tmp = 14;
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
/* SDRAM mode value */
sdmode = EMC_SDMR_BT_SEQ |
EMC_SDMR_OM_NORMAL |
EMC_SDMR_BL_4 |
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
REG_EMC_DMCR = dmcr;
REG8(EMC_SDMR0|sdmode) = 0;
if (CONFIG_MOBILE_SDRAM == 1)
/* Mobile SDRAM Extended Mode Register */
sdemode = EMC_SDMR_SET_BA1 | EMC_SDMR_DS_FULL | EMC_SDMR_PRSR_ALL;
/* Wait for precharge, > 200us */
tmp = (cpu_clk / 1000000) * 1000;
while (tmp--);
/* Stage 2. Enable auto-refresh */
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
tmp = SDRAM_TREF/ns;
tmp = tmp/64 + 1;
if (tmp > 0xff) tmp = 0xff;
REG_EMC_RTCOR = tmp;
REG_EMC_RTCNT = 0;
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
/* Wait for number of auto-refresh cycles */
tmp = (cpu_clk / 1000000) * 1000;
while (tmp--);
/* Stage 3. Mode Register Set */
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET | EMC_DMCR_MBSEL_B0;
REG8(EMC_SDMR0|sdmode) = 0;
if (CONFIG_MOBILE_SDRAM == 1)
REG8(EMC_SDMR0|sdemode) = 0; /* Set Mobile SDRAM Extended Mode Register */
/* Set back to basic DMCR value */
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
/* everything is ok now */
}
void serial_setbrg_4750(void)
{
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
u32 baud_div, tmp;
baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
(CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE);
tmp = *uart_lcr;
tmp |= UART_LCR_DLAB;
*uart_lcr = tmp;
*uart_dlhr = (baud_div >> 8) & 0xff;
*uart_dllr = baud_div & 0xff;
tmp &= ~UART_LCR_DLAB;
*uart_lcr = tmp;
}

2
usbboot/xburst_stage1/common.c
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@ -85,7 +85,7 @@ void serial_init(void)
if ( CPU_ID == 0x4740 )
serial_setbrg_4740();
else
serial_setbrg_4750();
serial_setbrg_4760();
/* Enable UART unit, enable and clear FIFO */
*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;

8
usbboot/xburst_stage1/debug.c
View File

@ -19,7 +19,7 @@
* Boston, MA 02110-1301, USA
*/
#include "target/jz4750.h"
#include "target/jz4760.h"
#include "target/configs.h"
#include "usb_boot_defines.h"
@ -79,10 +79,10 @@ void do_debug()
serial_init();
sdram_init_4740();
break;
case 0x4750:
gpio_init_4750();
case 0x4760:
gpio_init_4760();
serial_init();
sdram_init_4750();
sdram_init_4760();
break;
default:
;

22
usbboot/xburst_stage1/main.c
View File

@ -35,11 +35,11 @@ volatile u32 CFG_CPU_SPEED;
volatile u32 CFG_EXTAL;
volatile u8 PHM_DIV;
volatile u8 IS_SHARE;
extern int pllout2;
#if 0
void test_load_args(void)
{
CPU_ID = 0x4740 ;
CPU_ID = 0x4760;
CFG_EXTAL = 12000000;
CFG_CPU_SPEED = 252000000;
PHM_DIV = 3;
@ -68,8 +68,6 @@ void load_args(void)
CFG_CPU_SPEED = 192000000;
}
PHM_DIV = fw_args->phm_div;
if (fw_args->use_uart > 3)
fw_args->use_uart = 0;
UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000;
CONFIG_BAUDRATE = fw_args->boudrate;
SDRAM_BW16 = fw_args->bus_width;
@ -96,11 +94,12 @@ void c_main(void)
serial_init();
sdram_init_4740();
break;
case 0x4750:
gpio_init_4750();
pll_init_4750();
case 0x4760:
gpio_init_4760();
cpm_start_all_4760();
serial_init();
sdram_init_4750();
pll_init_4760();
sdram_init_4760();
break;
default:
return;
@ -117,8 +116,13 @@ void c_main(void)
serial_put_hex(SDRAM_BANK4);
serial_put_hex(SDRAM_ROW);
serial_put_hex(SDRAM_COL);
serial_put_hex(pllout2);
serial_put_hex(REG_CPM_CPCCR);
#endif
serial_puts("xburst stage1 run finish !\n");
if (CPU_ID == 0x4760) {
__asm__ (
"li $31, 0xbfc012e0 \n\t"
"jr $31 \n\t "
);
}
}