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synced 2024-11-01 08:29:41 +02:00
[xbboot] put all jz4760 board configure to board-jz4760.h file
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@ -138,7 +138,7 @@ void pll_init_4760()
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(n2FR[div[4]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[5]] << CPM_CPCCR_SDIV_BIT);
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if (ARG_EXTAL > 16000000)
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if (CFG_EXTAL > 16000000)
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cfcr |= CPM_CPCCR_ECS;
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else
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cfcr &= ~CPM_CPCCR_ECS;
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@ -151,7 +151,7 @@ void pll_init_4760()
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#endif
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cfcr |= CPM_CPCCR_CE;
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plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL);
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plcr1 = pll_calc_m_n_od(CFG_CPU_SPEED, CFG_EXTAL);
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plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */
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| CPM_CPPCR_PLLEN; /* enable PLL */
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@ -338,7 +338,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) {
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int channel;
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#ifndef CONFIG_DDRC
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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@ -352,7 +352,7 @@ static int dma_memcpy_test(int channle_0, int channle_1) {
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DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = CFG_CPU_SPEED;
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// for(channel = 0; channel < MAX_DMA_NUM; channel++) {
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@ -465,7 +465,7 @@ static int ddr_dma_test(int print_flag) {
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REG_DMAC_DMADCKE(1) = 0x3f;
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#ifndef CONFIG_DDRC
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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banks = (SDRAM_BANK4 ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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@ -487,7 +487,7 @@ for(times = 0; times < banks; times++) {
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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#endif
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = CFG_CPU_SPEED;
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#ifdef DMA_CHANNEL0_EN
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addr = DDR_DMA0_SRC;
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@ -560,7 +560,7 @@ void ddr_mem_init(int msel, int hl, int tsel, int arg)
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register unsigned int cpu_clk, ddr_twr;
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register unsigned int ddrc_cfg_reg=0, init_ddrc_mdelay=0;
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = CFG_CPU_SPEED;
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#if defined(CONFIG_SDRAM_DDR2) // ddr2
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ddrc_cfg_reg = DDRC_CFG_TYPE_DDR2 | (DDR_ROW-12)<<10
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@ -869,14 +869,14 @@ void sdram_init_4760(void)
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#endif
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testall = 0;
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = CFG_CPU_SPEED;
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#ifdef DEBUG
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ddrc_regs_print();
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#endif
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#if defined(CONFIG_FPGA)
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mem_clk = ARG_EXTAL / CFG_DIV;
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mem_clk = CFG_EXTAL / CFG_DIV;
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ns = 7;
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#else
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mem_clk = __cpm_get_mclk();
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@ -1157,7 +1157,7 @@ void sdram_init_4760(void)
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = ARG_CPU_SPEED;
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cpu_clk = CFG_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_BCR = 0; /* Disable bus release */
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@ -1178,7 +1178,7 @@ void sdram_init_4760(void)
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(ARG_BANK_ADDR_2BIT<<EMC_DMCR_BA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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@ -1248,10 +1248,7 @@ static void serial_setbrg(void)
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volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
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u32 baud_div, tmp;
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// baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
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// (ARG_EXTAL / 32 / CONFIG_BAUDRATE) : (ARG_EXTAL / 16 / CONFIG_BAUDRATE);
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baud_div = (ARG_EXTAL / 16 / 57600);
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baud_div = (CFG_EXTAL / 16 / 57600);
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tmp = *uart_lcr;
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tmp |= UART_LCR_DLAB;
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*uart_lcr = tmp;
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@ -10,6 +10,9 @@
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//#define CONFIG_FPGA
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//#define CFG_DIV 2 /* for FPGA */
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#define CFG_EXTAL 12000000
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#define CFG_CPU_SPEED 144000000 /* CPU clock */
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#define CONFIG_DDRC
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#define CONFIG_SDRAM_DDR2
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//#define CONFIG_SDRAM_MDDR
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@ -35,19 +35,6 @@ void load_args_4740()
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ARG_COL_ADDR = 9;
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}
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void load_args_4760()
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{
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ARG_EXTAL = 12 * 1000000;
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ARG_CPU_SPEED = 12 * ARG_EXTAL;
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ARG_PHM_DIV = 3;
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ARG_UART_BAUD = 57600;
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ARG_BUS_WIDTH_16 = * (int *)0x80002014;
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ARG_BANK_ADDR_2BIT = 4;
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ARG_ROW_ADDR = 13;
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ARG_COL_ADDR = 10;
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}
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void c_main(void)
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{
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ARG_CPU_ID = * (int *)0x80002008;
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@ -63,7 +50,6 @@ void c_main(void)
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serial_puts("Ben NanoNote\n");
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break;
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case 0x4760:
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load_args_4760();
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gpio_init_4760();
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cpm_start_all_4760();
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serial_init_4760(1);
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