mirror of
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239 lines
6.4 KiB
C
239 lines
6.4 KiB
C
//
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// Authors: Xiangfu Liu <xiangfu@sharism.cc>
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//
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// This program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version
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// 3 of the License, or (at your option) any later version.
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//
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#include "jz4740.h"
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void gpio_init_4740()
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{
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__gpio_as_nand();
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__gpio_as_sdram_32bit();
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/* enable the TP4, TP5 as UART0 */
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REG_GPIO_PXSELS(2) = 0x80000000;
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__gpio_as_uart0();
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__gpio_as_lcd_18bit();
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__gpio_as_msc();
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#define GPIO_LCD_CS (2 * 32 + 21)
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#define GPIO_KEYOUT_BASE (2 * 32 + 10)
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#define GPIO_KEYIN_BASE (3 * 32 + 18)
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unsigned int i;
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for (i = 0; i < 7; i++){
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__gpio_as_input(GPIO_KEYIN_BASE + i);
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__gpio_enable_pull(GPIO_KEYIN_BASE + i);
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}
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for (i = 0; i < 8; i++) {
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__gpio_as_output(GPIO_KEYOUT_BASE + i);
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__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
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}
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__gpio_as_output(GPIO_LCD_CS);
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__gpio_clear_pin(GPIO_LCD_CS);
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}
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void pll_init_4740()
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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/* int div[5] = {1, 4, 4, 4, 4}; */ /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[ARG_PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[ARG_PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[ARG_PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[ARG_PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
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/* Init UHC clock */
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REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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nf = ARG_CPU_SPEED * 2 / ARG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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static void serial_setbaud()
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{
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volatile u8* uart_lcr = (volatile u8*)(UART_BASE + OFF_LCR);
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volatile u8* uart_dlhr = (volatile u8*)(UART_BASE + OFF_DLHR);
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volatile u8* uart_dllr = (volatile u8*)(UART_BASE + OFF_DLLR);
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u32 baud_div, tmp;
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baud_div = ARG_EXTAL / 16 / ARG_UART_BAUD;
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tmp = *uart_lcr;
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tmp |= UART_LCR_DLAB;
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*uart_lcr = tmp;
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*uart_dlhr = (baud_div >> 8) & 0xff;
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*uart_dllr = baud_div & 0xff;
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tmp &= ~UART_LCR_DLAB;
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*uart_lcr = tmp;
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}
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void serial_init_4740(int uart)
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{
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UART_BASE = UART0_BASE + uart * UART_OFF;
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volatile u8* uart_fcr = (volatile u8*)(UART_BASE + OFF_FCR);
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volatile u8* uart_lcr = (volatile u8*)(UART_BASE + OFF_LCR);
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volatile u8* uart_ier = (volatile u8*)(UART_BASE + OFF_IER);
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volatile u8* uart_sircr = (volatile u8*)(UART_BASE + OFF_SIRCR);
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/* Disable port interrupts while changing hardware */
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*uart_ier = 0;
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/* Disable UART unit function */
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*uart_fcr = ~UART_FCR_UUE;
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/* Set both receiver and transmitter in UART mode (not SIR) */
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*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
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/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
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/* Set baud rate */
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serial_setbaud();
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/* Enable UART unit, enable and clear FIFO */
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*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
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}
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#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
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// SDRAM Timings, unit: ns
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#define SDRAM_TRAS 45 /* RAS# Active Time */
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
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void sdram_init_4740()
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{
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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if (ARG_BUS_WIDTH_16 == 0xff)
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return;
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else
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ARG_BUS_WIDTH_16 = 1;
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cpu_clk = ARG_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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#define SDRAM_BW16 1
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dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((ARG_ROW_ADDR-11)<<EMC_DMCR_RA_BIT) |
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((ARG_COL_ADDR-8)<<EMC_DMCR_CA_BIT) |
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(ARG_BANK_ADDR_2BIT<<EMC_DMCR_BA_BIT) |
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(ARG_BUS_WIDTH_16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS/ns;
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if (tmp < 4) tmp = 4;
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if (tmp > 11) tmp = 11;
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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tmp = SDRAM_RCD/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = SDRAM_TPC/ns;
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if (tmp > 7) tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = SDRAM_TRWL/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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if (tmp > 14) tmp = 14;
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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REG_EMC_DMCR = dmcr;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 2. Enable auto-refresh */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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REG_EMC_RTCOR = tmp;
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REG_EMC_RTCNT = 0;
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REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 3. Mode Register Set */
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REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Set back to basic DMCR value */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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/* everything is ok now */
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}
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void nand_init_4740()
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{
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REG_EMC_SMCR1 = 0x094c4400;
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REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1; //__nand_enable()
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}
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