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First part of the board bringup: power and clock.
- atusd/ERRATA: variations of the circuit being debugged from the design - tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable the board and (in the future) establish communication - atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative load from scope probe
This commit is contained in:
Werner Almesberger
parent
fc0acf1787
commit
86e556ce92
5
atusd/ERRATA
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5
atusd/ERRATA
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- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
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a bad trace. According to simulations, 22 pF should be more than enough.
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- added wire connecting uSD-side ground plane to ground plane at outer edge,
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to improve CLK signal return. (Probably unnecessary, too.)
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54
atusd/sim/clk.sch
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54
atusd/sim/clk.sch
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<Qucs Schematic 0.0.15>
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<Properties>
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<View=0,0,1010,882,1,0,0>
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<Grid=10,10,1>
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<DataSet=clk.dat>
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<DataDisplay=clk.dpl>
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<OpenDisplay=1>
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<showFrame=0>
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<FrameText0=Title>
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<FrameText1=Drawn By:>
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<FrameText2=Date:>
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<FrameText3=Revision:>
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</Properties>
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<Symbol>
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</Symbol>
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<Components>
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<GND * 1 560 480 0 0 0 0>
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<.DC DC1 1 90 40 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
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<Vrect V2 1 560 390 18 -26 0 1 "3.3 V" 1 "33 ns" 1 "33 ns" 1 "1 ns" 0 "1 ns" 0 "0 ns" 0>
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<.TR TR1 1 100 120 0 57 0 0 "lin" 1 "0" 1 "0.1 us" 1 "9991" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
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<R R3 1 490 260 -26 15 0 0 "100 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
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<GND * 1 420 480 0 0 0 0>
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<C C2 1 420 370 17 -26 0 1 "50 pF" 1 "" 0 "neutral" 0>
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<GND * 1 280 480 0 0 0 0>
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<R R1 1 280 330 15 -26 0 1 "56 kOhm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
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<R R2 1 280 430 15 -26 0 1 "10 kOhm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
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<C C1 1 350 260 -26 17 0 0 "22 pF" 1 "" 0 "neutral" 0>
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</Components>
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<Wires>
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<520 260 560 260 "" 0 0 0 "">
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<560 260 560 360 "" 0 0 0 "">
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<560 420 560 480 "" 0 0 0 "">
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<420 400 420 480 "" 0 0 0 "">
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<420 260 460 260 "" 0 0 0 "">
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<420 260 420 340 "" 0 0 0 "">
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<380 260 420 260 "Vmeas" 350 140 39 "">
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<280 360 280 400 "Vout" 170 330 17 "">
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<280 260 280 300 "" 0 0 0 "">
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<280 260 320 260 "" 0 0 0 "">
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<280 460 280 480 "" 0 0 0 "">
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<560 260 560 260 "Vin" 590 200 0 "">
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</Wires>
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<Diagrams>
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<Rect 120 752 719 212 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
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<"Vin.Vt" #0000ff 0 3 0 0 0>
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<"Vmeas.Vt" #ff0000 0 3 0 0 0>
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<"Vout.Vt" #ff00ff 0 3 0 0 0>
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</Rect>
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<Rect 670 480 278 250 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
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<"Vout.Vt" #0000ff 0 3 0 0 0>
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</Rect>
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</Diagrams>
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<Paintings>
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</Paintings>
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7
atusd/tools/Makefile
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7
atusd/tools/Makefile
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CC=mipsel-openwrt-linux-gcc
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CFLAGS=-Wall
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MAIN = try
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OBJS = $(MAIN).c lib/atusd.o
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$(MAIN): $(OBJS)
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113
atusd/tools/lib/atusd.c
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113
atusd/tools/lib/atusd.c
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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enum {
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VDD_OFF = 1 << 6, /* VDD disable, PD06 */
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MxSx = 1 << 8, /* CMD, PD08 */
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CLK = 1 << 9, /* CLK, PD09 */
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SCLK = 1 << 10, /* DAT0, PD10 */
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SLP_TR = 1 << 11, /* DAT1, PD11 */
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IRQ = 1 << 12, /* DAT2, PD12 */
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nSEL = 1 << 13, /* DAT3/CD, PD13 */
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};
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#define SOC_BASE 0x10000000
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#define REG(n) (*(volatile uint32_t *) (dsc->mem+(n)))
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#define CGU(n) REG(0x00000+(n))
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#define GPIO(n) REG(0x10000+(n))
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#define MSC(n) REG(0x21000+(n))
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#define PDDATS GPIO(0x314) /* port D data set */
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#define PDDATC GPIO(0x318) /* port D data clear */
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#define PDFUNS GPIO(0x344) /* port D function set */
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#define PDFUNC GPIO(0x348) /* port D function clear */
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#define PDDIRS GPIO(0x364) /* port D direction set */
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#define PDDIRC GPIO(0x368) /* port D direction clear */
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#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_CLKRT MSC(0x08) /* MSC Clock Rate */
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#define CLKGR CGU(0x0020) /* Clock Gate */
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#define MSCCDR CGU(0x0068) /* MSC device clock divider */
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#define PAGE_SIZE 4096
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struct atusd_dsc {
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int fd;
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void *mem;
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};
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struct atusd_dsc *atusd_open(void)
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{
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struct atusd_dsc *dsc;
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dsc = malloc(sizeof(*dsc));
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if (!dsc) {
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perror("malloc");
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exit(1);
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}
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dsc->fd = open("/dev/mem", O_RDWR);
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if (dsc->fd < 0) {
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perror("/dev/mem");
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exit(1);
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}
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dsc->mem = mmap(NULL, PAGE_SIZE*3*16, PROT_READ | PROT_WRITE,
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MAP_SHARED, dsc->fd, SOC_BASE);
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if (dsc->mem == MAP_FAILED) {
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perror("mmap");
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exit(1);
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}
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/* set the output levels */
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PDDATS = nSEL | VDD_OFF;
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PDDATC = SCLK | SLP_TR;
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/* take the GPIOs away from the MMC controller */
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PDFUNC = MxSx | SCLK | SLP_TR | IRQ | nSEL;
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PDFUNS = CLK;
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/* set the pin directions */
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PDDIRC = IRQ;
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PDDIRS = MxSx | CLK | SCLK | SLP_TR | nSEL;
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/* enable power */
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PDDATC = VDD_OFF;
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/* set the MSC clock to 316 MHz / 21 = 16 MHz */
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MSCCDR = 20;
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/*
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* Enable the MSC clock. We need to do this before accessing any
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* registers of the MSC block !
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*/
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CLKGR &= ~(1 << 7);
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/* bus clock = MSC clock / 1 */
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MSC_CLKRT = 0;
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/* start MMC clock output */
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MSC_STRPCL = 2;
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return dsc;
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}
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void atusd_close(struct atusd_dsc *dsc)
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{
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/* stop the MMC clock */
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MSC_STRPCL = 1;
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/* cut the power */
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PDDATS = VDD_OFF;
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/* make all MMC pins inputs */
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PDDIRC = MxSx | CLK | SCLK | SLP_TR | IRQ | nSEL;
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}
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14
atusd/tools/try.c
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14
atusd/tools/try.c
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struct atusd_dsc;
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int main(void)
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{
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struct atusd_dsc *dsc;
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char tmp;
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dsc = atusd_open();
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read(1, tmp, 1);
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atusd_close(dsc);
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return 0;
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}
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