First part of the board bringup: power and clock.

- atusd/ERRATA: variations of the circuit being debugged from the design - tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable the board and (in the future) establish communication - atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative load from scope probe
2024-11-22 20:39:20 +02:00 · 2010-09-04 23:14:57 -03:00 · 2010-09-04 23:14:57 -03:00 · 86e556ce92
commit 86e556ce92
parent fc0acf1787
5 changed files with 193 additions and 0 deletions
--- a/atusd/ERRATA
+++ b/atusd/ERRATA
@ -0,0 +1,5 @@
+- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
+  a bad trace. According to simulations, 22 pF should be more than enough.
+
+- added wire connecting uSD-side ground plane to ground plane at outer edge,
+  to improve CLK signal return. (Probably unnecessary, too.)
--- a/atusd/sim/clk.sch
+++ b/atusd/sim/clk.sch
@ -0,0 +1,54 @@
+<Qucs Schematic 0.0.15>
+<Properties>
+  <View=0,0,1010,882,1,0,0>
+  <Grid=10,10,1>
+  <DataSet=clk.dat>
+  <DataDisplay=clk.dpl>
+  <OpenDisplay=1>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <GND * 1 560 480 0 0 0 0>
+  <.DC DC1 1 90 40 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
+  <Vrect V2 1 560 390 18 -26 0 1 "3.3 V" 1 "33 ns" 1 "33 ns" 1 "1 ns" 0 "1 ns" 0 "0 ns" 0>
+  <.TR TR1 1 100 120 0 57 0 0 "lin" 1 "0" 1 "0.1 us" 1 "9991" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
+  <R R3 1 490 260 -26 15 0 0 "100 Ohm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <GND * 1 420 480 0 0 0 0>
+  <C C2 1 420 370 17 -26 0 1 "50 pF" 1 "" 0 "neutral" 0>
+  <GND * 1 280 480 0 0 0 0>
+  <R R1 1 280 330 15 -26 0 1 "56 kOhm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <R R2 1 280 430 15 -26 0 1 "10 kOhm" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <C C1 1 350 260 -26 17 0 0 "22 pF" 1 "" 0 "neutral" 0>
+</Components>
+<Wires>
+  <520 260 560 260 "" 0 0 0 "">
+  <560 260 560 360 "" 0 0 0 "">
+  <560 420 560 480 "" 0 0 0 "">
+  <420 400 420 480 "" 0 0 0 "">
+  <420 260 460 260 "" 0 0 0 "">
+  <420 260 420 340 "" 0 0 0 "">
+  <380 260 420 260 "Vmeas" 350 140 39 "">
+  <280 360 280 400 "Vout" 170 330 17 "">
+  <280 260 280 300 "" 0 0 0 "">
+  <280 260 320 260 "" 0 0 0 "">
+  <280 460 280 480 "" 0 0 0 "">
+  <560 260 560 260 "Vin" 590 200 0 "">
+</Wires>
+<Diagrams>
+  <Rect 120 752 719 212 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+	<"Vin.Vt" #0000ff 0 3 0 0 0>
+	<"Vmeas.Vt" #ff0000 0 3 0 0 0>
+	<"Vout.Vt" #ff00ff 0 3 0 0 0>
+  </Rect>
+  <Rect 670 480 278 250 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+	<"Vout.Vt" #0000ff 0 3 0 0 0>
+  </Rect>
+</Diagrams>
+<Paintings>
+</Paintings>
--- a/atusd/tools/Makefile
+++ b/atusd/tools/Makefile
@ -0,0 +1,7 @@
+CC=mipsel-openwrt-linux-gcc
+CFLAGS=-Wall
+
+MAIN = try
+OBJS = $(MAIN).c lib/atusd.o
+
+$(MAIN):	$(OBJS)
--- a/atusd/tools/lib/atusd.c
+++ b/atusd/tools/lib/atusd.c
@ -0,0 +1,113 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+
+enum {
+	VDD_OFF	= 1 << 6,	/* VDD disable, PD06 */
+	MxSx	= 1 << 8,	/* CMD, PD08 */
+	CLK	= 1 << 9,	/* CLK, PD09 */
+	SCLK	= 1 << 10,	/* DAT0, PD10 */
+	SLP_TR	= 1 << 11,	/* DAT1, PD11 */
+	IRQ	= 1 << 12,	/* DAT2, PD12 */
+	nSEL	= 1 << 13,	/* DAT3/CD, PD13 */
+};
+
+
+#define SOC_BASE	0x10000000
+
+#define	REG(n)	(*(volatile uint32_t *) (dsc->mem+(n)))
+
+#define CGU(n)	REG(0x00000+(n))
+#define GPIO(n)	REG(0x10000+(n))
+#define MSC(n)	REG(0x21000+(n))
+
+#define PDDATS	GPIO(0x314)	/* port D data set */
+#define PDDATC	GPIO(0x318)	/* port D data clear */
+#define PDFUNS	GPIO(0x344)	/* port D function set */
+#define PDFUNC	GPIO(0x348)	/* port D function clear */
+#define PDDIRS	GPIO(0x364)	/* port D direction set */
+#define PDDIRC	GPIO(0x368)	/* port D direction clear */
+
+#define MSC_STRPCL	MSC(0x00)	/* Start/stop MMC/SD clock */
+#define MSC_CLKRT	MSC(0x08)	/* MSC Clock Rate */
+
+#define CLKGR		CGU(0x0020)	/* Clock Gate */
+#define MSCCDR		CGU(0x0068)	/* MSC device clock divider */
+
+
+#define	PAGE_SIZE	4096
+
+
+struct atusd_dsc {
+	int fd;
+	void *mem;
+};
+
+
+struct atusd_dsc *atusd_open(void)
+{
+	struct atusd_dsc *dsc;
+
+	dsc = malloc(sizeof(*dsc));
+	if (!dsc) {
+		perror("malloc");
+		exit(1);
+	}
+
+	dsc->fd = open("/dev/mem", O_RDWR);
+	if (dsc->fd < 0) {
+		perror("/dev/mem");
+		exit(1);
+	}
+	dsc->mem = mmap(NULL, PAGE_SIZE*3*16, PROT_READ | PROT_WRITE,
+	    MAP_SHARED, dsc->fd, SOC_BASE);
+        if (dsc->mem == MAP_FAILED) {
+                perror("mmap");
+                exit(1);
+        }
+
+	/* set the output levels */
+	PDDATS = nSEL | VDD_OFF;
+	PDDATC = SCLK | SLP_TR;
+
+	/* take the GPIOs away from the MMC controller */
+	PDFUNC = MxSx | SCLK | SLP_TR | IRQ | nSEL;
+	PDFUNS = CLK;
+
+	/* set the pin directions */
+	PDDIRC = IRQ;
+	PDDIRS = MxSx | CLK | SCLK | SLP_TR | nSEL;
+
+	/* enable power */
+	PDDATC = VDD_OFF;
+
+	/* set the MSC clock to 316 MHz / 21 = 16 MHz */
+	MSCCDR = 20;
+	/*
+	 * Enable the MSC clock. We need to do this before accessing any
+	 * registers of the MSC block !
+	 */
+	CLKGR &= ~(1 << 7);
+	/* bus clock = MSC clock / 1 */
+	MSC_CLKRT = 0;
+	/* start MMC clock output */
+	MSC_STRPCL = 2;
+
+	return dsc;
+}
+
+
+void atusd_close(struct atusd_dsc *dsc)
+{
+	/* stop the MMC clock */
+	MSC_STRPCL = 1;
+
+	/* cut the power */
+	PDDATS = VDD_OFF;
+
+	/* make all MMC pins inputs */
+	PDDIRC = MxSx | CLK | SCLK | SLP_TR | IRQ | nSEL;
+}
--- a/atusd/tools/try.c
+++ b/atusd/tools/try.c
@ -0,0 +1,14 @@
+struct atusd_dsc;
+
+
+int main(void)
+{
+	struct atusd_dsc *dsc;
+	char tmp;
+
+	dsc = atusd_open();
+	read(1, tmp, 1);
+	atusd_close(dsc);
+
+	return 0;
+}