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Adding evolvable hardware example

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This commit is contained in:
Carlos Camargo
2010-10-01 09:03:07 -05:00
parent 5459532f07
commit 1f2712e4de
44 changed files with 4424 additions and 1047 deletions
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75
Examples/ehw4/logic/Makefile Normal file
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DESIGN = ehw
PINS = $(DESIGN).ucf
DEVICE = xc3s500e-VQ100-4
BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
-g CRC:enable -g StartUpClk:CCLK
SIM_CMD = /opt/cad/modeltech/bin/vsim
SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
#SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SAKC_IP = 192.168.254.101
SRC = $(DESIGN).v reg_bank.v
SRC_HDL = evalfit_peripheral.vhd counters.vhd mt.vhd
all: bits
remake: clean-build all
clean:
rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
clean-build: clean
rm -rf build
cleanall: clean
rm -rf build $(DESIGN).bit
bits: $(DESIGN).bit
#
# Synthesis
#
build/project.src:
@[ -d build ] || mkdir build
@rm -f $@
#If you don't have logicores disable this line
cp *ngc build/
for i in $(SRC); do echo verilog work ../$$i >> $@; done
for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
build/project.xst: build/project.src
echo "run" > $@
echo "-top $(DESIGN) " >> $@
echo "-p $(DEVICE)" >> $@
echo "-opt_mode Area" >> $@
echo "-opt_level 1" >> $@
echo "-ifn project.src" >> $@
echo "-ifmt mixed" >> $@
echo "-ofn project.ngc" >> $@
echo "-ofmt NGC" >> $@
echo "-rtlview yes" >> $@
build/project.ngc: build/project.xst $(SRC)
cd build && xst -ifn project.xst -ofn project.log
build/project.ngd: build/project.ngc $(PINS)
cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
build/project.ncd: build/project.ngd
cd build && map -pr b -p $(DEVICE) project
build/project_r.ncd: build/project.ncd
cd build && par -w project project_r.ncd
build/project_r.twr: build/project_r.ncd
cd build && trce -v 25 project_r.ncd project.pcf
$(DESIGN).bit: build/project_r.ncd build/project_r.twr
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
@mv -f build/project_r.bit $@
sim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
upload: $(DESIGN).bit
scp $(DESIGN).bit root@$(SAKC_IP):

147
Examples/ehw4/logic/counters.vhd Executable file
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-------------------------------------------------------------------------------
-- --
-- MT32 - Mersenne Twister --
-- Copyright (C) 2007 HT-LAB --
-- --
-- Contact : Use feedback form on the website. --
-- Web: http://www.ht-lab.com --
-- --
-- MT32 files are released under the GNU General Public License. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- --
-- Counters, instantiated in top level --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY counters IS
GENERIC(
M : integer := 397;
N : integer := 623
);
PORT(
clk : IN std_logic;
resetn : IN std_logic;
ena : IN std_logic;
wea : OUT std_logic;
kk_cnt : OUT std_logic_vector (9 DOWNTO 0);
km_cnt : OUT std_logic_vector (9 DOWNTO 0);
kp_cnt : OUT std_logic_vector (9 DOWNTO 0);
wr_cnt : OUT std_logic_vector (9 DOWNTO 0)
);
END counters ;
--
ARCHITECTURE rtl OF counters IS
signal kk_cnt_s : std_logic_vector (9 DOWNTO 0);
signal km_cnt_s : std_logic_vector (9 DOWNTO 0);
signal kp_cnt_s : std_logic_vector (9 DOWNTO 0);
signal wr_cnt_s : std_logic_vector (9 DOWNTO 0);
BEGIN
process (clk,resetn)
begin
if (resetn='0') then
wea <= '0';
elsif (rising_edge(clk)) then
wea <= ena; -- wea is delayed by 1 clock cycle to
end if; -- prevent writing outside the dpram address
end process; -- address range (0..623)
-------------------------------------------------------------------------------
-- Write counter which is equal to kk-1
-- Required to achieve single cycle read/write
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
wr_cnt_s <= (others => '1');
elsif (rising_edge(clk)) then
if (wr_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
wr_cnt_s <= (others => '0');
elsif ena='1' then
wr_cnt_s <= wr_cnt_s + '1';
end if;
end if;
end process;
wr_cnt <= wr_cnt_s;
-------------------------------------------------------------------------------
-- kk Counter
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
kk_cnt_s <= (others => '0');
elsif (rising_edge(clk)) then
if (kk_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
kk_cnt_s <= (others => '0');
elsif ena='1' then
kk_cnt_s <= kk_cnt_s + '1';
end if;
end if;
end process;
kk_cnt <= kk_cnt_s;
-------------------------------------------------------------------------------
-- kp Counter
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
kp_cnt_s <= "0000000001";
elsif (rising_edge(clk)) then
if (kp_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
kp_cnt_s <= (others => '0');
elsif ena='1' then
kp_cnt_s <= kp_cnt_s + '1';
end if;
end if;
end process;
kp_cnt <= kp_cnt_s;
-------------------------------------------------------------------------------
-- km Counter
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
km_cnt_s <= CONV_STD_LOGIC_VECTOR(M,10);
elsif (rising_edge(clk)) then
if (km_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then
km_cnt_s <= (others => '0');
elsif ena='1' then
km_cnt_s <= km_cnt_s + '1';
end if;
end if;
end process;
km_cnt <= km_cnt_s;
end architecture rtl;

3
Examples/ehw4/logic/dpram624x1.ngc Normal file
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Examples/ehw4/logic/dpram624x31.ngc Normal file
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Examples/ehw4/logic/dpram624x32.ngc Normal file
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37
Examples/ehw4/logic/ehw.ucf Normal file
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NET clk LOC = "P38";
NET reset LOC = "P30"; #WARNING change to another pin
NET led LOC = "P44";
NET irq_pin LOC = "P71";
#ADDRESS BUS
NET "addr<12>" LOC = "P90";
NET "addr<11>" LOC = "P91";
NET "addr<10>" LOC = "P85";
NET "addr<9>" LOC = "P92";
NET "addr<8>" LOC = "P94";
NET "addr<7>" LOC = "P95";
NET "addr<6>" LOC = "P98";
NET "addr<5>" LOC = "P3";
NET "addr<4>" LOC = "P2";
NET "addr<3>" LOC = "P78";
NET "addr<2>" LOC = "P79";
NET "addr<1>" LOC = "P83";
NET "addr<0>" LOC = "P84";
#DATA BUS
NET "sram_data<7>" LOC = "P4";
NET "sram_data<6>" LOC = "P5";
NET "sram_data<5>" LOC = "P9";
NET "sram_data<4>" LOC = "P10";
NET "sram_data<3>" LOC = "P11";
NET "sram_data<2>" LOC = "P12";
NET "sram_data<1>" LOC = "P15";
NET "sram_data<0>" LOC = "P16";
#CONTROL BUS
NET "nwe" LOC = "P88";
NET "noe" LOC = "P86";
NET "ncs" LOC = "P69";

278
Examples/ehw4/logic/ehw.v Normal file
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`timescale 1ns / 1ps
module ehw(clk, sram_data, addr, nwe, ncs, noe, reset, led,
irq_pin);
parameter B = (7);
input clk, addr, nwe, ncs, noe, reset;
inout [B:0] sram_data;
output led;
output irq_pin;
// synchronize signals
reg sncs, snwe;
reg [12:0] buffer_addr;
reg [B:0] buffer_data;
wire led;
// bram-cpu interfaz
reg we;
reg w_st=0;
reg [B:0] wdBus;
reg [B:0] rdBus;
wire [12:0] addr;
reg [7:0] bae;
// bram-evalfit interfaz
wire we_eval, en_ev;
wire [63:0] ev_do;
wire [63:0] ev_di;
// Interconnection
wire [31:0] mt_rnd;
wire [31:0] reg0;
wire [31:0] reg1;
wire [31:0] reg2;
wire [31:0] reg3;
wire [31:0] reg4;
wire [7:0] status;
wire [15:0] error;
wire [8:0] evalfit_addr;
wire en_fit;
wire [15:0] max_com;
wire [3:0] max_lev;
wire [7:0] control;
reg [7:0] reg_bank [31:0];
wire enReg;
wire [4:0] address;
// Test : LED blinking
reg [25:0] counter;
always @(posedge clk) begin
if (~reset)
counter <= {25{1'b0}};
else
counter <= counter + 1;
end
assign led = counter[24];
// Data Bus direction control
wire T = ~noe | ncs;
assign sram_data = T?8'bZ:rdBus;
// synchronize assignment
always @(negedge clk)
begin
sncs <= ncs;
snwe <= nwe;
buffer_data <= sram_data;
buffer_addr <= addr;
end
// write access cpu to bram
always @(posedge clk)
if(~reset) {w_st, we, wdBus} <= 0;
else begin
wdBus <= buffer_data;
case (w_st)
0: begin
we <= 0;
if(sncs | snwe) w_st <= 1;
end
1: begin
if(~(sncs | snwe)) begin
we <= 1;
w_st <= 0;
end
else we <= 0;
end
endcase
end
// Address Decoder
// We have 2 memory blocks 1: 512 x 64 bits memory 32kb = 4kB 0000 - 0FFF buffer_addr[12] = 0
// 2: Register Bank 1000 - 101F buffer_addr[12] = 1
// SIE has an eight bits data bus, this module generate the required signals to create a 64 bits word.
always @(buffer_addr)
begin
if(~buffer_addr[12]) begin
case (buffer_addr[2:0])
0: bae <= 8'h01;
1: bae <= 8'h02;
2: bae <= 8'h04;
3: bae <= 8'h08;
4: bae <= 8'h10;
5: bae <= 8'h20;
6: bae <= 8'h40;
7: bae <= 8'h80;
endcase
end
else
bae <= 8'h00;
end
wire en1, en2; // enable memory signals
assign en0 = bae[0] | bae[1] | bae[2] | bae[3];
assign en1 = bae[4] | bae[5] | bae[6] | bae[7];
reg[31:0] DIA_Aux;
always @ (posedge clk) begin
if (bae[0]) DIA_Aux[7:0] = wdBus[7:0];
if (bae[1]) DIA_Aux[15:8] = wdBus[7:0];
if (bae[2]) DIA_Aux[23:16] = wdBus[7:0];
if (bae[3]) DIA_Aux[31:24] = wdBus[7:0];
if (bae[4]) DIA_Aux[7:0] = wdBus[7:0];
if (bae[5]) DIA_Aux[15:8] = wdBus[7:0];
if (bae[6]) DIA_Aux[23:16] = wdBus[7:0];
if (bae[7]) DIA_Aux[31:24] = wdBus[7:0];
end
reg [2:0] state, nextstate; //FSM for write in 32bit mode to memory
wire we0, we1;
wire nreset;
assign nreset = ~reset;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
always @ (posedge clk, posedge nreset)
if (nreset) state <= S0;
else state <= nextstate;
// next state logic
always@(*)
case (state)
S0:if (bae[3]&we) nextstate = S1;
else
if (bae[7]&we) nextstate = S2;
else nextstate = S0;
S1: nextstate = S0;
S2: nextstate = S0;
default: nextstate = S0;
endcase
// output logic
assign we0 = (state == S1);
assign we1 = (state == S2);
// Read control
reg [7:0] MemDOA;
wire [63:0] DOA_Aux;
always @(posedge clk)
if(~reset)begin
rdBus = 8'h00;
end
else begin
if(enReg)
rdBus = reg_bank[address];
else
rdBus = MemDOA[7:0];
end
// memory output mux
always @(buffer_addr[2:0])
case (buffer_addr[2:0])
0 : MemDOA = DOA_Aux[7:0];
1 : MemDOA = DOA_Aux[15:8];
2 : MemDOA = DOA_Aux[23:16];
3 : MemDOA = DOA_Aux[31:24];
4 : MemDOA = DOA_Aux[39:32];
5 : MemDOA = DOA_Aux[47:40];
6 : MemDOA = DOA_Aux[55:48];
7 : MemDOA = DOA_Aux[63:56];
default: MemDOA = 8'h00;
endcase
// Store Inputs
always @(posedge clk)
begin
if(enReg) begin
reg_bank[20] = error[7:0];
reg_bank[21] = error[15:8];
reg_bank[22] = status[7:0];
reg_bank[24] = mt_rnd[7:0];
reg_bank[25] = mt_rnd[15:8];
reg_bank[26] = mt_rnd[23:16];
reg_bank[27] = mt_rnd[31:24];
end
end
assign address[4:0] = buffer_addr[4:0];
assign enReg = buffer_addr[12];
assign reg0[7:0] = reg_bank[0];
assign reg0[15:8] = reg_bank[1];
assign reg0[23:16] = reg_bank[2];
assign reg0[31:24] = reg_bank[3];
assign reg1[7:0] = reg_bank[4];
assign reg1[15:8] = reg_bank[5];
assign reg1[23:16] = reg_bank[6];
assign reg1[31:24] = reg_bank[7];
assign reg2[7:0] = reg_bank[8];
assign reg2[15:8] = reg_bank[9];
assign reg2[23:16] = reg_bank[10];
assign reg2[31:24] = reg_bank[11];
assign reg3[7:0] = reg_bank[12];
assign reg3[15:8] = reg_bank[13];
assign reg3[23:16] = reg_bank[14];
assign reg3[31:24] = reg_bank[15];
assign reg4[7:0] = reg_bank[16];
assign reg4[15:8] = reg_bank[17];
assign reg4[23:16] = reg_bank[18];
assign reg4[31:24] = reg_bank[19];
assign max_lev = reg_bank[28];
assign control = reg_bank[29];
assign max_com[7:0] = reg_bank[30];
assign max_com[15:8] = reg_bank[31];
// Write control
always @(negedge clk)
if(we & enReg) begin
case (address)
0: reg_bank[0] = wdBus;
1: reg_bank[1] = wdBus;
2: reg_bank[2] = wdBus;
3: reg_bank[3] = wdBus;
4: reg_bank[4] = wdBus;
5: reg_bank[5] = wdBus;
6: reg_bank[6] = wdBus;
7: reg_bank[7] = wdBus;
8: reg_bank[8] = wdBus;
9: reg_bank[9] = wdBus;
10: reg_bank[10] = wdBus;
11: reg_bank[11] = wdBus;
12: reg_bank[12] = wdBus;
13: reg_bank[13] = wdBus;
14: reg_bank[14] = wdBus;
15: reg_bank[15] = wdBus;
16: reg_bank[16] = wdBus;
17: reg_bank[17] = wdBus;
18: reg_bank[18] = wdBus;
19: reg_bank[19] = wdBus;
28: reg_bank[28] = wdBus;
29: reg_bank[29] = wdBus;
30: reg_bank[30] = wdBus;
31: reg_bank[31] = wdBus;
endcase
end
RAMB16_S36_S36 #(.INIT_00(256'hABCDEF00_00000000_00000000_00000000_00000000_00000000_00000000_76543210) )
mem0 ( .CLKA(~clk), .ENA(en0), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we0), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[31:0]),
.CLKB(~clk), .ENB(en_ev), .SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[31:0]), .DIPB(0'b0), .DOB(ev_di[31:0]));
RAMB16_S36_S36 mem1( .CLKA(~clk), .ENA(en1), .SSRA(1'b0), .ADDRA(buffer_addr[11:3]), .WEA(we1), .DIA(DIA_Aux[31:0]), .DIPA(0'b0), .DOA(DOA_Aux[63:32]),
.CLKB(~clk), .ENB(en_ev),.SSRB(1'b0), .ADDRB(evalfit_addr), .WEB(we_eval), .DIB(ev_do[63:32]), .DIPB(0'b0), .DOB(ev_di[63:32]));
// evalfit_peripheral
evalfit_peripheral evalfit( .clk(clk), .reset(~reset), .habilita(control[0]), .maxcombs(max_com), .nivel_max(max_lev),
.peripheral_mem_in(ev_di), .peripheral_mem_en(en_eval), .peripheral_mem_out(ev_do), .peripheral_mem_we(we_eval),
.peripheral_mem_addr(evalfit_addr), .evalfit3_estado(status), .errores(error),
.fin_ack(irq_pin), .reg0_s(reg0), .reg1_s(reg1), .reg2_s(reg2), .reg3_s(reg3), .reg4_s(reg4));
// MersenneTwister
mt_mem random( .clk(clk), .ena(1'b1), .resetn(reset), .random(mt_rnd));
endmodule

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Examples/ehw4/logic/evalfit_peripheral.vhd Normal file
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-- 07/11/08
-- Evalfit_peripheral
-- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables ***
-- Funciona hasta con 14 vars.
-- mapa:
-- 0 - 0x3F Cromosoma
-- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB.
-- Cromosoma en memoria
-- bit bit Contenido
-- 28 a 31 Nivel del arbol
-- 32 a 47 LUT o tabla del arbol
-- 48 a 63 Variables de entrada del arbol (4 bits por variable)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity evalfit_peripheral is
Port ( clk, reset, habilita: in STD_LOGIC;
maxcombs : in STD_LOGIC_VECTOR (0 to 15);
nivel_max : in STD_LOGIC_VECTOR (0 to 3);
peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_en : out std_logic;
peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_we : out STD_LOGIC;
peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8);
evalfit3_estado : out std_logic_vector(0 to 7);
errores : out STD_LOGIC_VECTOR (0 to 15);
fin_ack : out std_logic;
reg0_s : out STD_LOGIC_VECTOR (0 to 31);
reg1_s : out STD_LOGIC_VECTOR (0 to 31);
reg2_s : out STD_LOGIC_VECTOR (0 to 31);
reg3_s : out STD_LOGIC_VECTOR (0 to 31);
reg4_s : out STD_LOGIC_VECTOR (0 to 31)
);
end evalfit_peripheral;
architecture Behavioral of evalfit_peripheral is
function mux16(sel: in std_logic_vector(0 to 3); ent: in std_logic_vector(0 to 15)) return std_logic is
begin
case sel is
when "0000" => return ent(15);
when "0001" => return ent(14);
when "0010" => return ent(13);
when "0011" => return ent(12);
when "0100" => return ent(11);
when "0101" => return ent(10);
when "0110" => return ent(9);
when "0111" => return ent(8);
when "1000" => return ent(7);
when "1001" => return ent(6);
when "1010" => return ent(5);
when "1011" => return ent(4);
when "1100" => return ent(3);
when "1101" => return ent(2);
when "1110" => return ent(1);
when others => return ent(0);
end case;
end mux16;
function mux4(sel: in std_logic_vector(0 to 1); ent: in std_logic_vector(0 to 3)) return std_logic is
begin
case sel is
when "00" => return ent(3);
when "01" => return ent(2);
when "10" => return ent(1);
when others => return ent(0);
end case;
end mux4;
-- senales para evaluar funciones
signal reg0, reg1, reg2, reg3, reg4, regn3, regn4:STD_LOGIC_VECTOR (0 to 31);
signal reg0_sig, reg1_sig, reg2_sig, reg3_sig, reg4_sig, regn3_sig, regn4_sig :STD_LOGIC_VECTOR (0 to 31);
signal sel_aux0, sel_aux1, sel_aux2, sel_aux3, sel_aux4, sel_auxn3, sel_auxn4, sal_arbol, minter_n3, minter_n4 : std_logic_vector(0 to 3);
signal salida_s, fin_ack_sig, fifow_wrreq_sig: std_logic;
signal entrada, errores_aux, errores_sig, salida_nivel : STD_LOGIC_VECTOR (0 to 15);
-- senales para las memorias, guardan resultados de arboles intermedios
signal DO_n2, DI_n2, DO_n3, DI_n3, DO_n4, DI_n4: std_logic_vector(3 downto 0);
signal ADDR_n2, ADDR_n3, ADDR_n4: std_logic_vector(0 to 13);
signal WE_n2, WE_n3, WE_n4: std_logic_vector(3 downto 0);
signal WE_n2_sig, WE_n3_sig, WE_n4_sig: std_logic_vector(3 downto 0);
signal EN_n2, SSR, EN_n3, EN_n4: std_logic;
-- senales para el control
type estado is (reset1, reset2, inicio, proceso, n1, n2, n3, n4, precuenta, cuenta, final, final2);
signal ep, es: estado;
signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3);
signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1);
signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15);
signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 7);
signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8);
begin
process(ep, habilita, reg0, reg1, reg2, reg3, reg4, regn3, regn4, nivel, c1, c2, c3, c4, conta,
salida_s, salida_nivel, WE_n2, WE_n3, WE_n4, nivel_max,
maxcombs, peripheral_mem_in, peripheral_mem_addr_crom, peripheral_mem_addr_aux)
begin
es <= reset1;
WE_n2_sig <= "0000";
WE_n3_sig <= "0000";
WE_n4_sig <= "0000";
reg0_sig <= reg0;
reg1_sig <= reg1;
reg2_sig <= reg2;
reg3_sig <= reg3;
reg4_sig <= reg4;
regn3_sig <= regn3;
regn4_sig <= regn4;
conta_sig <= conta;
conta2_sig <= conta2;
c1_sig <= c1;
c2_sig <= c2;
c3_sig <= c3;
c4_sig <= c4;
DI_n2 <= "0000";
DI_n3 <= "0000";
DI_n4 <= "0000";
fin_ack_sig <= '0';
peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
peripheral_mem_addr_crom_sig <= peripheral_mem_addr_crom;
peripheral_mem_we <= '0';
peripheral_mem_en <= '0';
errores_sig <= errores_aux;
nivel_sig <= nivel_reg;
estado_evalf3_sig <= x"FF";
case ep is
when reset1 => --poner la memoria a 0000
WE_n2_sig <= "1111";
WE_n3_sig <= "1111";
WE_n4_sig <= "1111";
conta2_sig <= (others => '0');
es <= reset2;
when reset2 =>
DI_n2 <= "0000";
DI_n3 <= "0000";
DI_n4 <= "0000";
if(conta2 = maxcombs)then
WE_n2_sig <= "0000";
WE_n3_sig <= "0000";
WE_n4_sig <= "0000";
conta2_sig <= (others => '0');
es <= inicio;
else
WE_n2_sig <= "1111";
WE_n3_sig <= "1111";
WE_n4_sig <= "1111";
conta2_sig <= conta2 + 1;
es <= reset2;
end if;
when inicio =>
if(habilita = '0') then
es <= inicio;
conta_sig <= (others => '0');
conta2_sig <= (others => '0');
peripheral_mem_addr_sig <= (others => '0');
c1_sig <= "00";
c2_sig <= "00";
c3_sig <= "00";
c4_sig <= "00";
errores_sig <= x"0000";
else
es <= proceso;
peripheral_mem_en <= '1';
end if;
estado_evalf3_sig <= x"01";
when proceso =>
peripheral_mem_en <= '1';
if(nivel = "0001")then
case c1 is
when "00" => reg0_sig <= peripheral_mem_in(32 to 63);
when "01" => reg1_sig <= peripheral_mem_in(32 to 63);
when "10" => reg2_sig <= peripheral_mem_in(32 to 63);
when others => reg3_sig <= peripheral_mem_in(32 to 63);
end case;
es <= n1;
elsif(nivel = "0010")then
reg4_sig <= peripheral_mem_in(32 to 63);
WE_n2_sig(conv_integer(c2)) <= '1';
DI_n2(conv_integer(c2)) <= salida_nivel(2);
es <= n2;
elsif(nivel = "0011")then
regn3_sig <= peripheral_mem_in(32 to 63);
WE_n3_sig(conv_integer(c3)) <= '1';
DI_n3(conv_integer(c3)) <= salida_nivel(3);
es <= n3;
elsif(nivel = "0100")then
regn4_sig <= peripheral_mem_in(32 to 63);
WE_n4_sig(conv_integer(c4)) <= '1';
DI_n4(conv_integer(c4)) <= salida_nivel(4);
es <= n4;
elsif(nivel = "1111")then
es <= final2;
end if;
peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1;
peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1;
nivel_sig <= nivel;
estado_evalf3_sig <= x"02";
when n1 =>
peripheral_mem_en <= '1';
c1_sig <= c1 + 1;
peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
es <= proceso;
estado_evalf3_sig <= x"03";
when n2 =>
WE_n2_sig(conv_integer(c2)) <= '1';
DI_n2(conv_integer(c2)) <= salida_nivel(2);
peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida
es <= precuenta;
conta2_sig <= (others => '0');
estado_evalf3_sig <= x"04";
when n3 =>
WE_n3_sig(conv_integer(c3)) <= '1';
DI_n3(conv_integer(c3)) <= salida_nivel(3);
peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
es <= precuenta;
conta2_sig <= (others => '0');
estado_evalf3_sig <= x"05";
when n4 =>
WE_n4_sig(conv_integer(c4)) <= '1';
DI_n4(conv_integer(c4)) <= salida_nivel(4);
peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
es <= precuenta;
conta2_sig <= (others => '0');
estado_evalf3_sig <= x"06";
when precuenta =>
WE_n2_sig <= WE_n2;
WE_n3_sig <= WE_n3;
WE_n4_sig <= WE_n4;
DI_n2(conv_integer(c2)) <= salida_nivel(2);
DI_n3(conv_integer(c3)) <= salida_nivel(3);
DI_n4(conv_integer(c4)) <= salida_nivel(4);
peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9));
conta_sig <= conta;
conta2_sig <= conta + 1;
es <= cuenta;
estado_evalf3_sig <= x"07";
when cuenta =>
DI_n2(conv_integer(c2)) <= salida_nivel(2);
DI_n3(conv_integer(c3)) <= salida_nivel(3);
DI_n4(conv_integer(c4)) <= salida_nivel(4);
peripheral_mem_en <= '1';
if(conta = maxcombs)then
WE_n2_sig <= "0000";
WE_n3_sig <= "0000";
WE_n4_sig <= "0000";
conta_sig <= (others => '0');
conta2_sig <= (others => '0');
peripheral_mem_addr_sig <= peripheral_mem_addr_crom; --direccion de mem donde esta el cromosoma
es <= final;
else
WE_n2_sig <= WE_n2;
WE_n3_sig <= WE_n3;
WE_n4_sig <= WE_n4;
conta_sig <= conta + 1;
conta2_sig <= conta2 + 1;
peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9));--crear señal conta futura
if(conta(10 to 15) = "111111")then
es <= precuenta;
else
es <= cuenta;
end if;
end if;
if(nivel_reg = nivel_max)then
if(salida_nivel(conv_integer(nivel_max)) = peripheral_mem_in(conv_integer(conta(10 to 15))))then
errores_sig <= errores_aux;
else
errores_sig <= errores_aux + 1;
end if;
else
errores_sig <= errores_aux;
end if;
estado_evalf3_sig <= x"08";
when final =>
if(nivel_reg = "0010")then
c2_sig <= c2 + 1;
elsif(nivel_reg = "0011")then
c3_sig <= c3 + 1;
elsif(nivel_reg = "0100")then
c4_sig <= c4 + 1;
end if;
peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= peripheral_mem_addr_crom;
es <= proceso;
estado_evalf3_sig <= x"09";
when final2 =>
if(habilita = '1') then
es <= final2;
else
es <= inicio;
end if;
fin_ack_sig <= '1';
estado_evalf3_sig <= x"0A";
when others => es <= inicio;
end case;
end process;
process(clk, reset)
begin
if(reset = '1')then
ep <= reset1;
c1 <= "00";
c2 <= "00";
c3 <= "00";
c4 <= "00";
WE_n2 <= "0000";
WE_n3 <= "0000";
WE_n4 <= "0000";
reg0 <= x"00000000";
reg1 <= x"00000000";
reg2 <= x"00000000";
reg3 <= x"00000000";
reg4 <= x"00000000";
regn3 <= x"00000000";
regn4 <= x"00000000";
conta <= (others => '0');
conta2 <= (others => '0');
fin_ack <= '0';
peripheral_mem_addr_aux <= "000000000";
peripheral_mem_addr_crom <= "000000000";
errores_aux <= (others => '0');
nivel_reg <= "0000";
estado_evalf3 <= x"00";
elsif(rising_edge(clk))then
ep <= es;
c1 <= c1_sig;
c2 <= c2_sig;
c3 <= c3_sig;
c4 <= c4_sig;
WE_n2 <= WE_n2_sig;
WE_n3 <= WE_n3_sig;
WE_n4 <= WE_n4_sig;
reg0 <= reg0_sig;
reg1 <= reg1_sig;
reg2 <= reg2_sig;
reg3 <= reg3_sig;
reg4 <= reg4_sig;
regn3 <= regn3_sig;
regn4 <= regn4_sig;
conta <= conta_sig;
conta2 <= conta2_sig;
fin_ack <= fin_ack_sig;
peripheral_mem_addr_aux <= peripheral_mem_addr_sig;
peripheral_mem_addr_crom <= peripheral_mem_addr_crom_sig;
errores_aux <= errores_sig;
nivel_reg <= nivel_sig;
estado_evalf3 <= estado_evalf3_sig;
end if;
end process;
process(nivel_reg, conta, conta2)
begin
case nivel_reg is
when "0000" =>
ADDR_n2 <= conta(2 to 15);
ADDR_n3 <= conta(2 to 15);
ADDR_n4 <= conta(2 to 15);
when "0010" =>
ADDR_n2 <= conta(2 to 15);
ADDR_n3 <= conta(2 to 15);
ADDR_n4 <= conta(2 to 15);
when "0011" =>
ADDR_n2 <= conta2(2 to 15);
ADDR_n3 <= conta(2 to 15);
ADDR_n4 <= conta(2 to 15);
when "0100" =>
ADDR_n2 <= conta(2 to 15);
ADDR_n3 <= conta2(2 to 15);
ADDR_n4 <= conta(2 to 15);
when others =>
ADDR_n2 <= conta2(2 to 15);
ADDR_n3 <= conta2(2 to 15);
ADDR_n4 <= conta2(2 to 15);
end case;
end process;
errores <= errores_aux;
peripheral_mem_addr <= peripheral_mem_addr_aux;
nivel <= peripheral_mem_in(28 to 31);
EN_n2 <= '1';
EN_n3 <= '1';
EN_n4 <= '1';
SSR <= '0';
minter_n3 <= DO_n2;
minter_n4 <= DO_n3;
entrada <= conta;
evalfit3_estado <= estado_evalf3;
reg0_s <= reg0;
reg1_s <= reg1;
reg2_s <= reg2;
reg3_s <= reg3;
reg4_s <= reg4;
salida_nivel(1) <= sal_arbol(3);
sel_aux0(3) <= mux16(reg0(28 to 31), entrada);
sel_aux0(2) <= mux16(reg0(24 to 27), entrada);
sel_aux0(1) <= mux16(reg0(20 to 23), entrada);
sel_aux0(0) <= mux16(reg0(16 to 19), entrada);
sal_arbol(3) <= mux16(sel_aux0, reg0(0 to 15)); -- reg0(0 to 15) = dato_lut
sel_aux1(3) <= mux16(reg1(28 to 31), entrada);
sel_aux1(2) <= mux16(reg1(24 to 27), entrada);
sel_aux1(1) <= mux16(reg1(20 to 23), entrada);
sel_aux1(0) <= mux16(reg1(16 to 19), entrada);
sal_arbol(2) <= mux16(sel_aux1, reg1(0 to 15));
sel_aux2(3) <= mux16(reg2(28 to 31), entrada);
sel_aux2(2) <= mux16(reg2(24 to 27), entrada);
sel_aux2(1) <= mux16(reg2(20 to 23), entrada);
sel_aux2(0) <= mux16(reg2(16 to 19), entrada);
sal_arbol(1) <= mux16(sel_aux2, reg2(0 to 15));
sel_aux3(3) <= mux16(reg3(28 to 31), entrada);
sel_aux3(2) <= mux16(reg3(24 to 27), entrada);
sel_aux3(1) <= mux16(reg3(20 to 23), entrada);
sel_aux3(0) <= mux16(reg3(16 to 19), entrada);
sal_arbol(0) <= mux16(sel_aux3, reg3(0 to 15));
sel_aux4(3) <= mux4(reg4(30 to 31), sal_arbol); --arbol de 2do nivel
sel_aux4(2) <= mux4(reg4(26 to 27), sal_arbol);
sel_aux4(1) <= mux4(reg4(22 to 23), sal_arbol);
sel_aux4(0) <= mux4(reg4(18 to 19), sal_arbol);
salida_nivel(2) <= mux16(sel_aux4, reg4(0 to 15));
sel_auxn3(3) <= mux4(regn3(30 to 31), minter_n3); --arboles de 3er nivel
sel_auxn3(2) <= mux4(regn3(26 to 27), minter_n3);
sel_auxn3(1) <= mux4(regn3(22 to 23), minter_n3);
sel_auxn3(0) <= mux4(regn3(18 to 19), minter_n3);
salida_nivel(3) <= mux16(sel_auxn3, regn3(0 to 15));
sel_auxn4(3) <= mux4(regn4(30 to 31), minter_n4); --arboles de 4to nivel
sel_auxn4(2) <= mux4(regn4(26 to 27), minter_n4);
sel_auxn4(1) <= mux4(regn4(22 to 23), minter_n4);
sel_auxn4(0) <= mux4(regn4(18 to 19), minter_n4);
salida_nivel(4) <= mux16(sel_auxn4, regn4(0 to 15));
ram_nivel20:RAMB16_S1 port map(DO => DO_n2(3 downto 3), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(3 downto 3), EN => EN_n2, SSR => SSR, WE => WE_n2(3));
ram_nivel21:RAMB16_S1 port map(DO => DO_n2(2 downto 2), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(2 downto 2), EN => EN_n2, SSR => SSR, WE => WE_n2(2));
ram_nivel22:RAMB16_S1 port map(DO => DO_n2(1 downto 1), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(1 downto 1), EN => EN_n2, SSR => SSR, WE => WE_n2(1));
ram_nivel23:RAMB16_S1 port map(DO => DO_n2(0 downto 0), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(0 downto 0), EN => EN_n2, SSR => SSR, WE => WE_n2(0));
ram_nivel30:RAMB16_S1 port map(DO => DO_n3(3 downto 3), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(3 downto 3), EN => EN_n3, SSR => SSR, WE => WE_n3(3));
ram_nivel31:RAMB16_S1 port map(DO => DO_n3(2 downto 2), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(2 downto 2), EN => EN_n3, SSR => SSR, WE => WE_n3(2));
ram_nivel32:RAMB16_S1 port map(DO => DO_n3(1 downto 1), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(1 downto 1), EN => EN_n3, SSR => SSR, WE => WE_n3(1));
ram_nivel33:RAMB16_S1 port map(DO => DO_n3(0 downto 0), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(0 downto 0), EN => EN_n3, SSR => SSR, WE => WE_n3(0));
ram_nivel40:RAMB16_S1 port map(DO => DO_n4(3 downto 3), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(3 downto 3), EN => EN_n4, SSR => SSR, WE => WE_n4(3));
ram_nivel41:RAMB16_S1 port map(DO => DO_n4(2 downto 2), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(2 downto 2), EN => EN_n4, SSR => SSR, WE => WE_n4(2));
ram_nivel42:RAMB16_S1 port map(DO => DO_n4(1 downto 1), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(1 downto 1), EN => EN_n4, SSR => SSR, WE => WE_n4(1));
ram_nivel43:RAMB16_S1 port map(DO => DO_n4(0 downto 0), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(0 downto 0), EN => EN_n4, SSR => SSR, WE => WE_n4(0));
end Behavioral;

191
Examples/ehw4/logic/mt.vhd Executable file
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@@ -0,0 +1,191 @@
-------------------------------------------------------------------------------
-- --
-- MT32 - Mersenne Twister --
-- Copyright (C) 2007 HT-LAB --
-- --
-- Contact : Use feedback form on the website. --
-- Web: http://www.ht-lab.com --
-- --
-- MT32 files are released under the GNU General Public License. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- --
-- Top Level (Synthesis) --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY mt_mem IS
PORT(
clk : IN std_logic;
ena : IN std_logic;
resetn : IN std_logic;
random : OUT std_logic_vector (31 DOWNTO 0)
);
END mt_mem ;
LIBRARY ieee;
ARCHITECTURE struct OF mt_mem IS
-- Architecture declarations
-- internal signal declarations
signal kk_cnt : std_logic_vector(9 downto 0);
signal km_cnt : std_logic_vector(9 downto 0);
signal kp_cnt : std_logic_vector(9 downto 0);
signal mt_kk31 : std_logic_vector(0 downto 0);
signal mt_kk_s : std_logic_vector(31 downto 0);
signal mt_km : std_logic_vector(31 downto 0);
signal mt_kp : std_logic_vector(30 downto 0);
signal wea : std_logic;
signal wea_s : std_logic_vector(0 downto 0);
signal wr_cnt : std_logic_vector(9 downto 0);
signal xor1_s : std_logic_vector(31 downto 0);
signal xor2_s : std_logic_vector(31 downto 0);
signal xor3_s : std_logic_vector(31 downto 0);
signal y_s : std_logic_vector(31 downto 0);
signal mag01_s : std_logic_vector(31 downto 0);
-- Component Declarations
COMPONENT counters
GENERIC (
M : integer := 397;
N : integer := 623
);
PORT (
clk : IN std_logic ;
resetn : IN std_logic ;
ena : IN std_logic ;
wea : OUT std_logic ;
kk_cnt : OUT std_logic_vector (9 DOWNTO 0);
km_cnt : OUT std_logic_vector (9 DOWNTO 0);
kp_cnt : OUT std_logic_vector (9 DOWNTO 0);
wr_cnt : OUT std_logic_vector (9 DOWNTO 0)
);
END COMPONENT;
COMPONENT dpram624x1
PORT (
addra : IN std_logic_VECTOR (9 DOWNTO 0);
addrb : IN std_logic_VECTOR (9 DOWNTO 0);
clka : IN std_logic;
clkb : IN std_logic;
dina : IN std_logic_VECTOR (0 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
doutb : OUT std_logic_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT dpram624x31
PORT (
addra : IN std_logic_VECTOR (9 DOWNTO 0);
addrb : IN std_logic_VECTOR (9 DOWNTO 0);
clka : IN std_logic;
clkb : IN std_logic;
dina : IN std_logic_VECTOR (30 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
doutb : OUT std_logic_VECTOR (30 DOWNTO 0)
);
END COMPONENT;
COMPONENT dpram624x32
PORT (
addra : IN std_logic_VECTOR (9 DOWNTO 0);
addrb : IN std_logic_VECTOR (9 DOWNTO 0);
clka : IN std_logic;
clkb : IN std_logic;
dina : IN std_logic_VECTOR (31 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
doutb : OUT std_logic_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
wea_s(0) <= wea; -- wonderful VHDL
-- HDL Embedded Text Block 2 XOR_CHAIN1
-- eb1 1
xor1_s <= mt_kk_s XOR ("00000000000"&mt_kk_s(31 downto 11));
xor2_s <= xor1_s XOR (xor1_s(24 downto 0)&"0000000" AND X"9D2C5680");
xor3_s <= xor2_s XOR (xor2_s(16 downto 0)&"000000000000000" AND X"EFC60000");
random <= xor3_s XOR "000000000000000000"&xor3_s(31 downto 18);
-- HDL Embedded Text Block 3 eb3
y_s <= mt_kk31(0)&mt_kp(30 downto 0);
mag01_s <= X"00000000" when y_s(0)='0' else X"9908B0DF";
mt_kk_s <= mt_km XOR ('0'&y_s(31 downto 1)) XOR mag01_s;
-- Instance port mappings.
U_7 : counters
GENERIC MAP (
M => 397,
N => 623
)
PORT MAP (
clk => clk,
resetn => resetn,
ena => ena,
wea => wea,
kk_cnt => kk_cnt,
km_cnt => km_cnt,
kp_cnt => kp_cnt,
wr_cnt => wr_cnt
);
U_0 : dpram624x1
PORT MAP (
clka => clk,
dina => mt_kk_s(31 DOWNTO 31),
addra => wr_cnt,
wea => wea_s,
clkb => clk,
addrb => kk_cnt,
doutb => mt_kk31
);
U_1 : dpram624x31
PORT MAP (
clka => clk,
dina => mt_kk_s(30 DOWNTO 0),
addra => wr_cnt,
wea => wea_s,
clkb => clk,
addrb => kp_cnt,
doutb => mt_kp
);
U_2 : dpram624x32
PORT MAP (
clka => clk,
dina => mt_kk_s,
addra => wr_cnt,
wea => wea_s,
clkb => clk,
addrb => km_cnt,
doutb => mt_km
);
END struct;

96
Examples/ehw4/logic/reg_bank.v Normal file
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`timescale 1ns / 1ps
module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg3, reg4, regMT, error, status, max_lev, max_com, control);
input clk, reset, en, we;
input [7:0] wdBus;
output [7:0] rdBus;
input [4:0] address;
input [31:0] reg0;
input [31:0] reg1;
input [31:0] reg2;
input [31:0] reg3;
input [31:0] reg4;
input [31:0] regMT;
input [16:0] error;
input [7:0] status;
output [15:0] max_com;
output [7:0] max_lev;
output [7:0] control;
reg [7:0] reg_bank [31:0];
reg [7:0] rdBus;
// Read control
always @(posedge clk)
if(reset)
rdBus = 8'h00;
else begin
rdBus = reg_bank[address];
end
// Store Inputs
always @(posedge clk)
begin
if(en) begin
reg_bank[0] = reg0[7:0];
reg_bank[1] = reg0[15:8];
reg_bank[2] = reg0[23:16];
reg_bank[3] = reg0[31:24];
reg_bank[4] = reg1[7:0];
reg_bank[5] = reg1[15:8];
reg_bank[6] = reg1[23:16];
reg_bank[7] = reg1[31:24];
reg_bank[8] = reg2[7:0];
reg_bank[9] = reg2[15:8];
reg_bank[10] = reg2[23:16];
reg_bank[11] = reg2[31:24];
reg_bank[12] = reg3[7:0];
reg_bank[13] = reg3[15:8];
reg_bank[14] = reg3[23:16];
reg_bank[15] = reg3[31:24];
reg_bank[16] = reg4[7:0];
reg_bank[17] = reg4[15:8];
reg_bank[18] = reg4[23:16];
reg_bank[19] = reg4[31:24];
reg_bank[20] = error[7:0];
reg_bank[21] = error[15:8];
reg_bank[22] = { 4'b0, status};
// reg_bank[23] = regMT[7:0];
// reg_bank[24] = regMT[15:8];
// reg_bank[25] = regMT[23:16];
// reg_bank[26] = regMT[31:24];
end
end
assign max_com[7:0] = reg_bank[26];
assign max_com[15:8] = reg_bank[27];
assign max_lev = reg_bank[28];
assign control = reg_bank[29];
// Write control
always @(negedge clk)
if(we & en) begin
case (address)
27: reg_bank[26] = wdBus;
28: reg_bank[27] = wdBus;
29: reg_bank[28] = wdBus;
30: reg_bank[29] = wdBus;
endcase
end
endmodule