carlos 372739573d Connecting FPGA GPIOs to U6 (max3223) allowing RS232 serial communication ...

Change J6-J7 layout allowing the creation of a serial communication channel between ingenic CPU and FPGA.
Changing LCD analog ground, according to LCD datasheet

2010-10-02 11:04:00 -05:00

binaries

Adding evolvable hardware example

2010-10-01 09:03:07 -05:00

course/.docs

aaa

2010-09-12 19:57:04 -05:00

Datasheet

Adding ADC and FPGA Datasheet

2010-04-03 20:51:39 -05:00

docs

Updating schematic PDF file

2010-04-28 18:46:05 -05:00

Examples

Adding evolvable hardware example

2010-10-01 09:03:07 -05:00

KICAD_design_files

Connecting FPGA GPIOs to U6 (max3223) allowing RS232 serial communication

2010-10-02 11:04:00 -05:00

linux-2.6.32.7_sakc

Update SAKC kernel.

2010-03-12 09:59:15 -05:00

lm32/logic

Adding evolvable hardware example

2010-10-01 09:03:07 -05:00

lua/examples

aaa

2010-09-12 19:57:04 -05:00

ORCAD_design_files

making some manufacturer recommendations

2010-08-10 09:49:05 -05:00

plasma

Adding evolvable hardware example

2010-10-01 09:03:07 -05:00

sie_fs

Adding file-system

2010-09-21 17:05:23 -05:00

Software/xc3sprog

Adding new SAKC version, including LED circuit.

2010-05-20 11:49:05 -05:00

u-boot_sakc

Update uboot SAKC

2010-03-13 09:40:17 -05:00

xilinx_lib

Fixing some examples, adding scripts for compiling xilinx libs with ghdl

2010-08-31 09:39:37 -05:00

Description

Hardware Design: SIE, NanoNote derived board with Jz4725 and FPGA for hardware hackers

http://projects.qi-hardware.com/index.php/p/nn-usb-fpga/

24 MiB

Languages

Verilog 39.2%

C 29.2%

C++ 14.3%

VHDL 8.6%

Makefile 2.8%

Other 5.7%