mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-01 08:24:40 +02:00
[xbboot] just some cleanup, make the stage1 size less then 8KB
This commit is contained in:
parent
0659b47c28
commit
19ce238122
@ -154,20 +154,17 @@ void pll_init_4760()
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| CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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serial_puts("cfcr = ");
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serial_put_hex(cfcr);
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serial_puts("plcr1 = ");
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serial_put_hex(plcr1);
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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while(!(REG_CPM_CPPSR & (1 << 29)));
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#ifdef DEBUG
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serial_puts("REG_CPM_CPCCR = ");
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serial_put_hex(REG_CPM_CPCCR);
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serial_puts("REG_CPM_CPPCR = ");
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serial_put_hex(REG_CPM_CPPCR);
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#endif
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}
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#if (defined(CONFIG_SDRAM_MDDR)||defined(CONFIG_SDRAM_DDR1)||defined(CONFIG_SDRAM_DDR2))
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@ -228,10 +225,8 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag)
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data_expect = gen_verify_data(i);
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dsrc = REG32(addr1);
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ddst = REG32(addr2);
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if ((dsrc != data_expect)
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|| (ddst != data_expect)) {
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#if 1
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//serial_puts("wrong data at34:");
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if ((dsrc != data_expect) || (ddst != data_expect)) {
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#if DEBUG
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serial_put_hex(addr2);
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serial_puts("data:");
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serial_put_hex(data_expect);
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@ -239,7 +234,6 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag)
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serial_put_hex(dsrc);
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serial_puts("dst");
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serial_put_hex(ddst);
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#endif
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err = 1;
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if(!print_flag)
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@ -249,11 +243,10 @@ static int dma_check_result(void *src, void *dst, int size,int print_flag)
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addr1 += 4;
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addr2 += 4;
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}
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// serial_puts("check passed!");
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return err;
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}
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#if 0
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#if DEBUG
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void dump_jz_dma_channel(unsigned int dmanr)
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{
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@ -284,7 +277,6 @@ void dump_jz_dma_channel(unsigned int dmanr)
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serial_puts(" DMADBR = ");
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serial_put_hex(REG_DMAC_DMADBR(dmanr/HALF_DMA_NUM));
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}
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#endif
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void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, int size)
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{
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@ -304,6 +296,140 @@ void dma_nodesc_test_single(int dma_chan, int dma_src_addr, int dma_dst_addr, in
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REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
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}
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static void ddrc_regs_print(void)
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{
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serial_puts("\nDDRC REGS:\n");
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serial_puts("REG_DDRC_ST \t\t=");
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serial_put_hex(REG_DDRC_ST);
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serial_puts("REG_DDRC_CFG \t\t=");
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serial_put_hex( REG_DDRC_CFG);
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serial_puts("REG_DDRC_CTRL \t\t=");
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serial_put_hex(REG_DDRC_CTRL);
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serial_puts("REG_DDRC_LMR \t\t=");
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serial_put_hex(REG_DDRC_LMR);
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serial_puts("REG_DDRC_TIMING1 \t=");
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serial_put_hex(REG_DDRC_TIMING1);
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serial_puts("REG_DDRC_TIMING2 \t=");
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serial_put_hex(REG_DDRC_TIMING2);
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serial_puts("REG_DDRC_REFCNT \t\t=");
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serial_put_hex(REG_DDRC_REFCNT);
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serial_puts("REG_DDRC_DQS \t\t=");
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serial_put_hex(REG_DDRC_DQS);
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serial_puts("REG_DDRC_DQS_ADJ \t=");
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serial_put_hex(REG_DDRC_DQS_ADJ);
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serial_puts("REG_DDRC_MMAP0 \t\t=");
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serial_put_hex(REG_DDRC_MMAP0);
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serial_puts("REG_DDRC_MMAP1 \t\t=");
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serial_put_hex(REG_DDRC_MMAP1);
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serial_puts("REG_DDRC_MDELAY \t\t=");
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serial_put_hex(REG_DDRC_MDELAY);
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serial_puts("REG_EMC_PMEMPS2 \t\t=");
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serial_put_hex(REG_EMC_PMEMPS2);
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}
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static int dma_memcpy_test(int channle_0, int channle_1) {
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int i, err = 0, banks;
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unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST;
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volatile unsigned int tmp;
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register unsigned int cpu_clk;
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long int memsize, banksize, testsize;
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int channel;
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#ifndef CONFIG_DDRC
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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memsize = initdram(0);
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banksize = memsize/banks;
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testsize = 4096;
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DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0;
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DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize;
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DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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cpu_clk = ARG_CPU_SPEED;
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// for(channel = 0; channel < MAX_DMA_NUM; channel++) {
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// MDMA
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REG_MDMAC_DMACR = DMAC_DMACR_DMAE;
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// COMMON DMA
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//REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */
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//REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */
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// Write A0
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addr = DDR_DMA0_SRC;
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for (i = 0; i < testsize; i += 4) {
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*(volatile unsigned int *)addr = (i/4*0x11111111);
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//*(volatile unsigned int *)addr = addr;
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addr += 4;
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}
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// Write A2
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addr = DDR_DMA1_SRC;
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for (i = 0; i < testsize; i += 4) {
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*(volatile unsigned int *)addr = (i/4*0x11111111);
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//*(volatile unsigned int *)addr = addr;
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addr += 4;
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}
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// MDMA
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REG_MDMAC_DMACR = 0;
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// COMMON DMA
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//REG_DMAC_DMACR(0) = 0;
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//REG_DMAC_DMACR(1) = 0;
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/* Init target buffer */
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jzmemset((void *)DDR_DMA0_DST, 0, testsize);
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jzmemset((void *)DDR_DMA1_DST, 0, testsize);
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// Set DMA1 for moving data from A0 -> A1
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dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE);
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// Set DMA2 for moving data from A2 -> A3
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dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE);
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// Start DMA0
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REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
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// Wait for DMA0 finishing
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while(REG_DMAC_DTCR(0));
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// Start DMA1
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REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
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// Read from A1 & check
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err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize);
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REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */
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if (err != 0) {
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serial_puts("DMA0: err!\n");
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//return err;
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}
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// Wait for DMA1 finishing
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while(REG_DMAC_DTCR(1));
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// Read from A3 & check
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err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize);
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REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */
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if (err != 0) {
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serial_puts("DMA1: err!\n");
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//return err;
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}
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serial_puts("TEST PASSED\n\n");
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tmp = (cpu_clk / 1000000) * 1;
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while (tmp--);
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// }
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return err;
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}
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#endif
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void dma_nodesc_test(int dma_chan, int dma_src_addr, int dma_dst_addr, int size)
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{
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@ -386,8 +512,8 @@ for(times = 0; times < banks; times++) {
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dma_nodesc_test(0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize);
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#endif
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#ifdef DMA_CHANNEL1_EN
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//jzmemset((void *)DDR_DMA1_DST, 0, testsize);
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//dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize);
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jzmemset((void *)DDR_DMA1_DST, 0, testsize);
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dma_nodesc_test(1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize);
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#endif
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REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */
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@ -427,38 +553,6 @@ for(times = 0; times < banks; times++) {
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}
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return err;
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}
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#if 0
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static void ddrc_regs_print(void)
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{
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serial_puts("\nDDRC REGS:\n");
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serial_puts("REG_DDRC_ST \t\t=");
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serial_put_hex(REG_DDRC_ST);
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serial_puts("REG_DDRC_CFG \t\t=");
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serial_put_hex( REG_DDRC_CFG);
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serial_puts("REG_DDRC_CTRL \t\t=");
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serial_put_hex(REG_DDRC_CTRL);
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serial_puts("REG_DDRC_LMR \t\t=");
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serial_put_hex(REG_DDRC_LMR);
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serial_puts("REG_DDRC_TIMING1 \t=");
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serial_put_hex(REG_DDRC_TIMING1);
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serial_puts("REG_DDRC_TIMING2 \t=");
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serial_put_hex(REG_DDRC_TIMING2);
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serial_puts("REG_DDRC_REFCNT \t\t=");
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serial_put_hex(REG_DDRC_REFCNT);
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serial_puts("REG_DDRC_DQS \t\t=");
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serial_put_hex(REG_DDRC_DQS);
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serial_puts("REG_DDRC_DQS_ADJ \t=");
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serial_put_hex(REG_DDRC_DQS_ADJ);
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serial_puts("REG_DDRC_MMAP0 \t\t=");
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serial_put_hex(REG_DDRC_MMAP0);
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serial_puts("REG_DDRC_MMAP1 \t\t=");
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serial_put_hex(REG_DDRC_MMAP1);
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serial_puts("REG_DDRC_MDELAY \t\t=");
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serial_put_hex(REG_DDRC_MDELAY);
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serial_puts("REG_EMC_PMEMPS2 \t\t=");
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serial_put_hex(REG_EMC_PMEMPS2);
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}
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#endif
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void ddr_mem_init(int msel, int hl, int tsel, int arg)
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{
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@ -743,107 +837,7 @@ static int check_result(void *src, void *dst, int size)
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return err;
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}
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static int dma_memcpy_test(int channle_0, int channle_1) {
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int i, err = 0, banks;
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unsigned int addr, DDR_DMA0_SRC, DDR_DMA0_DST, DDR_DMA1_SRC, DDR_DMA1_DST;
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volatile unsigned int tmp;
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register unsigned int cpu_clk;
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long int memsize, banksize, testsize;
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int channel;
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#ifndef CONFIG_DDRC
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banks = (ARG_BANK_ADDR_2BIT ? 4 : 2) *(CONFIG_NR_DRAM_BANKS);
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#else
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banks = (DDR_BANK8 ? 8 : 4) *(DDR_CS0EN + DDR_CS1EN);
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#endif
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memsize = initdram(0);
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banksize = memsize/banks;
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testsize = 4096;
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DDR_DMA0_SRC = DDR_DMA_BASE + banksize*0;
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DDR_DMA0_DST = DDR_DMA_BASE + banksize*0 + testsize;
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DDR_DMA1_SRC = DDR_DMA_BASE + banksize*(banks - 1) + testsize*2;
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DDR_DMA1_DST = DDR_DMA_BASE + banksize*(banks - 1) + testsize*3;
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cpu_clk = ARG_CPU_SPEED;
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// for(channel = 0; channel < MAX_DMA_NUM; channel++) {
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// MDMA
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REG_MDMAC_DMACR = DMAC_DMACR_DMAE;
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// COMMON DMA
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//REG_DMAC_DMACR(0) = DMAC_DMACR_DMAE; /* global DMA enable bit */
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//REG_DMAC_DMACR(1) = DMAC_DMACR_DMAE; /* global DMA enable bit */
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// Write A0
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addr = DDR_DMA0_SRC;
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for (i = 0; i < testsize; i += 4) {
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*(volatile unsigned int *)addr = (i/4*0x11111111);
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//*(volatile unsigned int *)addr = addr;
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addr += 4;
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}
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// Write A2
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addr = DDR_DMA1_SRC;
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for (i = 0; i < testsize; i += 4) {
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*(volatile unsigned int *)addr = (i/4*0x11111111);
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//*(volatile unsigned int *)addr = addr;
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addr += 4;
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}
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// MDMA
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REG_MDMAC_DMACR = 0;
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// COMMON DMA
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//REG_DMAC_DMACR(0) = 0;
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//REG_DMAC_DMACR(1) = 0;
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/* Init target buffer */
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jzmemset((void *)DDR_DMA0_DST, 0, testsize);
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jzmemset((void *)DDR_DMA1_DST, 0, testsize);
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// Set DMA1 for moving data from A0 -> A1
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dma_data_move(channle_0, DDR_DMA0_SRC, DDR_DMA0_DST, testsize, DMAC_DCMD_DS_32BYTE);
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// Set DMA2 for moving data from A2 -> A3
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dma_data_move(channle_1, DDR_DMA1_SRC, DDR_DMA1_DST, testsize, DMAC_DCMD_DS_64BYTE);
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// Start DMA0
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REG_DMAC_DCCSR(0) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
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// Wait for DMA0 finishing
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while(REG_DMAC_DTCR(0));
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// Start DMA1
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REG_DMAC_DCCSR(1) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
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// Read from A1 & check
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err = check_result((void *)DDR_DMA0_SRC, (void *)DDR_DMA0_DST, testsize);
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REG_DMAC_DCCSR(0) &= ~DMAC_DCCSR_EN; /* disable DMA */
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if (err != 0) {
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serial_puts("DMA0: err!\n");
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//return err;
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}
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// Wait for DMA1 finishing
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while(REG_DMAC_DTCR(1));
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// Read from A3 & check
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err = check_result((void *)DDR_DMA1_SRC, (void *)DDR_DMA1_DST, testsize);
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REG_DMAC_DCCSR(1) &= ~DMAC_DCCSR_EN; /* disable DMA */
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if (err != 0) {
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serial_puts("DMA1: err!\n");
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//return err;
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}
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serial_puts("TEST PASSED\n\n");
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tmp = (cpu_clk / 1000000) * 1;
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while (tmp--);
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// }
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return err;
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}
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#endif/* CONFIG_SDRAM_MDDR */
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#if (defined(CONFIG_SDRAM_MDDR) || defined(CONFIG_SDRAM_DDR1) || defined(CONFIG_SDRAM_DDR2))
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#define DEF_DDR_CVT 0
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@ -852,51 +846,50 @@ unsigned int testall = 0;
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/* DDR sdram init */
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void sdram_init_4760(void)
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{
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serial_puts("REG_CPM_CPCCR = ");
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serial_put_hex(REG_CPM_CPCCR);
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serial_puts("REG_CPM_CPPCR = ");
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serial_put_hex(REG_CPM_CPPCR);
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//add driver power
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REG_EMC_PMEMPS2 |= (3 << 18);
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REG_DMAC_DMADCKE(0) = 0x3f;
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REG_DMAC_DMADCKE(1) = 0x3f;
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int i, num = 0, tsel = 0, msel, hl;
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#if defined(CONFIG_FPGA)
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int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1, max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0, tsel0 = 0, tsel1 = 0;
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#endif
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volatile unsigned int tmp_cnt;
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register unsigned int tmp, cpu_clk, mem_clk, ddr_twr, ns, ns_int;
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register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0, init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0;
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register unsigned int ddrc_timing1_reg=0, ddrc_timing2_reg=0;
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register unsigned int init_ddrc_refcnt=0, init_ddrc_dqs=0, init_ddrc_ctrl=0;
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register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg;
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register unsigned int mem_base0, mem_base1, mem_mask0, mem_mask1;
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#if defined(CONFIG_FPGA)
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int cvt = DEF_DDR_CVT, cvt_cnt0 = 0, cvt_cnt1 = 1;
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int max = 0, max0 = 0, max1 = 0, min0 = 0, min1 = 0;
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int tsel0 = 0, tsel1 = 0;
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struct ddr_delay_sel_t ddr_delay_sel[] = {
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{0, 1}, {0, 0}, {1, 1}, {1, 0},
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{2, 1}, {2, 0}, {3, 1}, {3, 0}
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||||
};
|
||||
#endif
|
||||
register unsigned int memsize, ddrc_mmap0_reg, ddrc_mmap1_reg, mem_base0, mem_base1, mem_mask0, mem_mask1;
|
||||
|
||||
testall = 0;
|
||||
cpu_clk = ARG_CPU_SPEED;
|
||||
|
||||
#ifdef DEBUG
|
||||
ddrc_regs_print();
|
||||
#endif
|
||||
|
||||
cpu_clk = ARG_CPU_SPEED;
|
||||
|
||||
#if defined(CONFIG_FPGA)
|
||||
mem_clk = ARG_EXTAL / CFG_DIV;
|
||||
#else
|
||||
mem_clk = __cpm_get_mclk();
|
||||
#endif
|
||||
|
||||
serial_puts("mem_clk = ");
|
||||
serial_put_hex(mem_clk);
|
||||
#if defined(CONFIG_FPGA)
|
||||
ns = 7;
|
||||
#else
|
||||
mem_clk = __cpm_get_mclk();
|
||||
ns = 1000000000 / mem_clk; /* ns per tck ns <= real value */
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
serial_puts("mem_clk = ");
|
||||
serial_put_hex(mem_clk);
|
||||
#endif
|
||||
|
||||
/* ACTIVE to PRECHARGE command period */
|
||||
tmp = (DDR_tRAS%ns == 0) ? (DDR_tRAS/ns) : (DDR_tRAS/ns+1);
|
||||
if (tmp < 1) tmp = 1;
|
||||
@ -1047,20 +1040,12 @@ void sdram_init_4760(void)
|
||||
while (tmp_cnt--);
|
||||
|
||||
{
|
||||
//ddrc_regs_print();
|
||||
int result = 0;
|
||||
serial_puts("ddr test:");
|
||||
result = ddr_dma_test(0);
|
||||
if(result != 0)
|
||||
{
|
||||
serial_puts("ddr test fail\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
serial_puts("ddr test ok\n");
|
||||
}
|
||||
|
||||
#if 0
|
||||
serial_puts("FAIL!\n");
|
||||
#if DEBUG
|
||||
serial_puts("result:");
|
||||
serial_put_hex(result);
|
||||
serial_put_hex(num);
|
||||
@ -1083,15 +1068,17 @@ void sdram_init_4760(void)
|
||||
break;
|
||||
}
|
||||
if (tsel == 3 && num == 0)
|
||||
serial_puts("\n\nDDR INIT ERROR: can't find a suitable mask delay.\n");
|
||||
serial_puts("DDR INIT ERROR\n"); /* can't find a suitable mask delay. */
|
||||
index = 0;
|
||||
for (i = 0; i < num; i++) {
|
||||
index += mem_index[i];
|
||||
serial_put_hex(mem_index[i]);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
serial_puts("index-1:");
|
||||
serial_put_hex(index);
|
||||
#endif
|
||||
|
||||
if (num)
|
||||
index /= num;
|
||||
@ -1101,12 +1088,14 @@ void sdram_init_4760(void)
|
||||
hl = ((index/2)&1)^1;
|
||||
quar = index&1;
|
||||
|
||||
#ifdef DEBUG
|
||||
serial_puts("tsel");
|
||||
serial_put_hex(tsel);
|
||||
serial_puts("num");
|
||||
serial_put_hex(num);
|
||||
serial_puts("index-2:");
|
||||
serial_put_hex(index);
|
||||
#endif
|
||||
|
||||
/* reset ddrc_controller */
|
||||
REG_DDRC_CTRL = DDRC_CTRL_RESET;
|
||||
|
@ -22,8 +22,6 @@
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
|
||||
|
||||
#define CONFIG_MOBILE_SDRAM 1 /* use mobile sdram */
|
||||
|
||||
#ifndef CONFIG_MOBILE_SDRAM
|
||||
// SDRAM paramters
|
||||
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
|
||||
|
Loading…
Reference in New Issue
Block a user