mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2024-12-23 13:30:48 +02:00
add read configure file code
This commit is contained in:
parent
4f47892d13
commit
60cb0eb193
@ -31,11 +31,11 @@ endif
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CC = gcc
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CFLAGS += -pedantic -Wall -W -O1 -g3 -std=gnu99
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LDFLAGS += -lusb
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LDFLAGS += -lusb -lconfuse
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BINARY_NAME = inflash
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SRC_C= main.c usb.c
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SRC_H= main.h usb.h
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SRC_H= main.h usb.h usb_boot_defines.h
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SRC_O= $(SRC_C:.c=.o)
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$(BINARY_NAME): $(SRC_O) $(SRC_H) Makefile
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@ -23,6 +23,7 @@
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#include "main.h"
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#include "usb.h"
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#include "usb_boot_defines.h"
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#include <stdio.h>
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#include <string.h>
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@ -32,9 +33,48 @@
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#include <fcntl.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <confuse.h>
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fw_args_t fw_args;
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int load_file(struct ingenic_dev *ingenic_dev, const char *file_path)
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static int parse_configure(char * file_path)
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{
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cfg_opt_t opts[] = {
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CFG_SIMPLE_INT("EXTCLK", &fw_args.ext_clk),
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CFG_SIMPLE_INT("CPUSPEED", &fw_args.cpu_speed),
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CFG_SIMPLE_INT("PHMDIV", &fw_args.phm_div),
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CFG_SIMPLE_INT("BOUDRATE", &fw_args.boudrate),
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CFG_SIMPLE_INT("USEUART", &fw_args.use_uart),
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CFG_SIMPLE_INT("BUSWIDTH", &fw_args.bus_width),
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CFG_SIMPLE_INT("BANKS", &fw_args.bank_num),
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CFG_SIMPLE_INT("ROWADDR", &fw_args.row_addr),
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CFG_SIMPLE_INT("COLADDR", &fw_args.col_addr),
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CFG_SIMPLE_INT("ISMOBILE", &fw_args.is_mobile),
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CFG_SIMPLE_INT("ISBUSSHARE", &fw_args.is_busshare),
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CFG_SIMPLE_INT("DEBUGOPS", &fw_args.debug_ops),
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CFG_SIMPLE_INT("PINNUM", &fw_args.pin_num),
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CFG_SIMPLE_INT("START", &fw_args.start),
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CFG_SIMPLE_INT("SIZE", &fw_args.size),
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CFG_END()
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};
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cfg_t *cfg;
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cfg = cfg_init(opts, 0);
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if (cfg_parse(cfg, file_path) == CFG_PARSE_ERROR)
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return -1;
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cfg_free(cfg);
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total_size = (unsigned int)(2 << (fw_args.row_addr + fw_args.col_addr - 1)) * 2
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* (fw_args.bank_num + 1) * 2
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* (2 - fw_args.bus_width);
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return 1;
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}
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static int load_file(struct ingenic_dev *ingenic_dev, const char *file_path)
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{
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struct stat fstat;
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int fd, status, res = -1;
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@ -73,6 +113,8 @@ int load_file(struct ingenic_dev *ingenic_dev, const char *file_path)
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goto close;
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}
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memcpy(ingenic_dev->file_buff + 8, &fw_args, sizeof(fw_args_t));
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res = 1;
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close:
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@ -84,6 +126,7 @@ out:
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int main(int argc, char **argv)
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{
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struct ingenic_dev ingenic_dev;
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int res = EXIT_FAILURE;
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if ((getuid()) || (getgid())) {
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@ -92,6 +135,10 @@ int main(int argc, char **argv)
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}
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memset(&ingenic_dev, 0, sizeof(struct ingenic_dev));
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memset(&fw_args, 0, sizeof(fw_args_t));
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if (parse_configure(CONFIG_FILE_PATH) < 1)
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goto out;
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if (usb_ingenic_init(&ingenic_dev) < 1)
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goto out;
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@ -99,12 +146,22 @@ int main(int argc, char **argv)
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if (usb_get_ingenic_cpu(&ingenic_dev) < 1)
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goto out;
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/* now we upload the usb boot stage1 */
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if (load_file(&ingenic_dev, STAGE1_FILE_PATH) < 1)
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goto out;
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if (usb_ingenic_upload(&ingenic_dev, 1) < 1)
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goto cleanup;
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#if 0
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/* now we upload the usb boot stage2 */
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sleep(1);
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if (load_file(&ingenic_dev, STAGE2_FILE_PATH) < 1)
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goto cleanup;
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if (usb_ingenic_upload(&ingenic_dev, 2) < 1)
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goto cleanup;
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#endif
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res = EXIT_SUCCESS;
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cleanup:
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@ -23,11 +23,12 @@
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#include <stdint.h>
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#define VENDOR_ID 0x601a
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#define PRODUCT_ID 0x4740
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#define STAGE1_FILE_PATH "fw.bin"
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#define STAGE2_FILE_PATH "usb_boot.bin"
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#define CONFIG_FILE_PATH "usb_boot.cfg"
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struct ingenic_dev {
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@ -38,3 +39,6 @@ struct ingenic_dev {
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char *file_buff;
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int file_len;
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};
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unsigned total_size;
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@ -23,6 +23,7 @@
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#include "main.h"
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#include "usb.h"
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#include "usb_boot_defines.h"
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#include <usb.h>
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#include <stdio.h>
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@ -150,7 +151,7 @@ int usb_get_ingenic_cpu(struct ingenic_dev *ingenic_dev)
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if (status != sizeof(ingenic_dev->cpu_info_buff)) {
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fprintf(stderr, "Error - can't retrieve Ingenic CPU information: %i\n", status);
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goto out;
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return status;
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}
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printf("CPU data: %02x, %02x, %02x, %02x, %02x, %02x, %02x, %02x : %s\n",
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@ -160,22 +161,44 @@ int usb_get_ingenic_cpu(struct ingenic_dev *ingenic_dev)
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ingenic_dev->cpu_info_buff[6], ingenic_dev->cpu_info_buff[7],
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ingenic_dev->cpu_info_buff);
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status = 1;
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return 1;
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}
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out:
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return status;
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int usb_ingenic_flush_cache(struct ingenic_dev *ingenic_dev)
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{
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int status;
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status = usb_control_msg(ingenic_dev->usb_handle,
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/* bmRequestType */ USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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/* bRequest */ VR_FLUSH_CACHES,
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/* wValue */ 0,
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/* wIndex */ 0,
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/* Data */ 0,
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/* wLength */ 0,
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USB_TIMEOUT);
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if (status != sizeof(ingenic_dev->cpu_info_buff)) {
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fprintf(stderr, "Error - can't flush cache: %i\n", status);
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return status;
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}
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return 1;
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}
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int usb_ingenic_upload(struct ingenic_dev *ingenic_dev, int stage)
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{
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int status;
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unsigned int stage2_addr;
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stage2_addr = total_size + 0x80000000;
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stage2_addr -= CODE_SIZE;
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/* tell the device the RAM address to store the file */
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status = usb_control_msg(ingenic_dev->usb_handle,
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/* bmRequestType */ USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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/* bRequest */ VR_SET_DATA_ADDRESS,
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/* wValue */ (stage == 1 ? STAGE1_ADDR_MSB : STAGE2_ADDR_MSB),
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/* wIndex */ (stage == 1 ? STAGE1_ADDR_LSB : STAGE2_ADDR_LSB),
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/* wValue */ STAGE_ADDR_MSB(stage == 1 ? 0x80002000 : stage2_addr),
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/* wIndex */ STAGE_ADDR_LSB(stage == 1 ? 0x80002000 : stage2_addr),
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/* Data */ 0,
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/* wLength */ 0,
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USB_TIMEOUT);
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@ -212,12 +235,17 @@ int usb_ingenic_upload(struct ingenic_dev *ingenic_dev, int stage)
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return -1;
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}
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if (stage != 1) {
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usb_get_ingenic_cpu(ingenic_dev);
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usb_ingenic_flush_cache(ingenic_dev);
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}
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/* tell the device to start the uploaded device */
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status = usb_control_msg(ingenic_dev->usb_handle,
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/* bmRequestType */ USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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/* bRequest */ (stage == 1 ? VR_PROGRAM_START1 : VR_PROGRAM_START2),
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/* wValue */ (stage == 1 ? STAGE1_ADDR_MSB : STAGE2_ADDR_MSB),
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/* wIndex */ (stage == 1 ? STAGE1_ADDR_LSB : STAGE2_ADDR_LSB),
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/* wValue */ STAGE_ADDR_MSB(stage == 1 ? 0x80002000 : stage2_addr),
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/* wIndex */ STAGE_ADDR_LSB(stage == 1 ? 0x80002000 : stage2_addr),
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/* Data */ 0,
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/* wLength */ 0,
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USB_TIMEOUT);
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@ -227,6 +255,7 @@ int usb_ingenic_upload(struct ingenic_dev *ingenic_dev, int stage)
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goto out;
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}
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usb_get_ingenic_cpu(ingenic_dev);
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status = 1;
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out:
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@ -35,10 +35,8 @@
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#define VR_CONFIGRATION 0x09
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#define VR_GET_NUM 0x0a
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#define STAGE1_ADDR_MSB (0x80002000 >> 16)
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#define STAGE1_ADDR_LSB (0x80002000 & 0xffff)
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#define STAGE2_ADDR_MSB 0x8000
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#define STAGE2_ADDR_LSB 0x0000
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#define STAGE_ADDR_MSB(addr) ((addr) >> 16)
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#define STAGE_ADDR_LSB(addr) ((addr) & 0xffff)
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#define USB_PACKET_SIZE 512
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#define USB_TIMEOUT 5000
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@ -35,19 +35,19 @@ ISMOBILE = 0 #Define whether SDRAM is mobile SDRAM, this only valid for Jz4750 ,
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ISBUSSHARE = 1 #Define whether SDRAM bus share with NAND 1:shared 0:unshared
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# [NAND]
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BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32)
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ROWCYCLES = 3 #The row address cycles (2|3)
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PAGESIZE = 2048 #The page size of the NAND chip in bytes(512|2048|4096)
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PAGEPERBLOCK = 128 #The page number per block
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FORCEERASE = 1 #The force to erase flag (0|1)
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OOBSIZE = 64 #oob size in byte
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ECCPOS = 6 #Specify the ECC offset inside the oob data (0-[oobsize-1])
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BADBLACKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1])
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BADBLACKPAGE = 127 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
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PLANENUM = 1 #The planes number of target nand flash
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BCHBIT = 4 #Specify the hardware BCH algorithm for 4750 (4|8)
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WPPIN = 0 #Specify the write protect pin number
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BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore
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# BUSWIDTH = 8 #The width of the NAND flash chip in bits (8|16|32)
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# ROWCYCLES = 3 #The row address cycles (2|3)
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# PAGESIZE = 2048 #The page size of the NAND chip in bytes(512|2048|4096)
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# PAGEPERBLOCK = 128 #The page number per block
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# FORCEERASE = 1 #The force to erase flag (0|1)
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# OOBSIZE = 64 #oob size in byte
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# ECCPOS = 6 #Specify the ECC offset inside the oob data (0-[oobsize-1])
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# BADBLACKPOS = 0 #Specify the badblock flag offset inside the oob (0-[oobsize-1])
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# BADBLACKPAGE = 127 #Specify the page number of badblock flag inside a block(0-[PAGEPERBLOCK-1])
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# PLANENUM = 1 #The planes number of target nand flash
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# BCHBIT = 4 #Specify the hardware BCH algorithm for 4750 (4|8)
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# WPPIN = 0 #Specify the write protect pin number
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# BLOCKPERCHIP = 0 #Specify the block number per chip,0 means ignore
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# [END]
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