mirror of
git://projects.qi-hardware.com/xburst-tools.git
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cleanup head files
remove: archdefs.h mips.h mipsregs.h sysdefs.h Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
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Xiangfu Liu
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@ -1,820 +0,0 @@
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/**************************************************************************
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* *
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* PROJECT : MIPS port for uC/OS-II *
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* *
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* MODULE : MIPS.h *
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* *
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* AUTHOR : Michael Anburaj *
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* URL : http://geocities.com/michaelanburaj/ *
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* EMAIL: michaelanburaj@hotmail.com *
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* *
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* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
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* *
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* TOOL-CHAIN : SDE & Cygnus *
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* *
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* DESCRIPTION : *
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* MIPS processor definitions. *
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* The basic CPU definitions are found in the file archdefs.h, which *
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* is included by mips.h. *
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* *
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* mips.h implements aliases for some of the definitions in archdefs.h *
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* and adds various definitions. *
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* *
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**************************************************************************/
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#ifndef __MIPS_H__
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#define __MIPS_H__
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#include "archdefs.h"
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/* ********************************************************************* */
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/* Module configuration */
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/* ********************************************************************* */
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/* Interface macro & data definition */
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#ifndef MSK
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#define MSK(n) ((1 << (n)) - 1)
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#endif
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/* CPU registers */
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#define SYS_CPUREG_ZERO 0
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#define SYS_CPUREG_AT 1
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#define SYS_CPUREG_V0 2
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#define SYS_CPUREG_V1 3
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#define SYS_CPUREG_A0 4
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#define SYS_CPUREG_A1 5
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#define SYS_CPUREG_A2 6
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#define SYS_CPUREG_A3 7
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#define SYS_CPUREG_T0 8
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#define SYS_CPUREG_T1 9
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#define SYS_CPUREG_T2 10
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#define SYS_CPUREG_T3 11
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#define SYS_CPUREG_T4 12
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#define SYS_CPUREG_T5 13
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#define SYS_CPUREG_T6 14
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#define SYS_CPUREG_T7 15
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#define SYS_CPUREG_S0 16
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#define SYS_CPUREG_S1 17
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#define SYS_CPUREG_S2 18
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#define SYS_CPUREG_S3 19
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#define SYS_CPUREG_S4 20
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#define SYS_CPUREG_S5 21
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#define SYS_CPUREG_S6 22
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#define SYS_CPUREG_S7 23
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#define SYS_CPUREG_T8 24
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#define SYS_CPUREG_T9 25
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#define SYS_CPUREG_K0 26
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#define SYS_CPUREG_K1 27
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#define SYS_CPUREG_GP 28
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#define SYS_CPUREG_SP 29
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#define SYS_CPUREG_S8 30
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#define SYS_CPUREG_FP SYS_CPUREG_S8
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#define SYS_CPUREG_RA 31
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/* CPU register fp ($30) has an alias s8 */
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#define s8 fp
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/* Aliases for System Control Coprocessor (CP0) registers */
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#define C0_INDEX C0_Index
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#define C0_RANDOM C0_Random
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#define C0_ENTRYLO0 C0_EntryLo0
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#define C0_ENTRYLO1 C0_EntryLo1
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#define C0_CONTEXT C0_Context
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#define C0_PAGEMASK C0_PageMask
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#define C0_WIRED C0_Wired
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#define C0_BADVADDR C0_BadVAddr
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#define C0_COUNT C0_Count
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#define C0_ENTRYHI C0_EntryHi
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#define C0_COMPARE C0_Compare
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#define C0_STATUS C0_Status
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#define C0_CAUSE C0_Cause
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#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
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#undef C0_PRID
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#endif
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#define C0_PRID C0_PRId
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#define C0_CONFIG C0_Config
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#define C0_CONFIG1 C0_Config1
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#define C0_LLADDR C0_LLAddr
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#define C0_WATCHLO C0_WatchLo
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#define C0_WATCHHI C0_WatchHi
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#define C0_DEBUG C0_Debug
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#define C0_PERFCNT C0_PerfCnt
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#define C0_ERRCTL C0_ErrCtl
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#define C0_CACHEERR C0_CacheErr
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#define C0_TAGLO C0_TagLo
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#define C0_DATALO C0_DataLo
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#define C0_TAGHI C0_TagHi
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#define C0_DATAHI C0_DataHi
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#define C0_ERROREPC C0_ErrorEPC
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#if 0
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#define C0_DESAVE C0_DESAVE
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#define C0_EPC C0_EPC
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#define C0_DEPC C0_DEPC
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#endif
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/* System Control Coprocessor (CP0) registers select fields */
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#define C0_INDEX_SEL 0 /* TLB Index */
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#define C0_RANDOM_SEL 0 /* TLB Random */
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#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
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#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
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#define C0_CONTEXT_SEL 0 /* Context */
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#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
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#define C0_WIRED_SEL 0 /* TLB Wired */
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#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
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#define C0_COUNT_SEL 0 /* Count */
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#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
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#define C0_COMPARE_SEL 0 /* Compare */
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#define C0_STATUS_SEL 0 /* Processor Status */
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#define C0_CAUSE_SEL 0 /* Exception Cause */
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#define C0_EPC_SEL 0 /* Exception PC */
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#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
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#define C0_CONFIG_SEL 0 /* Config */
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#define C0_CONFIG1_SEL 1 /* Config1 */
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#define C0_LLADDR_SEL 0 /* LLAddr */
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#define C0_WATCHLO_SEL 0 /* WatchpointLo */
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#define C0_WATCHHI_SEL 0 /* WatchpointHi */
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#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
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#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
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#define C0_PERFCNT_SEL 0 /* Performance counter interface */
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#define C0_ERRCTL_SEL 0 /* ERRCTL */
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#define C0_CACHEERR_SEL 0 /* CacheErr */
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#define C0_TAGLO_SEL 0 /* TagLo */
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#define C0_DATALO_SEL 1 /* DataLo */
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#define C0_DTAGLO_SEL 2 /* DTagLo */
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#define C0_TAGHI_SEL 0 /* TagHi */
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#define C0_DATAHI_SEL 1 /* DataHi */
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#define C0_DTAGHI_SEL 2 /* DTagHi */
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#define C0_ERROREPC_SEL 0 /* ErrorEPC */
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#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
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/* C0_CONFIG register encoding */
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#define C0_CONFIG_M_SHF S_ConfigMore
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#define C0_CONFIG_M_MSK M_ConfigMore
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#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
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#define C0_CONFIG_BE_SHF S_ConfigBE
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#define C0_CONFIG_BE_MSK M_ConfigBE
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#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
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#define C0_CONFIG_AT_SHF S_ConfigAT
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#define C0_CONFIG_AT_MSK M_ConfigAT
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#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
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#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
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#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
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#define C0_CONFIG_AR_SHF S_ConfigAR
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#define C0_CONFIG_AR_MSK M_ConfigAR
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#define C0_CONFIG_MT_SHF S_ConfigMT
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#define C0_CONFIG_MT_MSK M_ConfigMT
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#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
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#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
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#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
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#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
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#define C0_CONFIG_K0_SHF S_ConfigK0
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#define C0_CONFIG_K0_MSK M_ConfigK0
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#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
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#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
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#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
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#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
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#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
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#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
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#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
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#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
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/* WC field.
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*
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* This feature is present specifically to support configuration
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* testing of the core in a lead vehicle, and is not supported
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* in any other environment. Attempting to use this feature
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* outside of the scope of a lead vehicle is a violation of the
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* MIPS Architecture, and may cause unpredictable operation of
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* the processor.
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*/
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#define C0_CONFIG_WC_SHF 19
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#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
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#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
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/* C0_CONFIG1 register encoding */
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#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
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#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
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#define C0_CONFIG1_IS_SHF S_Config1IS
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#define C0_CONFIG1_IS_MSK M_Config1IS
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#define C0_CONFIG1_IL_SHF S_Config1IL
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#define C0_CONFIG1_IL_MSK M_Config1IL
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#define C0_CONFIG1_IA_SHF S_Config1IA
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#define C0_CONFIG1_IA_MSK M_Config1IA
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#define C0_CONFIG1_DS_SHF S_Config1DS
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#define C0_CONFIG1_DS_MSK M_Config1DS
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#define C0_CONFIG1_DL_SHF S_Config1DL
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#define C0_CONFIG1_DL_MSK M_Config1DL
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#define C0_CONFIG1_DA_SHF S_Config1DA
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#define C0_CONFIG1_DA_MSK M_Config1DA
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#define C0_CONFIG1_WR_SHF S_Config1WR
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#define C0_CONFIG1_WR_MSK M_Config1WR
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#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
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#define C0_CONFIG1_CA_SHF S_Config1CA
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#define C0_CONFIG1_CA_MSK M_Config1CA
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#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
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#define C0_CONFIG1_EP_SHF S_Config1EP
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#define C0_CONFIG1_EP_MSK M_Config1EP
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#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
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#define C0_CONFIG1_FP_SHF S_Config1FP
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#define C0_CONFIG1_FP_MSK M_Config1FP
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#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
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/* C0_STATUS register encoding */
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#define C0_STATUS_CU3_SHF S_StatusCU3
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#define C0_STATUS_CU3_MSK M_StatusCU3
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#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
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#define C0_STATUS_CU2_SHF S_StatusCU2
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#define C0_STATUS_CU2_MSK M_StatusCU2
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#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
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#define C0_STATUS_CU1_SHF S_StatusCU1
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#define C0_STATUS_CU1_MSK M_StatusCU1
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#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
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#define C0_STATUS_CU0_SHF S_StatusCU1
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#define C0_STATUS_CU0_MSK M_StatusCU1
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#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
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#define C0_STATUS_RP_SHF S_StatusRP
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#define C0_STATUS_RP_MSK M_StatusRP
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#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
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#define C0_STATUS_FR_SHF S_StatusFR
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#define C0_STATUS_FR_MSK M_StatusFR
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#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
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#define C0_STATUS_RE_SHF S_StatusRE
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#define C0_STATUS_RE_MSK M_StatusRE
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#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
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#define C0_STATUS_BEV_SHF S_StatusBEV
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#define C0_STATUS_BEV_MSK M_StatusBEV
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#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
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#define C0_STATUS_TS_SHF S_StatusTS
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#define C0_STATUS_TS_MSK M_StatusTS
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#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
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#define C0_STATUS_SR_SHF S_StatusSR
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#define C0_STATUS_SR_MSK M_StatusSR
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#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
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#define C0_STATUS_NMI_SHF S_StatusNMI
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#define C0_STATUS_NMI_MSK M_StatusNMI
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#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
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#define C0_STATUS_IM_SHF S_StatusIM
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#define C0_STATUS_IM_MSK M_StatusIM
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/* Note that the the definitions below indicate the interrupt number
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* rather than the mask.
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* (0..1 for SW interrupts and 2...7 for HW interrupts)
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*/
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#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
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#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
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#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
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#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
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#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
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#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
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#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
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#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
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/* Max interrupt code */
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#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
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#define C0_STATUS_KSU_SHF S_StatusKSU
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#define C0_STATUS_KSU_MSK M_StatusKSU
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#define C0_STATUS_UM_SHF S_StatusUM
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#define C0_STATUS_UM_MSK M_StatusUM
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#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
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#define C0_STATUS_ERL_SHF S_StatusERL
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#define C0_STATUS_ERL_MSK M_StatusERL
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#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
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#define C0_STATUS_EXL_SHF S_StatusEXL
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#define C0_STATUS_EXL_MSK M_StatusEXL
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#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
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#define C0_STATUS_IE_SHF S_StatusIE
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#define C0_STATUS_IE_MSK M_StatusIE
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#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
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/* C0_PRID register encoding */
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#define C0_PRID_OPT_SHF S_PRIdCoOpt
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#define C0_PRID_OPT_MSK M_PRIdCoOpt
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#define C0_PRID_COMP_SHF S_PRIdCoID
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#define C0_PRID_COMP_MSK M_PRIdCoID
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#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
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#define C0_PRID_COMP_NOT_MIPS32_64 0
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#define C0_PRID_PRID_SHF S_PRIdImp
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#define C0_PRID_PRID_MSK M_PRIdImp
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/* Jade */
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#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
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#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
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/* Emerald */
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#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
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#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
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/* Coral */
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#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
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/* Opal */
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#define C0_PRID_PRID_5K K_PRIdImp_Opal
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/* Ruby */
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#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
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/* Other CPUs */
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#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
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#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
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#define C0_PRID_PRID_RM70XX 0x27
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#define C0_PRID_REV_SHF S_PRIdRev
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#define C0_PRID_REV_MSK M_PRIdRev
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#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
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C0_PRID_COMP_SHF) | \
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(C0_PRID_PRID_4Kc << \
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C0_PRID_PRID_SHF) \
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)
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#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
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C0_PRID_COMP_SHF) | \
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(C0_PRID_PRID_4Kmp << \
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C0_PRID_PRID_SHF) \
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)
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#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
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C0_PRID_COMP_SHF) | \
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(C0_PRID_PRID_4KEc << \
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C0_PRID_PRID_SHF) \
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)
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#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
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C0_PRID_COMP_SHF) | \
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(C0_PRID_PRID_4KEmp << \
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C0_PRID_PRID_SHF) \
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)
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#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
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C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_4KSc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_5K << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_20Kc << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_RM52XX << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||
C0_PRID_COMP_SHF) | \
|
||||
(C0_PRID_PRID_RM70XX << \
|
||||
C0_PRID_PRID_SHF) \
|
||||
)
|
||||
|
||||
/* C0_ENTRYHI register encoding */
|
||||
|
||||
#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
|
||||
#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
|
||||
|
||||
#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
|
||||
#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
|
||||
|
||||
|
||||
/* C0_CAUSE register encoding */
|
||||
|
||||
#define C0_CAUSE_BD_SHF S_CauseBD
|
||||
#define C0_CAUSE_BD_MSK M_CauseBD
|
||||
#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
|
||||
|
||||
#define C0_CAUSE_CE_SHF S_CauseCE
|
||||
#define C0_CAUSE_CE_MSK M_CauseCE
|
||||
|
||||
#define C0_CAUSE_IV_SHF S_CauseIV
|
||||
#define C0_CAUSE_IV_MSK M_CauseIV
|
||||
#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
|
||||
|
||||
#define C0_CAUSE_WP_SHF S_CauseWP
|
||||
#define C0_CAUSE_WP_MSK M_CauseWP
|
||||
#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
|
||||
|
||||
#define C0_CAUSE_IP_SHF S_CauseIP
|
||||
#define C0_CAUSE_IP_MSK M_CauseIP
|
||||
|
||||
#define C0_CAUSE_CODE_SHF S_CauseExcCode
|
||||
#define C0_CAUSE_CODE_MSK M_CauseExcCode
|
||||
|
||||
#define C0_CAUSE_CODE_INT EX_INT
|
||||
#define C0_CAUSE_CODE_MOD EX_MOD
|
||||
#define C0_CAUSE_CODE_TLBL EX_TLBL
|
||||
#define C0_CAUSE_CODE_TLBS EX_TLBS
|
||||
#define C0_CAUSE_CODE_ADEL EX_ADEL
|
||||
#define C0_CAUSE_CODE_ADES EX_ADES
|
||||
#define C0_CAUSE_CODE_IBE EX_IBE
|
||||
#define C0_CAUSE_CODE_DBE EX_DBE
|
||||
#define C0_CAUSE_CODE_SYS EX_SYS
|
||||
#define C0_CAUSE_CODE_BP EX_BP
|
||||
#define C0_CAUSE_CODE_RI EX_RI
|
||||
#define C0_CAUSE_CODE_CPU EX_CPU
|
||||
#define C0_CAUSE_CODE_OV EX_OV
|
||||
#define C0_CAUSE_CODE_TR EV_TR
|
||||
#define C0_CAUSE_CODE_FPE EX_FPE
|
||||
#define C0_CAUSE_CODE_WATCH EX_WATCH
|
||||
#define C0_CAUSE_CODE_MCHECK EX_MCHECK
|
||||
|
||||
/* Max cause code */
|
||||
#define C0_CAUSE_CODE_MAX EX_MCHECK
|
||||
|
||||
|
||||
/* C0_PAGEMASK register encoding */
|
||||
#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
|
||||
#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
|
||||
#define C0_PAGEMASK_MASK_4K K_PageMask4K
|
||||
#define C0_PAGEMASK_MASK_16K K_PageMask16K
|
||||
#define C0_PAGEMASK_MASK_64K K_PageMask64K
|
||||
#define C0_PAGEMASK_MASK_256K K_PageMask256K
|
||||
#define C0_PAGEMASK_MASK_1M K_PageMask1M
|
||||
#define C0_PAGEMASK_MASK_4M K_PageMask4M
|
||||
#define C0_PAGEMASK_MASK_16M K_PageMask16M
|
||||
|
||||
|
||||
/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
|
||||
#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
|
||||
#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
|
||||
|
||||
#define C0_ENTRYLO0_C_SHF S_EntryLoC
|
||||
#define C0_ENTRYLO0_C_MSK M_EntryLoC
|
||||
|
||||
#define C0_ENTRYLO0_D_SHF S_EntryLoD
|
||||
#define C0_ENTRYLO0_D_MSK M_EntryLoD
|
||||
|
||||
#define C0_ENTRYLO0_V_SHF S_EntryLoV
|
||||
#define C0_ENTRYLO0_V_MSK M_EntryLoV
|
||||
|
||||
#define C0_ENTRYLO0_G_SHF S_EntryLoG
|
||||
#define C0_ENTRYLO0_G_MSK M_EntryLoG
|
||||
|
||||
|
||||
/* FPU (CP1) FIR register encoding */
|
||||
#define C1_FIR_3D_SHF S_FIRConfig3D
|
||||
#define C1_FIR_3D_MSK M_FIRConfig3D
|
||||
|
||||
#define C1_FIR_PS_SHF S_FIRConfigPS
|
||||
#define C1_FIR_PS_MSK M_FIRConfigPS
|
||||
|
||||
#define C1_FIR_D_SHF S_FIRConfigD
|
||||
#define C1_FIR_D_MSK M_FIRConfigD
|
||||
|
||||
#define C1_FIR_S_SHF S_FIRConfigS
|
||||
#define C1_FIR_S_MSK M_FIRConfigS
|
||||
|
||||
#define C1_FIR_PRID_SHF S_FIRImp
|
||||
#define C1_FIR_PRID_MSK M_FIRImp
|
||||
|
||||
#define C1_FIR_REV_SHF S_FIRRev
|
||||
#define C1_FIR_REV_MSK M_FIRRev
|
||||
|
||||
|
||||
/* FPU (CP1) FCSR control/status register */
|
||||
#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
|
||||
#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
|
||||
|
||||
#define C1_FCSR_FS_SHF S_FCSRFS
|
||||
#define C1_FCSR_FS_MSK M_FCSRFS
|
||||
#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
|
||||
|
||||
#define C1_FCSR_CC_SHF S_FCSRCC
|
||||
#define C1_FCSR_CC_MSK M_FCSRCC
|
||||
|
||||
#define C1_FCSR_IMPL_SHF S_FCSRImpl
|
||||
#define C1_FCSR_IMPL_MSK M_FCSRImpl
|
||||
|
||||
#define C1_FCSR_EXC_SHF S_FCSRExc
|
||||
#define C1_FCSR_EXC_MSK M_FCSRExc
|
||||
|
||||
#define C1_FCSR_ENA_SHF S_FCSREna
|
||||
#define C1_FCSR_ENA_MSK M_FCSREna
|
||||
|
||||
#define C1_FCSR_FLG_SHF S_FCSRFlg
|
||||
#define C1_FCSR_FLG_MSK M_FCSRFlg
|
||||
|
||||
#define C1_FCSR_RM_SHF S_FCSRRM
|
||||
#define C1_FCSR_RM_MSK M_FCSRRM
|
||||
#define C1_FCSR_RM_RN K_FCSRRM_RN
|
||||
#define C1_FCSR_RM_RZ K_FCSRRM_RZ
|
||||
#define C1_FCSR_RM_RP K_FCSRRM_RP
|
||||
#define C1_FCSR_RM_RM K_FCSRRM_RM
|
||||
|
||||
|
||||
|
||||
/* cache operations */
|
||||
|
||||
#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
|
||||
|
||||
#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
|
||||
#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
|
||||
#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
|
||||
#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
|
||||
#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
|
||||
#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
|
||||
#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
|
||||
|
||||
#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
|
||||
#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
|
||||
#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
|
||||
#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
|
||||
#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
|
||||
#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
|
||||
#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
|
||||
|
||||
#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
|
||||
|
||||
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||
* processors. Only relevant in early engineering samples of test
|
||||
* chips (RTL revision <= 3.0).
|
||||
*
|
||||
* The bug is described in :
|
||||
*
|
||||
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||
* MIPS Document No: MD00003
|
||||
*
|
||||
* The bug is identified as : C16
|
||||
*/
|
||||
#ifndef SET_MIPS0
|
||||
#define SET_MIPS0()
|
||||
#define SET_PUSH()
|
||||
#define SET_POP()
|
||||
#endif
|
||||
#define ICACHE_INVALIDATE_WORKAROUND(reg) \
|
||||
SET_PUSH(); \
|
||||
SET_MIPS0(); \
|
||||
la reg, 999f; \
|
||||
SET_POP(); \
|
||||
cache ICACHE_ADDR_FILL, 0(reg); \
|
||||
sync; \
|
||||
nop; nop; nop; nop; \
|
||||
999:
|
||||
|
||||
/* EMPTY_PIPELINE is used for the below cache invalidation operations.
|
||||
* When $I is invalidated, there will still be operations in the
|
||||
* pipeline. We make sure these are 'nop' operations.
|
||||
*/
|
||||
#define EMPTY_PIPELINE nop; nop; nop; nop
|
||||
|
||||
#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
|
||||
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||
cache ICACHE_INDEX_INVALIDATE, 0(index); \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
|
||||
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||
cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
/* The sync used in the below macro is there in case we are installing
|
||||
* a new instruction (flush $D, sync, invalidate $I sequence).
|
||||
*/
|
||||
#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
|
||||
cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
|
||||
sync; \
|
||||
EMPTY_PIPELINE
|
||||
|
||||
/* Config1 cache field decoding */
|
||||
#define CACHE_CALC_SPW(s) ( 64 << (s) )
|
||||
#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
|
||||
#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
|
||||
#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
|
||||
|
||||
|
||||
/**** Move from/to Coprocessor operations ****/
|
||||
|
||||
/* We use ssnop instead of nop operations in order to handle
|
||||
* superscalar CPUs.
|
||||
* The "sll zero,zero,1" notation is compiler backwards compatible.
|
||||
*/
|
||||
#define SSNOP sll zero,zero,1
|
||||
#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
|
||||
|
||||
#define MFLO(dst) \
|
||||
mflo dst;\
|
||||
NOPS
|
||||
|
||||
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||
* processors.
|
||||
*
|
||||
* This concerns the nop instruction before mtc0 in the
|
||||
* MTC0 macro below.
|
||||
*
|
||||
* The bug is described in :
|
||||
*
|
||||
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||
* MIPS Document No: MD00003
|
||||
*
|
||||
* The bug is identified as : C27
|
||||
*/
|
||||
|
||||
#define MTC0(src, dst) \
|
||||
nop; \
|
||||
mtc0 src,dst;\
|
||||
NOPS
|
||||
|
||||
#define DMTC0(src, dst) \
|
||||
nop; \
|
||||
dmtc0 src,dst;\
|
||||
NOPS
|
||||
|
||||
#define MFC0(dst, src) \
|
||||
mfc0 dst,src;\
|
||||
NOPS
|
||||
|
||||
#define DMFC0(dst, src) \
|
||||
dmfc0 dst,src;\
|
||||
NOPS
|
||||
|
||||
#define MFC0_SEL_OPCODE(dst, src, sel)\
|
||||
.##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||
NOPS
|
||||
|
||||
#define MTC0_SEL_OPCODE(dst, src, sel)\
|
||||
.##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||
NOPS
|
||||
|
||||
#define LDC1(dst, src, offs)\
|
||||
.##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
|
||||
|
||||
#define SDC1(src, dst, offs)\
|
||||
.##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
|
||||
|
||||
|
||||
/* Instruction opcode fields */
|
||||
#define OPC_SPECIAL 0x0
|
||||
#define OPC_REGIM 0x1
|
||||
#define OPC_J 0x2
|
||||
#define OPC_JAL 0x3
|
||||
#define OPC_BEQ 0x4
|
||||
#define OPC_BNE 0x5
|
||||
#define OPC_BLEZ 0x6
|
||||
#define OPC_BGTZ 0x7
|
||||
#define OPC_COP1 0x11
|
||||
#define OPC_JALX 0x1D
|
||||
#define OPC_BEQL 0x14
|
||||
#define OPC_BNEL 0x15
|
||||
#define OPC_BLEZL 0x16
|
||||
#define OPC_BGTZL 0x17
|
||||
|
||||
/* Instruction function fields */
|
||||
#define FUNC_JR 0x8
|
||||
#define FUNC_JALR 0x9
|
||||
|
||||
/* Instruction rt fields */
|
||||
#define RT_BLTZ 0x0
|
||||
#define RT_BGEZ 0x1
|
||||
#define RT_BLTZL 0x2
|
||||
#define RT_BGEZL 0x3
|
||||
#define RT_BLTZAL 0x10
|
||||
#define RT_BGEZAL 0x11
|
||||
#define RT_BLTZALL 0x12
|
||||
#define RT_BGEZALL 0x13
|
||||
|
||||
/* Instruction rs fields */
|
||||
#define RS_BC1 0x08
|
||||
|
||||
/* Access macros for instruction fields */
|
||||
#define MIPS_OPCODE( instr) ((instr) >> 26)
|
||||
#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
|
||||
#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
|
||||
#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
|
||||
#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
|
||||
#define MIPS_TARGET(instr) ((instr) & MSK(26))
|
||||
|
||||
/* Instructions */
|
||||
#define OPCODE_DERET 0x4200001f
|
||||
#define OPCODE_BREAK 0x0005000d
|
||||
#define OPCODE_NOP 0
|
||||
#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
|
||||
|
||||
#define DERET .##word OPCODE_DERET
|
||||
|
||||
/* MIPS16e opcodes and instruction field access macros */
|
||||
|
||||
#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
|
||||
#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
|
||||
#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
|
||||
#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
|
||||
#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
|
||||
#define MIPS16E_OPC_EXTEND 0x1e
|
||||
#define MIPS16E_OPC_JAL_X 0x03
|
||||
#define MIPS16E_OPC_B 0x02
|
||||
#define MIPS16E_OPC_BEQZ 0x04
|
||||
#define MIPS16E_OPC_BNEZ 0x05
|
||||
#define MIPS16E_OPC_I8 0x0c
|
||||
#define MIPS16E_I8_FUNC_BTEQZ 0x00
|
||||
#define MIPS16E_I8_FUNC_BTNEZ 0x01
|
||||
#define MIPS16E_X_JALX 0x01
|
||||
#define MIPS16E_OPC_RR 0x1d
|
||||
#define MIPS16E_RR_FUNC_JALRC 0x00
|
||||
#define MIPS16E_RR_RY_JRRX 0x00
|
||||
#define MIPS16E_RR_RY_JRRA 0x01
|
||||
#define MIPS16E_RR_RY_JALR 0x02
|
||||
#define MIPS16E_RR_RY_JRCRX 0x04
|
||||
#define MIPS16E_RR_RY_JRCRA 0x05
|
||||
#define MIPS16E_RR_RY_JALRC 0x06
|
||||
|
||||
#define MIPS16E_OPCODE_BREAK 0xE805
|
||||
#define MIPS16E_OPCODE_NOP 0x6500
|
||||
|
||||
/* MIPS reset vector */
|
||||
#define MIPS_RESET_VECTOR 0x1fc00000
|
||||
|
||||
/* Clock periods per count register increment */
|
||||
#define MIPS4K_COUNT_CLK_PER_CYCLE 2
|
||||
#define MIPS5K_COUNT_CLK_PER_CYCLE 2
|
||||
#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
|
||||
|
||||
|
||||
/**** MIPS 4K/5K families specific fields of CONFIG register ****/
|
||||
|
||||
#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23
|
||||
#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF)
|
||||
|
||||
#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU
|
||||
#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF)
|
||||
|
||||
|
||||
/**** MIPS 20Kc specific fields of CONFIG register ****/
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_EC_SHF 28
|
||||
#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_DD_SHF 27
|
||||
#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_LP_SHF 26
|
||||
#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_SP_SHF 25
|
||||
#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK
|
||||
|
||||
#define C0_CONFIG_MIPS20KC_TI_SHF 24
|
||||
#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
|
||||
#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Interface function definition */
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
|
||||
#endif /* #ifndef __MIPS_H__ */
|
||||
@ -1,985 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
|
||||
* Copyright (C) 2000 Silicon Graphics, Inc.
|
||||
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
|
||||
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2003 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef _ASM_MIPSREGS_H
|
||||
#define _ASM_MIPSREGS_H
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* The following macros are especially useful for __asm__
|
||||
* inline assembler.
|
||||
*/
|
||||
#ifndef __STR
|
||||
#define __STR(x) #x
|
||||
#endif
|
||||
#ifndef STR
|
||||
#define STR(x) __STR(x)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Configure language
|
||||
*/
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _ULCAST_
|
||||
#else
|
||||
#define _ULCAST_ (unsigned long)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Coprocessor 0 register names
|
||||
*/
|
||||
#define CP0_INDEX $0
|
||||
#define CP0_RANDOM $1
|
||||
#define CP0_ENTRYLO0 $2
|
||||
#define CP0_ENTRYLO1 $3
|
||||
#define CP0_CONF $3
|
||||
#define CP0_CONTEXT $4
|
||||
#define CP0_PAGEMASK $5
|
||||
#define CP0_WIRED $6
|
||||
#define CP0_INFO $7
|
||||
#define CP0_BADVADDR $8
|
||||
#define CP0_COUNT $9
|
||||
#define CP0_ENTRYHI $10
|
||||
#define CP0_COMPARE $11
|
||||
#define CP0_STATUS $12
|
||||
#define CP0_CAUSE $13
|
||||
#define CP0_EPC $14
|
||||
#define CP0_PRID $15
|
||||
#define CP0_CONFIG $16
|
||||
#define CP0_LLADDR $17
|
||||
#define CP0_WATCHLO $18
|
||||
#define CP0_WATCHHI $19
|
||||
#define CP0_XCONTEXT $20
|
||||
#define CP0_FRAMEMASK $21
|
||||
#define CP0_DIAGNOSTIC $22
|
||||
#define CP0_DEBUG $23
|
||||
#define CP0_DEPC $24
|
||||
#define CP0_PERFORMANCE $25
|
||||
#define CP0_ECC $26
|
||||
#define CP0_CACHEERR $27
|
||||
#define CP0_TAGLO $28
|
||||
#define CP0_TAGHI $29
|
||||
#define CP0_ERROREPC $30
|
||||
#define CP0_DESAVE $31
|
||||
|
||||
/*
|
||||
* R4640/R4650 cp0 register names. These registers are listed
|
||||
* here only for completeness; without MMU these CPUs are not useable
|
||||
* by Linux. A future ELKS port might take make Linux run on them
|
||||
* though ...
|
||||
*/
|
||||
#define CP0_IBASE $0
|
||||
#define CP0_IBOUND $1
|
||||
#define CP0_DBASE $2
|
||||
#define CP0_DBOUND $3
|
||||
#define CP0_CALG $17
|
||||
#define CP0_IWATCH $18
|
||||
#define CP0_DWATCH $19
|
||||
|
||||
/*
|
||||
* Coprocessor 0 Set 1 register names
|
||||
*/
|
||||
#define CP0_S1_DERRADDR0 $26
|
||||
#define CP0_S1_DERRADDR1 $27
|
||||
#define CP0_S1_INTCONTROL $20
|
||||
|
||||
/*
|
||||
* TX39 Series
|
||||
*/
|
||||
#define CP0_TX39_CACHE $7
|
||||
|
||||
/*
|
||||
* Coprocessor 1 (FPU) register names
|
||||
*/
|
||||
#define CP1_REVISION $0
|
||||
#define CP1_STATUS $31
|
||||
|
||||
/*
|
||||
* FPU Status Register Values
|
||||
*/
|
||||
/*
|
||||
* Status Register Values
|
||||
*/
|
||||
|
||||
#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
|
||||
#define FPU_CSR_COND 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
|
||||
#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
|
||||
#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
|
||||
#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
|
||||
#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
|
||||
#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
|
||||
#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
|
||||
#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
|
||||
|
||||
/*
|
||||
* X the exception cause indicator
|
||||
* E the exception enable
|
||||
* S the sticky/flag bit
|
||||
*/
|
||||
#define FPU_CSR_ALL_X 0x0003f000
|
||||
#define FPU_CSR_UNI_X 0x00020000
|
||||
#define FPU_CSR_INV_X 0x00010000
|
||||
#define FPU_CSR_DIV_X 0x00008000
|
||||
#define FPU_CSR_OVF_X 0x00004000
|
||||
#define FPU_CSR_UDF_X 0x00002000
|
||||
#define FPU_CSR_INE_X 0x00001000
|
||||
|
||||
#define FPU_CSR_ALL_E 0x00000f80
|
||||
#define FPU_CSR_INV_E 0x00000800
|
||||
#define FPU_CSR_DIV_E 0x00000400
|
||||
#define FPU_CSR_OVF_E 0x00000200
|
||||
#define FPU_CSR_UDF_E 0x00000100
|
||||
#define FPU_CSR_INE_E 0x00000080
|
||||
|
||||
#define FPU_CSR_ALL_S 0x0000007c
|
||||
#define FPU_CSR_INV_S 0x00000040
|
||||
#define FPU_CSR_DIV_S 0x00000020
|
||||
#define FPU_CSR_OVF_S 0x00000010
|
||||
#define FPU_CSR_UDF_S 0x00000008
|
||||
#define FPU_CSR_INE_S 0x00000004
|
||||
|
||||
/* rounding mode */
|
||||
#define FPU_CSR_RN 0x0 /* nearest */
|
||||
#define FPU_CSR_RZ 0x1 /* towards zero */
|
||||
#define FPU_CSR_RU 0x2 /* towards +Infinity */
|
||||
#define FPU_CSR_RD 0x3 /* towards -Infinity */
|
||||
|
||||
|
||||
/*
|
||||
* Values for PageMask register
|
||||
*/
|
||||
#ifdef CONFIG_CPU_VR41XX
|
||||
|
||||
/* Why doesn't stupidity hurt ... */
|
||||
|
||||
#define PM_1K 0x00000000
|
||||
#define PM_4K 0x00001800
|
||||
#define PM_16K 0x00007800
|
||||
#define PM_64K 0x0001f800
|
||||
#define PM_256K 0x0007f800
|
||||
|
||||
#else
|
||||
|
||||
#define PM_4K 0x00000000
|
||||
#define PM_16K 0x00006000
|
||||
#define PM_64K 0x0001e000
|
||||
#define PM_256K 0x0007e000
|
||||
#define PM_1M 0x001fe000
|
||||
#define PM_4M 0x007fe000
|
||||
#define PM_16M 0x01ffe000
|
||||
#define PM_64M 0x07ffe000
|
||||
#define PM_256M 0x1fffe000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Values used for computation of new tlb entries
|
||||
*/
|
||||
#define PL_4K 12
|
||||
#define PL_16K 14
|
||||
#define PL_64K 16
|
||||
#define PL_256K 18
|
||||
#define PL_1M 20
|
||||
#define PL_4M 22
|
||||
#define PL_16M 24
|
||||
#define PL_64M 26
|
||||
#define PL_256M 28
|
||||
|
||||
/*
|
||||
* R4x00 interrupt enable / cause bits
|
||||
*/
|
||||
#define IE_SW0 (_ULCAST_(1) << 8)
|
||||
#define IE_SW1 (_ULCAST_(1) << 9)
|
||||
#define IE_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define IE_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define IE_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define IE_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define IE_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define IE_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* R4x00 interrupt cause bits
|
||||
*/
|
||||
#define C_SW0 (_ULCAST_(1) << 8)
|
||||
#define C_SW1 (_ULCAST_(1) << 9)
|
||||
#define C_IRQ0 (_ULCAST_(1) << 10)
|
||||
#define C_IRQ1 (_ULCAST_(1) << 11)
|
||||
#define C_IRQ2 (_ULCAST_(1) << 12)
|
||||
#define C_IRQ3 (_ULCAST_(1) << 13)
|
||||
#define C_IRQ4 (_ULCAST_(1) << 14)
|
||||
#define C_IRQ5 (_ULCAST_(1) << 15)
|
||||
|
||||
/*
|
||||
* Bitfields in the R4xx0 cp0 status register
|
||||
*/
|
||||
#define ST0_IE 0x00000001
|
||||
#define ST0_EXL 0x00000002
|
||||
#define ST0_ERL 0x00000004
|
||||
#define ST0_KSU 0x00000018
|
||||
# define KSU_USER 0x00000010
|
||||
# define KSU_SUPERVISOR 0x00000008
|
||||
# define KSU_KERNEL 0x00000000
|
||||
#define ST0_UX 0x00000020
|
||||
#define ST0_SX 0x00000040
|
||||
#define ST0_KX 0x00000080
|
||||
#define ST0_DE 0x00010000
|
||||
#define ST0_CE 0x00020000
|
||||
|
||||
/*
|
||||
* Bitfields in the R[23]000 cp0 status register.
|
||||
*/
|
||||
#define ST0_IEC 0x00000001
|
||||
#define ST0_KUC 0x00000002
|
||||
#define ST0_IEP 0x00000004
|
||||
#define ST0_KUP 0x00000008
|
||||
#define ST0_IEO 0x00000010
|
||||
#define ST0_KUO 0x00000020
|
||||
/* bits 6 & 7 are reserved on R[23]000 */
|
||||
#define ST0_ISC 0x00010000
|
||||
#define ST0_SWC 0x00020000
|
||||
#define ST0_CM 0x00080000
|
||||
|
||||
/*
|
||||
* Bits specific to the R4640/R4650
|
||||
*/
|
||||
#define ST0_UM (_ULCAST_(1) << 4)
|
||||
#define ST0_IL (_ULCAST_(1) << 23)
|
||||
#define ST0_DL (_ULCAST_(1) << 24)
|
||||
|
||||
/*
|
||||
* Bitfields in the TX39 family CP0 Configuration Register 3
|
||||
*/
|
||||
#define TX39_CONF_ICS_SHIFT 19
|
||||
#define TX39_CONF_ICS_MASK 0x00380000
|
||||
#define TX39_CONF_ICS_1KB 0x00000000
|
||||
#define TX39_CONF_ICS_2KB 0x00080000
|
||||
#define TX39_CONF_ICS_4KB 0x00100000
|
||||
#define TX39_CONF_ICS_8KB 0x00180000
|
||||
#define TX39_CONF_ICS_16KB 0x00200000
|
||||
|
||||
#define TX39_CONF_DCS_SHIFT 16
|
||||
#define TX39_CONF_DCS_MASK 0x00070000
|
||||
#define TX39_CONF_DCS_1KB 0x00000000
|
||||
#define TX39_CONF_DCS_2KB 0x00010000
|
||||
#define TX39_CONF_DCS_4KB 0x00020000
|
||||
#define TX39_CONF_DCS_8KB 0x00030000
|
||||
#define TX39_CONF_DCS_16KB 0x00040000
|
||||
|
||||
#define TX39_CONF_CWFON 0x00004000
|
||||
#define TX39_CONF_WBON 0x00002000
|
||||
#define TX39_CONF_RF_SHIFT 10
|
||||
#define TX39_CONF_RF_MASK 0x00000c00
|
||||
#define TX39_CONF_DOZE 0x00000200
|
||||
#define TX39_CONF_HALT 0x00000100
|
||||
#define TX39_CONF_LOCK 0x00000080
|
||||
#define TX39_CONF_ICE 0x00000020
|
||||
#define TX39_CONF_DCE 0x00000010
|
||||
#define TX39_CONF_IRSIZE_SHIFT 2
|
||||
#define TX39_CONF_IRSIZE_MASK 0x0000000c
|
||||
#define TX39_CONF_DRSIZE_SHIFT 0
|
||||
#define TX39_CONF_DRSIZE_MASK 0x00000003
|
||||
|
||||
/*
|
||||
* Status register bits available in all MIPS CPUs.
|
||||
*/
|
||||
#define ST0_IM 0x0000ff00
|
||||
#define STATUSB_IP0 8
|
||||
#define STATUSF_IP0 (_ULCAST_(1) << 8)
|
||||
#define STATUSB_IP1 9
|
||||
#define STATUSF_IP1 (_ULCAST_(1) << 9)
|
||||
#define STATUSB_IP2 10
|
||||
#define STATUSF_IP2 (_ULCAST_(1) << 10)
|
||||
#define STATUSB_IP3 11
|
||||
#define STATUSF_IP3 (_ULCAST_(1) << 11)
|
||||
#define STATUSB_IP4 12
|
||||
#define STATUSF_IP4 (_ULCAST_(1) << 12)
|
||||
#define STATUSB_IP5 13
|
||||
#define STATUSF_IP5 (_ULCAST_(1) << 13)
|
||||
#define STATUSB_IP6 14
|
||||
#define STATUSF_IP6 (_ULCAST_(1) << 14)
|
||||
#define STATUSB_IP7 15
|
||||
#define STATUSF_IP7 (_ULCAST_(1) << 15)
|
||||
#define STATUSB_IP8 0
|
||||
#define STATUSF_IP8 (_ULCAST_(1) << 0)
|
||||
#define STATUSB_IP9 1
|
||||
#define STATUSF_IP9 (_ULCAST_(1) << 1)
|
||||
#define STATUSB_IP10 2
|
||||
#define STATUSF_IP10 (_ULCAST_(1) << 2)
|
||||
#define STATUSB_IP11 3
|
||||
#define STATUSF_IP11 (_ULCAST_(1) << 3)
|
||||
#define STATUSB_IP12 4
|
||||
#define STATUSF_IP12 (_ULCAST_(1) << 4)
|
||||
#define STATUSB_IP13 5
|
||||
#define STATUSF_IP13 (_ULCAST_(1) << 5)
|
||||
#define STATUSB_IP14 6
|
||||
#define STATUSF_IP14 (_ULCAST_(1) << 6)
|
||||
#define STATUSB_IP15 7
|
||||
#define STATUSF_IP15 (_ULCAST_(1) << 7)
|
||||
#define ST0_CH 0x00040000
|
||||
#define ST0_SR 0x00100000
|
||||
#define ST0_TS 0x00200000
|
||||
#define ST0_BEV 0x00400000
|
||||
#define ST0_RE 0x02000000
|
||||
#define ST0_FR 0x04000000
|
||||
#define ST0_CU 0xf0000000
|
||||
#define ST0_CU0 0x10000000
|
||||
#define ST0_CU1 0x20000000
|
||||
#define ST0_CU2 0x40000000
|
||||
#define ST0_CU3 0x80000000
|
||||
#define ST0_XX 0x80000000 /* MIPS IV naming */
|
||||
|
||||
/*
|
||||
* Bitfields and bit numbers in the coprocessor 0 cause register.
|
||||
*
|
||||
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
|
||||
*/
|
||||
#define CAUSEB_EXCCODE 2
|
||||
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
|
||||
#define CAUSEB_IP 8
|
||||
#define CAUSEF_IP (_ULCAST_(255) << 8)
|
||||
#define CAUSEB_IP0 8
|
||||
#define CAUSEF_IP0 (_ULCAST_(1) << 8)
|
||||
#define CAUSEB_IP1 9
|
||||
#define CAUSEF_IP1 (_ULCAST_(1) << 9)
|
||||
#define CAUSEB_IP2 10
|
||||
#define CAUSEF_IP2 (_ULCAST_(1) << 10)
|
||||
#define CAUSEB_IP3 11
|
||||
#define CAUSEF_IP3 (_ULCAST_(1) << 11)
|
||||
#define CAUSEB_IP4 12
|
||||
#define CAUSEF_IP4 (_ULCAST_(1) << 12)
|
||||
#define CAUSEB_IP5 13
|
||||
#define CAUSEF_IP5 (_ULCAST_(1) << 13)
|
||||
#define CAUSEB_IP6 14
|
||||
#define CAUSEF_IP6 (_ULCAST_(1) << 14)
|
||||
#define CAUSEB_IP7 15
|
||||
#define CAUSEF_IP7 (_ULCAST_(1) << 15)
|
||||
#define CAUSEB_IV 23
|
||||
#define CAUSEF_IV (_ULCAST_(1) << 23)
|
||||
#define CAUSEB_CE 28
|
||||
#define CAUSEF_CE (_ULCAST_(3) << 28)
|
||||
#define CAUSEB_BD 31
|
||||
#define CAUSEF_BD (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* Bits in the coprocessor 0 config register.
|
||||
*/
|
||||
/* Generic bits. */
|
||||
#define CONF_CM_CACHABLE_NO_WA 0
|
||||
#define CONF_CM_CACHABLE_WA 1
|
||||
#define CONF_CM_UNCACHED 2
|
||||
#define CONF_CM_CACHABLE_NONCOHERENT 3
|
||||
#define CONF_CM_CACHABLE_CE 4
|
||||
#define CONF_CM_CACHABLE_COW 5
|
||||
#define CONF_CM_CACHABLE_CUW 6
|
||||
#define CONF_CM_CACHABLE_ACCELERATED 7
|
||||
#define CONF_CM_CMASK 7
|
||||
#define CONF_BE (_ULCAST_(1) << 15)
|
||||
|
||||
/* Bits common to various processors. */
|
||||
#define CONF_CU (_ULCAST_(1) << 3)
|
||||
#define CONF_DB (_ULCAST_(1) << 4)
|
||||
#define CONF_IB (_ULCAST_(1) << 5)
|
||||
#define CONF_DC (_ULCAST_(7) << 6)
|
||||
#define CONF_IC (_ULCAST_(7) << 9)
|
||||
#define CONF_EB (_ULCAST_(1) << 13)
|
||||
#define CONF_EM (_ULCAST_(1) << 14)
|
||||
#define CONF_SM (_ULCAST_(1) << 16)
|
||||
#define CONF_SC (_ULCAST_(1) << 17)
|
||||
#define CONF_EW (_ULCAST_(3) << 18)
|
||||
#define CONF_EP (_ULCAST_(15)<< 24)
|
||||
#define CONF_EC (_ULCAST_(7) << 28)
|
||||
#define CONF_CM (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the R4xx0. */
|
||||
#define R4K_CONF_SW (_ULCAST_(1) << 20)
|
||||
#define R4K_CONF_SS (_ULCAST_(1) << 21)
|
||||
#define R4K_CONF_SB (_ULCAST_(3) << 22)
|
||||
|
||||
/* Bits specific to the R5000. */
|
||||
#define R5K_CONF_SE (_ULCAST_(1) << 12)
|
||||
#define R5K_CONF_SS (_ULCAST_(3) << 20)
|
||||
|
||||
/* Bits specific to the R10000. */
|
||||
#define R10K_CONF_DN (_ULCAST_(3) << 3)
|
||||
#define R10K_CONF_CT (_ULCAST_(1) << 5)
|
||||
#define R10K_CONF_PE (_ULCAST_(1) << 6)
|
||||
#define R10K_CONF_PM (_ULCAST_(3) << 7)
|
||||
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
|
||||
#define R10K_CONF_SB (_ULCAST_(1) << 13)
|
||||
#define R10K_CONF_SK (_ULCAST_(1) << 14)
|
||||
#define R10K_CONF_SS (_ULCAST_(7) << 16)
|
||||
#define R10K_CONF_SC (_ULCAST_(7) << 19)
|
||||
#define R10K_CONF_DC (_ULCAST_(7) << 26)
|
||||
#define R10K_CONF_IC (_ULCAST_(7) << 29)
|
||||
|
||||
/* Bits specific to the VR41xx. */
|
||||
#define VR41_CONF_CS (_ULCAST_(1) << 12)
|
||||
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
|
||||
#define VR41_CONF_AD (_ULCAST_(1) << 23)
|
||||
|
||||
/* Bits specific to the R30xx. */
|
||||
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
|
||||
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
|
||||
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
|
||||
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
|
||||
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
|
||||
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
|
||||
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
|
||||
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
|
||||
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
|
||||
|
||||
/* Bits specific to the TX49. */
|
||||
#define TX49_CONF_DC (_ULCAST_(1) << 16)
|
||||
#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
|
||||
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
|
||||
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
|
||||
|
||||
/* Bits specific to the MIPS32/64 PRA. */
|
||||
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
|
||||
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
|
||||
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
|
||||
#define MIPS_CONF_M (_ULCAST_(1) << 31)
|
||||
|
||||
/*
|
||||
* R10000 performance counter definitions.
|
||||
*
|
||||
* FIXME: The R10000 performance counter opens a nice way to implement CPU
|
||||
* time accounting with a precission of one cycle. I don't have
|
||||
* R10000 silicon but just a manual, so ...
|
||||
*/
|
||||
|
||||
/*
|
||||
* Events counted by counter #0
|
||||
*/
|
||||
#define CE0_CYCLES 0
|
||||
#define CE0_INSN_ISSUED 1
|
||||
#define CE0_LPSC_ISSUED 2
|
||||
#define CE0_S_ISSUED 3
|
||||
#define CE0_SC_ISSUED 4
|
||||
#define CE0_SC_FAILED 5
|
||||
#define CE0_BRANCH_DECODED 6
|
||||
#define CE0_QW_WB_SECONDARY 7
|
||||
#define CE0_CORRECTED_ECC_ERRORS 8
|
||||
#define CE0_ICACHE_MISSES 9
|
||||
#define CE0_SCACHE_I_MISSES 10
|
||||
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
|
||||
#define CE0_EXT_INTERVENTIONS_REQ 12
|
||||
#define CE0_EXT_INVALIDATE_REQ 13
|
||||
#define CE0_VIRTUAL_COHERENCY_COND 14
|
||||
#define CE0_INSN_GRADUATED 15
|
||||
|
||||
/*
|
||||
* Events counted by counter #1
|
||||
*/
|
||||
#define CE1_CYCLES 0
|
||||
#define CE1_INSN_GRADUATED 1
|
||||
#define CE1_LPSC_GRADUATED 2
|
||||
#define CE1_S_GRADUATED 3
|
||||
#define CE1_SC_GRADUATED 4
|
||||
#define CE1_FP_INSN_GRADUATED 5
|
||||
#define CE1_QW_WB_PRIMARY 6
|
||||
#define CE1_TLB_REFILL 7
|
||||
#define CE1_BRANCH_MISSPREDICTED 8
|
||||
#define CE1_DCACHE_MISS 9
|
||||
#define CE1_SCACHE_D_MISSES 10
|
||||
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
|
||||
#define CE1_EXT_INTERVENTION_HITS 12
|
||||
#define CE1_EXT_INVALIDATE_REQ 13
|
||||
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
|
||||
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
|
||||
|
||||
/*
|
||||
* These flags define in which priviledge mode the counters count events
|
||||
*/
|
||||
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
|
||||
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
|
||||
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
|
||||
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
|
||||
#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
|
||||
|
||||
/*
|
||||
* Functions to access the r10k performance counter and control registers
|
||||
*/
|
||||
#define read_r10k_perf_cntr(counter) \
|
||||
({ unsigned int __res; \
|
||||
__asm__ __volatile__( \
|
||||
"mfpc\t%0, "STR(counter) \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_r10k_perf_cntr(counter,val) \
|
||||
__asm__ __volatile__( \
|
||||
"mtpc\t%0, "STR(counter) \
|
||||
: : "r" (val));
|
||||
|
||||
#define read_r10k_perf_cntl(counter) \
|
||||
({ unsigned int __res; \
|
||||
__asm__ __volatile__( \
|
||||
"mfps\t%0, "STR(counter) \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_r10k_perf_cntl(counter,val) \
|
||||
__asm__ __volatile__( \
|
||||
"mtps\t%0, "STR(counter) \
|
||||
: : "r" (val));
|
||||
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
|
||||
#define __read_32bit_c0_register(source, sel) \
|
||||
({ int __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mfc0\t%0, " #source "\n\t" \
|
||||
: "=r" (__res)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0\n\t" \
|
||||
: "=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __read_64bit_c0_register(source, sel) \
|
||||
({ unsigned long __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmfc0\t%0, " #source "\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __write_32bit_c0_register(register, sel, value) \
|
||||
do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%z0, " #register "\n\t" \
|
||||
: : "Jr" (value)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips32\n\t" \
|
||||
"mtc0\t%z0, " #register ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
} while (0)
|
||||
|
||||
#define __write_64bit_c0_register(register, sel, value) \
|
||||
do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmtc0\t%z0, " #register "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "Jr" (value)); \
|
||||
} while (0)
|
||||
|
||||
#define __read_ulong_c0_register(reg, sel) \
|
||||
((sizeof(unsigned long) == 4) ? \
|
||||
__read_32bit_c0_register(reg, sel) : \
|
||||
__read_64bit_c0_register(reg, sel))
|
||||
|
||||
#define __write_ulong_c0_register(reg, sel, val) \
|
||||
do { \
|
||||
if (sizeof(unsigned long) == 4) \
|
||||
__write_32bit_c0_register(reg, sel, val); \
|
||||
else \
|
||||
__write_64bit_c0_register(reg, sel, val); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* These versions are only needed for systems with more than 38 bits of
|
||||
* physical address space running the 32-bit kernel. That's none atm :-)
|
||||
*/
|
||||
#define __read_64bit_c0_split(source, sel) \
|
||||
({ \
|
||||
unsigned long long val; \
|
||||
unsigned long flags; \
|
||||
\
|
||||
local_irq_save(flags); \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsrl\t%M0, %M0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (val)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsrl\t%M0, %M0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (val)); \
|
||||
local_irq_restore(flags); \
|
||||
\
|
||||
val; \
|
||||
})
|
||||
|
||||
#define __write_64bit_c0_split(source, sel, val) \
|
||||
do { \
|
||||
unsigned long flags; \
|
||||
\
|
||||
local_irq_save(flags); \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dsll\t%L0, %L0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
"dsll\t%M0, %M0, 32\n\t" \
|
||||
"or\t%L0, %L0, %M0\n\t" \
|
||||
"dmtc0\t%L0, " #source "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (val)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dsll\t%L0, %L0, 32\n\t" \
|
||||
"dsrl\t%L0, %L0, 32\n\t" \
|
||||
"dsll\t%M0, %M0, 32\n\t" \
|
||||
"or\t%L0, %L0, %M0\n\t" \
|
||||
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (val)); \
|
||||
local_irq_restore(flags); \
|
||||
} while (0)
|
||||
|
||||
#define read_c0_index() __read_32bit_c0_register($0, 0)
|
||||
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
|
||||
|
||||
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
|
||||
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
|
||||
|
||||
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
|
||||
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_conf() __read_32bit_c0_register($3, 0)
|
||||
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
|
||||
|
||||
#define read_c0_context() __read_ulong_c0_register($4, 0)
|
||||
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
|
||||
|
||||
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
|
||||
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
|
||||
|
||||
#define read_c0_wired() __read_32bit_c0_register($6, 0)
|
||||
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
|
||||
|
||||
#define read_c0_info() __read_32bit_c0_register($7, 0)
|
||||
|
||||
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
|
||||
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
|
||||
|
||||
#define read_c0_count() __read_32bit_c0_register($9, 0)
|
||||
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
|
||||
|
||||
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
|
||||
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
|
||||
|
||||
#define read_c0_compare() __read_32bit_c0_register($11, 0)
|
||||
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
|
||||
|
||||
#define read_c0_status() __read_32bit_c0_register($12, 0)
|
||||
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
|
||||
|
||||
#define read_c0_cause() __read_32bit_c0_register($13, 0)
|
||||
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
|
||||
|
||||
#define read_c0_prid() __read_32bit_c0_register($15, 0)
|
||||
|
||||
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||||
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||||
#define read_c0_config2() __read_32bit_c0_register($16, 2)
|
||||
#define read_c0_config3() __read_32bit_c0_register($16, 3)
|
||||
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
|
||||
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
|
||||
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
|
||||
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
|
||||
|
||||
/*
|
||||
* The WatchLo register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
|
||||
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
|
||||
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
|
||||
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
|
||||
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
|
||||
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
|
||||
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
|
||||
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
|
||||
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
|
||||
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
|
||||
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
|
||||
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
|
||||
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
|
||||
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
|
||||
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
|
||||
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
|
||||
|
||||
/*
|
||||
* The WatchHi register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
|
||||
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
|
||||
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
|
||||
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
|
||||
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
|
||||
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
|
||||
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
|
||||
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
|
||||
|
||||
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
|
||||
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
|
||||
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
|
||||
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
|
||||
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
|
||||
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
|
||||
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
|
||||
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
|
||||
|
||||
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
|
||||
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
|
||||
|
||||
#define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
|
||||
#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
|
||||
|
||||
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
|
||||
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
|
||||
|
||||
#define read_c0_debug() __read_32bit_c0_register($23, 0)
|
||||
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
|
||||
|
||||
#define read_c0_depc() __read_ulong_c0_register($24, 0)
|
||||
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
|
||||
|
||||
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
|
||||
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
|
||||
|
||||
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
|
||||
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
|
||||
|
||||
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
|
||||
|
||||
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
|
||||
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
|
||||
|
||||
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
|
||||
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
|
||||
|
||||
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
|
||||
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
|
||||
|
||||
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
|
||||
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
|
||||
|
||||
#define read_c0_epc() __read_ulong_c0_register($14, 0)
|
||||
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
|
||||
|
||||
#if 1
|
||||
/*
|
||||
* Macros to access the system control coprocessor
|
||||
*/
|
||||
#define read_32bit_cp0_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"mfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define read_32bit_cp0_set1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
/*
|
||||
* For now use this only with interrupts disabled!
|
||||
*/
|
||||
#define read_64bit_cp0_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmfc0\t%0,"STR(source)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define write_32bit_cp0_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
"mtc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value));
|
||||
|
||||
#define write_32bit_cp0_set1_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
"ctc0\t%0,"STR(register)"\n\t" \
|
||||
"nop" \
|
||||
: : "r" (value));
|
||||
|
||||
#define write_64bit_cp0_register(register,value) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips3\n\t" \
|
||||
"dmtc0\t%0,"STR(register)"\n\t" \
|
||||
".set\tmips0" \
|
||||
: : "r" (value))
|
||||
|
||||
/*
|
||||
* This should be changed when we get a compiler that support the MIPS32 ISA.
|
||||
*/
|
||||
#define read_mips32_cp0_config1() \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tnoreorder\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"#.set\tmips64\n\t" \
|
||||
"#mfc0\t$1, $16, 1\n\t" \
|
||||
"#.set\tmips0\n\t" \
|
||||
".word\t0x40018001\n\t" \
|
||||
"move\t%0,$1\n\t" \
|
||||
".set\tat\n\t" \
|
||||
".set\treorder" \
|
||||
:"=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Macros to access the floating point coprocessor control registers
|
||||
*/
|
||||
#define read_32bit_cp1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc1\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
/* TLB operations. */
|
||||
static inline void tlb_probe(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbp\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_read(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbr\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_write_indexed(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwi\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_write_random(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwr\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
/*
|
||||
* Manipulate bits in a c0 register.
|
||||
*/
|
||||
#define __BUILD_SET_C0(name,register) \
|
||||
static inline unsigned int \
|
||||
set_c0_##name(unsigned int set) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res |= set; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
clear_c0_##name(unsigned int clear) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~clear; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
change_c0_##name(unsigned int change, unsigned int new) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~change; \
|
||||
res |= (new & change); \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
}
|
||||
|
||||
__BUILD_SET_C0(status,CP0_STATUS)
|
||||
__BUILD_SET_C0(cause,CP0_CAUSE)
|
||||
__BUILD_SET_C0(config,CP0_CONFIG)
|
||||
|
||||
#define set_cp0_status(x) set_c0_status(x)
|
||||
#define set_cp0_cause(x) set_c0_cause(x)
|
||||
#define set_cp0_config(x) set_c0_config(x)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_MIPSREGS_H */
|
||||
@ -1,442 +0,0 @@
|
||||
/**************************************************************************
|
||||
* *
|
||||
* PROJECT : MIPS port for uC/OS-II *
|
||||
* *
|
||||
* MODULE : SYSDEFS.h *
|
||||
* *
|
||||
* AUTHOR : Michael Anburaj *
|
||||
* URL : http://geocities.com/michaelanburaj/ *
|
||||
* EMAIL: michaelanburaj@hotmail.com *
|
||||
* *
|
||||
* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
|
||||
* *
|
||||
* TOOL-CHAIN : SDE & Cygnus *
|
||||
* *
|
||||
* DESCRIPTION : *
|
||||
* System definitions header file. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef __SYSDEFS_H__
|
||||
#define __SYSDEFS_H__
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Module configuration */
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Interface macro & data definition */
|
||||
|
||||
#ifdef _ASSEMBLER_
|
||||
|
||||
/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
|
||||
|
||||
#ifdef __ghs__
|
||||
#define ALIGN(x) .##align (1 << (x))
|
||||
#else
|
||||
#define ALIGN(x) .##align (x)
|
||||
#endif
|
||||
|
||||
#ifdef __ghs__
|
||||
#define SET_MIPS3()
|
||||
#define SET_MIPS0()
|
||||
#define SET_PUSH()
|
||||
#define SET_POP()
|
||||
#else
|
||||
#define SET_MIPS3() .##set mips3
|
||||
#define SET_MIPS0() .##set mips0
|
||||
#define SET_PUSH() .##set push
|
||||
#define SET_POP() .##set pop
|
||||
#endif
|
||||
|
||||
/* Different assemblers have different requirements for how to
|
||||
* indicate that the next section is bss :
|
||||
*
|
||||
* Some use : .bss
|
||||
* Others use : .section bss
|
||||
*
|
||||
* We select which to use based on _BSS_OLD_, which may be defined
|
||||
* in makefile.
|
||||
*/
|
||||
#ifdef _BSS_OLD_
|
||||
#define BSS .##section bss
|
||||
#else
|
||||
#define BSS .##bss
|
||||
#endif
|
||||
|
||||
#define LEAF(name)\
|
||||
.##text;\
|
||||
.##globl name;\
|
||||
.##ent name;\
|
||||
name:
|
||||
|
||||
|
||||
#define SLEAF(name)\
|
||||
.##text;\
|
||||
.##ent name;\
|
||||
name:
|
||||
|
||||
|
||||
#ifdef __ghs__
|
||||
#define END(name)\
|
||||
.##end name
|
||||
#else
|
||||
#define END(name)\
|
||||
.##size name,.-name;\
|
||||
.##end name
|
||||
#endif
|
||||
|
||||
|
||||
#define EXTERN(name)
|
||||
|
||||
#else
|
||||
|
||||
#define U64 unsigned long long
|
||||
#define U32 unsigned int
|
||||
#define U16 unsigned short
|
||||
#define U8 unsigned char
|
||||
#define S64 signed long long
|
||||
#define S32 int
|
||||
#define S16 short int
|
||||
#define S8 signed char
|
||||
#define bool U8
|
||||
|
||||
#ifndef _SIZE_T_
|
||||
#define _SIZE_T_
|
||||
#ifdef __ghs__
|
||||
typedef unsigned int size_t;
|
||||
#else
|
||||
typedef unsigned long size_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sets the result on bPort */
|
||||
#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask)
|
||||
#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask)
|
||||
|
||||
/* Returns the result */
|
||||
#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask)
|
||||
#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask)
|
||||
|
||||
/* Returns 0 if the condition is False & a non-zero value if it is True */
|
||||
#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask)
|
||||
#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask)
|
||||
|
||||
/* Split union definitions */
|
||||
typedef union tunSU16
|
||||
{
|
||||
U16 hwHW;
|
||||
struct tst2U8
|
||||
{
|
||||
U8 bB0;
|
||||
U8 bB1;
|
||||
}st2U8;
|
||||
}tunSU16;
|
||||
|
||||
typedef union tunSU32
|
||||
{
|
||||
U32 wW;
|
||||
struct tst2U16
|
||||
{
|
||||
U16 hwHW0;
|
||||
U16 hwHW1;
|
||||
}st2U16;
|
||||
struct tst4U8
|
||||
{
|
||||
U8 bB0;
|
||||
U8 bB1;
|
||||
U8 bB2;
|
||||
U8 bB3;
|
||||
}st4U8;
|
||||
}tunSU32;
|
||||
|
||||
#endif /* #ifdef _ASSEMBLER_ */
|
||||
|
||||
|
||||
/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
|
||||
|
||||
|
||||
#define NO_ERR 0x00000000 /* operation completed successfully */
|
||||
#define ERR 0xffffffff /* operation completed not successfully */
|
||||
|
||||
#define False 0
|
||||
#define True !False
|
||||
|
||||
#define NULL ((void *)0)
|
||||
#define MIN(x,y) ((x) < (y) ? (x) : (y))
|
||||
#define MAX(x,y) ((x) > (y) ? (x) : (y))
|
||||
|
||||
#define MAXUINT(w) (\
|
||||
((w) == sizeof(U8)) ? 0xFFU :\
|
||||
((w) == sizeof(U16)) ? 0xFFFFU :\
|
||||
((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
|
||||
)
|
||||
|
||||
#define MAXINT(w) (\
|
||||
((w) == sizeof(S8)) ? 0x7F :\
|
||||
((w) == sizeof(S16)) ? 0x7FFF :\
|
||||
((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
|
||||
)
|
||||
|
||||
#define MSK(n) ((1 << (n)) - 1)
|
||||
|
||||
#define KUSEG_MSK 0x80000000
|
||||
#define KSEG_MSK 0xE0000000
|
||||
#define KUSEGBASE 0x00000000
|
||||
#define KSEG0BASE 0x80000000
|
||||
#define KSEG1BASE 0xA0000000
|
||||
#define KSSEGBASE 0xC0000000
|
||||
#define KSEG3BASE 0xE0000000
|
||||
|
||||
/* Below macros perform the following functions :
|
||||
*
|
||||
* KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
|
||||
* KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
|
||||
* PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
|
||||
* KSSEG : Not relevant for converting, but used for determining range.
|
||||
* KSEG3 : Not relevant for converting, but used for determining range.
|
||||
* KUSEG : Not relevant for converting, but used for determining range.
|
||||
* KSEG0A : Same as KSEG0 but operates on register rather than constant.
|
||||
* KSEG1A : Same as KSEG1 but operates on register rather than constant.
|
||||
* PHYSA : Same as PHYS but operates on register rather than constant.
|
||||
* CACHED : Alias for KSEG0 macro .
|
||||
* (Note that KSEG0 cache attribute is determined by K0
|
||||
* field of Config register, but this is typically cached).
|
||||
* UNCACHED : Alias for KSEG1 macro .
|
||||
*/
|
||||
#ifdef _ASSEMBLER_
|
||||
#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE)
|
||||
#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE)
|
||||
#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE)
|
||||
#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE)
|
||||
#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE)
|
||||
#define PHYS(addr) ( (addr) & ~KSEG_MSK)
|
||||
#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE
|
||||
#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE
|
||||
#define PHYSA(reg) and reg, ~KSEG_MSK
|
||||
#else
|
||||
#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE)
|
||||
#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE)
|
||||
#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE)
|
||||
#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE)
|
||||
#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
|
||||
#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK)
|
||||
#endif
|
||||
|
||||
#define CACHED(addr) KSEG0(addr)
|
||||
#define UNCACHED(addr) KSEG1(addr)
|
||||
|
||||
|
||||
#ifdef _ASSEMBLER_
|
||||
/* Macroes to access variables at constant addresses
|
||||
* Compensates for signed 16 bit displacement
|
||||
* Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD)
|
||||
* sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
|
||||
*/
|
||||
#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000)
|
||||
#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000)
|
||||
#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000)
|
||||
#define LO_OFFS(addr) ((addr) & 0xffff)
|
||||
#endif
|
||||
|
||||
|
||||
/* Most/Least significant 32 bit from 64 bit double word */
|
||||
#define HI32(data64) ((U32)(data64 >> 32))
|
||||
#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF))
|
||||
|
||||
#define REG8( addr ) (*(volatile U8 *) (addr))
|
||||
#define REG16( addr ) (*(volatile U16 *)(addr))
|
||||
#define REG32( addr ) (*(volatile U32 *)(addr))
|
||||
#define REG64( addr ) (*(volatile U64 *)(addr))
|
||||
|
||||
|
||||
/* Register field mapping */
|
||||
#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF)
|
||||
|
||||
/* absolute register address, access */
|
||||
#define REGA(addr) REG32(addr)
|
||||
|
||||
/* physical register address, access: base address + offsett */
|
||||
#define REGP(base,phys) REG32( (U32)(base) + (phys) )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/* relative register address, access: base address + offsett */
|
||||
#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS )
|
||||
|
||||
/**************************************
|
||||
* Macroes not used by YAMON any more
|
||||
* (kept for backwards compatibility)
|
||||
*/
|
||||
/* register read field */
|
||||
#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \
|
||||
>> addr##_##fld##_##SHF)
|
||||
|
||||
/* register write numeric field value */
|
||||
#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
|
||||
| ((intval) << addr##_##fld##_##SHF))
|
||||
|
||||
/* register write enumerated field value */
|
||||
#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
|
||||
| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
|
||||
|
||||
|
||||
/* Examples:
|
||||
*
|
||||
* exccode = REGARD(CPU_CAUSE,EXC);
|
||||
*
|
||||
* REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
|
||||
* | REGAWRE(OSG_CONTROL,DTYPE,PC1);
|
||||
*/
|
||||
|
||||
|
||||
/* register read field */
|
||||
#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \
|
||||
>> offs##_##fld##_##SHF)
|
||||
|
||||
/* register write numeric field value */
|
||||
#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
|
||||
| (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
|
||||
|
||||
/* register write enumerated field value */
|
||||
#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
|
||||
| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
|
||||
|
||||
|
||||
/* physical register read field */
|
||||
#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \
|
||||
>> phys##_##fld##_##SHF)
|
||||
|
||||
/* physical register write numeric field value */
|
||||
#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
|
||||
| ((intval) << phys##_##fld##_##SHF))
|
||||
|
||||
/* physical register write enumerated field value */
|
||||
#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
|
||||
| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
|
||||
/*
|
||||
* End of macroes not used by YAMON any more
|
||||
*********************************************/
|
||||
|
||||
/* Endian related macros */
|
||||
|
||||
#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 )
|
||||
#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
|
||||
|
||||
/* Set byte address to little endian format */
|
||||
#ifdef EL
|
||||
#define SWAP_BYTEADDR_EL(addr) addr
|
||||
#else
|
||||
#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set byte address to big endian format */
|
||||
#ifdef EB
|
||||
#define SWAP_BYTEADDR_EB(addr) addr
|
||||
#else
|
||||
#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set U16 address to little endian format */
|
||||
#ifdef EL
|
||||
#define SWAP_U16ADDR_EL(addr) addr
|
||||
#else
|
||||
#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr )
|
||||
#endif
|
||||
|
||||
/* Set U16 address to big endian format */
|
||||
#ifdef EB
|
||||
#define SWAP_U16ADDR_EB(addr) addr
|
||||
#else
|
||||
#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr )
|
||||
#endif
|
||||
|
||||
#ifdef EL
|
||||
#define REGW32LE(addr, data) REG32(addr) = (data)
|
||||
#define REGR32LE(addr, data) (data) = REG32(addr)
|
||||
#else
|
||||
#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data)
|
||||
#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data)
|
||||
#endif
|
||||
|
||||
/* Set of 'LE'-macros, convert by BE: */
|
||||
#ifdef EL
|
||||
#define CPU_TO_LE32( value ) (value)
|
||||
#define LE32_TO_CPU( value ) (value)
|
||||
|
||||
#define CPU_TO_LE16( value ) (value)
|
||||
#define LE16_TO_CPU( value ) (value)
|
||||
#else
|
||||
#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \
|
||||
((0x0000FF00UL & ((U32)value)) << 8) | \
|
||||
((0x00FF0000UL & ((U32)value)) >> 8) | \
|
||||
( ((U32)value) >> 24) )
|
||||
#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
|
||||
|
||||
#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \
|
||||
((U16)(((U16)value) >> 8)) )
|
||||
#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
|
||||
#endif
|
||||
|
||||
/* Set of 'BE'-macros, convert by LE: */
|
||||
#ifdef EB
|
||||
#define CPU_TO_BE32( value ) (value)
|
||||
#define BE32_TO_CPU( value ) (value)
|
||||
|
||||
#define CPU_TO_BE16( value ) (value)
|
||||
#define BE16_TO_CPU( value ) (value)
|
||||
#else
|
||||
#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \
|
||||
((0x0000FF00UL & ((U32)value)) << 8) | \
|
||||
((0x00FF0000UL & ((U32)value)) >> 8) | \
|
||||
( ((U32)value) >> 24) )
|
||||
#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
|
||||
|
||||
#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \
|
||||
((U16)(((U16)value) >> 8)) )
|
||||
#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
|
||||
#endif
|
||||
|
||||
|
||||
/* Control characters */
|
||||
#define CTRL_A ('A'-0x40)
|
||||
#define CTRL_B ('B'-0x40)
|
||||
#define CTRL_C ('C'-0x40)
|
||||
#define CTRL_D ('D'-0x40)
|
||||
#define CTRL_E ('E'-0x40)
|
||||
#define CTRL_F ('F'-0x40)
|
||||
#define CTRL_H ('H'-0x40)
|
||||
#define CTRL_K ('K'-0x40)
|
||||
#define CTRL_N ('N'-0x40)
|
||||
#define CTRL_P ('P'-0x40)
|
||||
#define CTRL_U ('U'-0x40)
|
||||
#define BACKSPACE 0x08
|
||||
#define DEL 0x7F
|
||||
#define TAB 0x09
|
||||
#define CR 0x0D /* Enter Key */
|
||||
#define LF 0x0A
|
||||
#define ESC 0x1B
|
||||
#define SP 0x20
|
||||
#define CSI 0x9B
|
||||
|
||||
|
||||
/* DEF2STR(x) converts #define symbol to string */
|
||||
#define DEF2STR1(x) #x
|
||||
#define DEF2STR(x) DEF2STR1(x)
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
/* Interface function definition */
|
||||
|
||||
|
||||
/* ********************************************************************* */
|
||||
|
||||
#endif /*__SYSDEFS_H__*/
|
||||
@ -24,6 +24,7 @@
|
||||
/* Here are these common definitions */
|
||||
/* Once your system configration change, just modify the file */
|
||||
|
||||
#include "target/xburst_types.h"
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
|
||||
#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
|
||||
/* SDRAM Timings, unit: ns */
|
||||
@ -33,6 +34,7 @@
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
|
||||
|
||||
|
||||
extern volatile u32 CPU_ID;
|
||||
extern volatile u8 SDRAM_BW16;
|
||||
extern volatile u8 SDRAM_BANK4;
|
||||
@ -49,14 +51,10 @@ extern volatile u8 IS_SHARE;
|
||||
|
||||
extern void gpio_init_4740(void);
|
||||
extern void sdram_init_4740(void);
|
||||
extern void serial_init_4740(void);
|
||||
extern void pll_init_4740(void);
|
||||
|
||||
extern void gpio_init_4750(void);
|
||||
extern void sdram_init_4750(void);
|
||||
extern void serial_init_4750(void);
|
||||
extern void pll_init_4750(void);
|
||||
|
||||
extern void serial_puts(const char *s);
|
||||
extern void gpio_init_4760(void);
|
||||
extern void sdram_init_4760(void);
|
||||
extern void pll_init_4760(void);
|
||||
|
||||
#endif
|
||||
0
usbboot/xburst_include/jz4750.h → usbboot/xburst_include/target/jz4750.h
Executable file → Normal file
0
usbboot/xburst_include/jz4750.h → usbboot/xburst_include/target/jz4750.h
Executable file → Normal file
@ -15,4 +15,8 @@ typedef unsigned char u8;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned int u32;
|
||||
|
||||
#define REG8(addr) *((volatile u8 *)(addr))
|
||||
#define REG16(addr) *((volatile u16 *)(addr))
|
||||
#define REG32(addr) *((volatile u32 *)(addr))
|
||||
|
||||
#endif /* __XBURST_TYPES_H__ */
|
||||
@ -19,8 +19,8 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "jz4740.h"
|
||||
#include "configs.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "target/configs.h"
|
||||
|
||||
void gpio_init_4740(void)
|
||||
{
|
||||
|
||||
@ -19,8 +19,9 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "jz4750.h"
|
||||
#include "configs.h"
|
||||
#include <stdint.h>
|
||||
#include "target/jz4750.h"
|
||||
#include "target/configs.h"
|
||||
|
||||
void gpio_init_4750(void)
|
||||
{
|
||||
|
||||
@ -19,8 +19,8 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "jz4740.h"
|
||||
#include "configs.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "target/configs.h"
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
|
||||
@ -19,8 +19,8 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "jz4750.h"
|
||||
#include "configs.h"
|
||||
#include "target/jz4750.h"
|
||||
#include "target/configs.h"
|
||||
#include "usb_boot_defines.h"
|
||||
|
||||
extern struct fw_args *fw_args;
|
||||
|
||||
@ -18,8 +18,8 @@
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
#include "jz4740.h"
|
||||
#include "configs.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "target/configs.h"
|
||||
#include "usb_boot_defines.h"
|
||||
|
||||
struct fw_args *fw_args;
|
||||
|
||||
@ -19,13 +19,14 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "jz4740.h"
|
||||
#include "usb.h"
|
||||
#include "error.h"
|
||||
#include "usb_boot.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "target/error.h"
|
||||
#include "target/usb_boot.h"
|
||||
#include "usb_boot_defines.h"
|
||||
#include "nandflash.h"
|
||||
#include "udc.h"
|
||||
#include "target/nandflash.h"
|
||||
#include "usb/udc.h"
|
||||
#include "usb/usb.h"
|
||||
|
||||
#define dprintf(x) serial_puts(x)
|
||||
|
||||
unsigned int (*nand_query)(u8 *);
|
||||
|
||||
@ -17,9 +17,9 @@
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
|
||||
#include "nandflash.h"
|
||||
#include "jz4740.h"
|
||||
#include "usb_boot.h"
|
||||
#include "target/nandflash.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "target/usb_boot.h"
|
||||
#include "usb_boot_defines.h"
|
||||
|
||||
#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
|
||||
|
||||
@ -16,9 +16,9 @@
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
#include "jz4750.h"
|
||||
#include "nandflash.h"
|
||||
#include "usb_boot.h"
|
||||
#include "target/jz4750.h"
|
||||
#include "target/nandflash.h"
|
||||
#include "target/usb_boot.h"
|
||||
#include "usb_boot_defines.h"
|
||||
|
||||
#define dprintf(n...)
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
#include "jz4750.h"
|
||||
#include "target/jz4740.h"
|
||||
|
||||
volatile u32 UART_BASE;
|
||||
#define CONFIG_BAUDRATE 57600
|
||||
|
||||
@ -16,10 +16,10 @@
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA
|
||||
*/
|
||||
#include <jz4740.h>
|
||||
#include "usb.h"
|
||||
#include "udc.h"
|
||||
#include "usb_boot.h"
|
||||
#include "target/jz4740.h"
|
||||
#include "usb/usb.h"
|
||||
#include "usb/udc.h"
|
||||
#include "target/usb_boot.h"
|
||||
|
||||
#define dprintf(x...)
|
||||
#define TXFIFOEP0 USB_FIFO_EP0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user