Andres Calderon
|
7c3c9a8380
|
some eth-phy to s6 nets has been routed
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2010-08-20 20:06:53 -05:00 |
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Andres Calderon
|
e0d4a591d6
|
some eth-phy to s6 nets has been routed
|
2010-08-20 19:10:05 -05:00 |
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Andres Calderon
|
033f3616c0
|
some eth-phy to s6 nets has been routed
|
2010-08-20 18:10:16 -05:00 |
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Juan64Bits
|
899d5995f6
|
Routing
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2010-08-20 16:38:29 -05:00 |
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Andres Calderon
|
f12b0a7911
|
PSU ICs has been selected
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2010-08-19 08:51:56 -05:00 |
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Andres Calderon
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f4bebe5f62
|
eth-phy routing startted
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2010-08-19 05:40:42 -05:00 |
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Andres Calderon
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e2867d726e
|
3.3v dc-dc added
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2010-08-18 22:09:52 -05:00 |
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Juan64Bits
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048e8b4322
|
Somthing routing
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2010-08-18 20:15:48 -05:00 |
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Andres Calderon
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ef7e11688c
|
fpga decoupling cap. placement improved
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2010-08-17 19:49:23 -05:00 |
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Andres Calderon
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7be9df3fef
|
fpga decoupling cap. placement improved
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2010-08-17 19:36:33 -05:00 |
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Andres Calderon
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00a88f8396
|
ddr terminators placment
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2010-08-17 19:04:05 -05:00 |
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Andres Calderon
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5c25d1c015
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DDR0 termaintor placement
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2010-08-16 23:30:34 -05:00 |
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Andres Calderon
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cf1645bb44
|
DDR0 termaintor placement
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2010-08-16 22:48:30 -05:00 |
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Andres Calderon
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8cf60ceb3c
|
PSU controller added
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2010-08-16 21:49:00 -05:00 |
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Andres Calderon
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2df63e4aea
|
ddr termination placement
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2010-08-16 20:56:08 -05:00 |
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Andres Calderon
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f1c6506b1e
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terminal resistors placement
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2010-08-16 19:36:21 -05:00 |
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Andres Calderon
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ba734f70bf
|
terminal resistors placement
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2010-08-16 19:06:33 -05:00 |
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Juan64Bits
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16026245e7
|
Series resistors (DDR) added
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2010-08-16 16:32:29 -05:00 |
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Andres Calderon
|
170ed5aa15
|
fix
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2010-08-14 10:43:33 -05:00 |
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Andres Calderon
|
4110ee21c8
|
fixed FPGA component bug
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2010-08-14 08:23:56 -05:00 |
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Andres Calderon
|
ef72b751a5
|
eth-phy placement
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2010-08-14 07:42:37 -05:00 |
|
Andres Calderon
|
fae8765d04
|
improved placement
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2010-08-13 22:09:52 -05:00 |
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Andres Calderon
|
e07bc340e0
|
decoupling nand flash added
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2010-08-13 18:38:38 -05:00 |
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Andres Calderon
|
8f8f332469
|
decoupling DDR cap. placement
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2010-08-13 18:20:50 -05:00 |
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Andres Calderon
|
333097ec1d
|
VCC fixed
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2010-08-13 17:34:12 -05:00 |
|
Andres Calderon
|
ef75347b57
|
spi memory added
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2010-08-13 15:42:35 -05:00 |
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Juan64Bits
|
37912ec628
|
FPGA decoupling capacitors
|
2010-08-13 11:24:39 -05:00 |
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Andres Calderon
|
35a1b35c7f
|
usb added
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2010-08-13 09:27:10 -05:00 |
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Andres Calderon
|
da7ba80fda
|
preliminary placement improved
|
2010-08-13 06:16:55 -05:00 |
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Andres Calderon
|
e1ce2a9e8f
|
fix
|
2010-08-12 21:12:14 -05:00 |
|
Andres Calderon
|
e678c0e51a
|
fixed placement
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2010-08-12 16:12:57 -05:00 |
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Juan64Bits
|
11bf380cc6
|
Fixing USB connections
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2010-08-10 21:25:32 -05:00 |
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Andres Calderon
|
57948cfc83
|
SD connector attached to th S6
|
2010-08-10 18:09:38 -05:00 |
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Andres Calderon
|
cac88e3756
|
DDR de-coupling caps. added
|
2010-08-10 17:38:37 -05:00 |
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Andres Calderon
|
a8fcbf091c
|
early placement
|
2010-08-09 22:25:05 -05:00 |
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Andres Calderon
|
171e409036
|
annotate
|
2010-08-09 21:55:50 -05:00 |
|
Andres Calderon
|
11ade0f1e8
|
ddr footprint changed
|
2010-08-09 21:29:52 -05:00 |
|
Juan64Bits
|
b22aa62b24
|
Ethernet-phy and USB connected to FPGA
|
2010-08-09 15:37:18 -05:00 |
|
Andres Calderon
|
bd2d314d9c
|
cleanup
|
2010-08-08 21:31:12 -05:00 |
|
Andres Calderon
|
5197a47953
|
ddr address and data has been conected to the FPGA
|
2010-08-04 20:50:31 -05:00 |
|
Andres Calderon
|
3e25e8dec9
|
ddr mobile replaced by ddr
|
2010-08-03 21:23:17 -05:00 |
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Andres Calderon
|
1580e66a1e
|
only one wire connected
|
2010-07-28 06:48:02 -05:00 |
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Andres Calderon
|
d79faef060
|
some ethernet phy conections
|
2010-07-27 20:09:20 -05:00 |
|
Andres Calderon
|
a8cbac05c9
|
chie renamed to xue
|
2010-07-24 14:02:57 -05:00 |
|