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correct the jz4760 lepus board mem parameter:

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ARG_ROW_ADDR = 13;
ARG_COL_ADDR = 10;

Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
This commit is contained in:
Xiangfu Liu 2010-06-13 23:06:03 +08:00
parent 031b54c699
commit 3272119164
2 changed files with 9 additions and 12 deletions
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11
xbboot/target-stage1/board-jz4760.c
View File

@ -124,12 +124,11 @@ void pll_init_4760()
/** divisors,
* for jz4760 ,I:H:H2:P:M:S.
* DIV should be one of [1, 2, 3, 4, 6, 8]
* DIV should be one of [1, 2, 3, 4, 6, 8] like:
* div[6] = {1, 2, 2, 2, 2, 2};
* div[6] = {1, 3, 6, 6, 6, 6};
*/
// int div[6] = {1, 2, 4, 4, 4, 4};
// int div[6] = {1, 3, 6, 6, 6, 6};
int div[6] = {1, 2, 2, 2, 2, 2};
int pllout2;
int div[6] = {1, 2, 4, 4, 4, 4};
cfcr = CPM_CPCCR_PCS |
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
@ -152,8 +151,6 @@ void pll_init_4760()
#endif
cfcr |= CPM_CPCCR_CE;
pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL);
plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */
| CPM_CPPCR_PLLEN; /* enable PLL */

4
xbboot/target-stage1/stage1.c
View File

@ -43,8 +43,8 @@ void load_args_4760()
ARG_UART_BAUD = 57600;
ARG_BUS_WIDTH_16 = * (int *)0x80002014;
ARG_BANK_ADDR_2BIT = 4;
ARG_ROW_ADDR = 12;
ARG_COL_ADDR = 9;
ARG_ROW_ADDR = 13;
ARG_COL_ADDR = 10;
}