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synced 2024-11-01 10:22:48 +02:00
correct the jz4760 lepus board mem parameter:
ARG_ROW_ADDR = 13; ARG_COL_ADDR = 10; Signed-off-by: Xiangfu Liu <xiangfu@sharism.cc>
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031b54c699
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3272119164
@ -122,14 +122,13 @@ void pll_init_4760()
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0, 0, 1, 2, 3, 0, 4, 0, 5
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};
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/** divisors,
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/** divisors,
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* for jz4760 ,I:H:H2:P:M:S.
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* DIV should be one of [1, 2, 3, 4, 6, 8]
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*/
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// int div[6] = {1, 2, 4, 4, 4, 4};
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// int div[6] = {1, 3, 6, 6, 6, 6};
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int div[6] = {1, 2, 2, 2, 2, 2};
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int pllout2;
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* DIV should be one of [1, 2, 3, 4, 6, 8] like:
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* div[6] = {1, 2, 2, 2, 2, 2};
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* div[6] = {1, 3, 6, 6, 6, 6};
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*/
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int div[6] = {1, 2, 4, 4, 4, 4};
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cfcr = CPM_CPCCR_PCS |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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@ -152,11 +151,9 @@ void pll_init_4760()
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#endif
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cfcr |= CPM_CPCCR_CE;
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? ARG_CPU_SPEED : (ARG_CPU_SPEED / 2);
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plcr1 = pll_calc_m_n_od(ARG_CPU_SPEED, ARG_EXTAL);
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plcr1 |= (0x20 << CPM_CPPCR_PLLST_BIT) /* PLL stable time */
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| CPM_CPPCR_PLLEN; /* enable PLL */
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| CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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@ -43,8 +43,8 @@ void load_args_4760()
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ARG_UART_BAUD = 57600;
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ARG_BUS_WIDTH_16 = * (int *)0x80002014;
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ARG_BANK_ADDR_2BIT = 4;
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ARG_ROW_ADDR = 12;
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ARG_COL_ADDR = 9;
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ARG_ROW_ADDR = 13;
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ARG_COL_ADDR = 10;
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}
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