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Code

Fixing some examples, adding scripts for compiling xilinx libs with ghdl

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This commit is contained in:
Carlos Camargo 2010-08-31 09:39:37 -05:00
parent b6f32d536f
commit acf516e22d
53 changed files with 13780 additions and 175 deletions
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46
Examples/sram/logic/simulation/work/_info
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m255
13
cModel Technology
d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
vglbl
IT?5S;>bN`@zG_25]R_4A33
VnN]4Gon>inod6>M^M2[SV1
w1273510321
Fglbl.v
L0 5
OE;L;6.0d;29
r1
31
o+libext+.v
vsram_bus
I4L5C3LJ<U_bBN0U__mYo>0
V7R>S0^PdJz?6eY;E[l1^E2
w1273543761
F../sram_bus.v
L0 2
OE;L;6.0d;29
r1
31
o+libext+.v
vsram_bus_TB
IeNSImUgW[X4l`QoUVUKI`3
V<VFiY^801Z<UUJ?^z?JM20
w1273676679
F../sram_bus_TB.v
L0 3
OE;L;6.0d;29
r1
31
o+libext+.v
nsram_bus_@t@b
vsram_bus_TB_v
IA=m;kT@<eh:`ekMlOPXX@0
VQ[@Nfjd=de;Dc[[gj0bf41
w1273541944
F../sram_bus_TB.v
L0 3
OE;L;6.0d;29
r1
31
o+libext+.v
nsram_bus_@t@b_v

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Examples/sram/logic/simulation/work/glbl/_primary.dat
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Examples/sram/logic/simulation/work/glbl/_primary.vhd
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library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;

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Examples/sram/logic/simulation/work/glbl/verilog.asm
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Examples/sram/logic/simulation/work/sram_bus/_primary.dat
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Examples/sram/logic/simulation/work/sram_bus/_primary.vhd
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library verilog;
use verilog.vl_types.all;
entity sram_bus is
generic(
B : integer := 7
);
port(
clk : in vl_logic;
sram_data : inout vl_logic_vector;
addr : in vl_logic_vector(12 downto 0);
nwe : in vl_logic;
ncs : in vl_logic;
noe : in vl_logic;
reset : in vl_logic;
led : out vl_logic
);
end sram_bus;

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Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat
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Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd
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library verilog;
use verilog.vl_types.all;
entity sram_bus_TB_v is
generic(
PERIOD : integer := 20;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer := 0;
TSET : integer := 3;
THLD : integer := 3;
NWS : integer := 3;
CAM_OFF : integer := 4000
);
end sram_bus_TB_v;

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Examples/sram/logic/Makefile → Examples/sram_gpio/logic/Makefile
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Examples/sram_gpio/logic/sim/ddr/ddr.v Normal file
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Examples/sram_gpio/logic/sim/ddr/ddr_parameters.vh Normal file
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/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
// `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
parameter tDQSQ = 0.45; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
parameter tRP = 15.0; // tRP ns Precharge command period
parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
parameter tWR = 15.0; // tWR ns Write recovery time
// Size Parameters based on Part Width
//`else `define x16
parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter full_mem_bits = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
parameter part_mem_bits = 14; // Set this parameter to control how many unique addresses are used
parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors
parameter Debug = 1; // Turn on debug message

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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: mig_v1_73_b0 $
// \ \ Application : MIG
// / / Filename : mem_interface_top_parameters_0.v
// /___/ /\ Date Last Modified : $Date: 2007/06/06 05:44:42 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3E/3A
// Design Name : DDR1 SDRAM
// Purpose : This module has the parameters used in the design.
///////////////////////////////////////////////////////////////////////////////
`define data_width 16
`define data_strobe_width 2
`define data_mask_width 2
`define clk_width 1
`define fifo_16 1
`define ReadEnable 1
`define memory_width 8
`define DatabitsPerReadClock 8
`define DatabitsPerMask 8
`define no_of_cs 1
`define data_mask 1
`define mask_disable 0
`define RESET 0
`define cke_width 1
`define registered 0
`define col_ap_width 11
`define write_pipe_itr 1
`define write_pipeline 4
`define top_bottom 0
`define left_right 1
`define row_address 13
`define column_address 10
`define bank_address 2
`define spartan3e 1
`define burst_length 3'b001
`define burst_type 1'b0
`define cas_latency_value 3'b110
`define Operating_mode 5'b00000
`define load_mode_register 13'b0000001100001
`define drive_strengh 1'b0
`define dll_enable 1'b0
`define ext_load_mode_register 13'b0000000000000
`define chip_address 1
`define reset_active_low 1'b1
`define rcd_count_value 3'b001
`define ras_count_value 4'b0101
`define mrd_count_value 1'b0
`define rp_count_value 3'b001
`define rfc_count_value 6'b001001
`define twr_count_value 3'b110
`define twtr_count_value 3'b100
`define max_ref_width 11
`define max_ref_cnt 11'b10000000001
`timescale 1ns/100ps

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********************************************************************************************
The sim folder has sample test_bench files to simulate the designs in Modelsim environment.
This folder has the memory model, test bench, glbl file and required parameter files.
Read the steps in this file before simulations are done.
To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI
options.
Data_width : 64
HDL : Verilog or VHDL
Memory configuration : x16
DIMM/Component : Component
Memory Part No : MT46V16M16XX-5
Add test bench : Yes
Use DCM : Yes
Number of controllers : 1
Number of Write pipelines : 4
-----------------------------------------------For Verilog or VHDL----------------------------------------------------------
1. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder
to the project Also add the memory model, test bench and glbl files from the sim folder.
2. Compile the design.
3. After successful compilation of design load the design using the following comamnd.
vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
Note : User should set proper path for unisim verilog libraries
4. After the design is successfully loaded, run the simulations and view the waveforms.
Notes :
1. To run simulations for different data widths and configurations, users should modify the test bench files
with right memory models and design files.
2. User must manually change the frequency of the test bench for proper simulations.
3. Users should modify the test bench files for without test bench case.

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//---------------------------------------------------------------------------
// Behavioral model of a static ram chip
//
// Organization:
//
// 16 bit x 2**(adr_width-1)
//---------------------------------------------------------------------------
module sram16 #(
parameter adr_width = 18
) (
input [adr_width-1:0] adr,
inout [15:0] dat,
input ub_n,
input lb_n,
input cs_n,
input we_n,
input oe_n
);
parameter dat_width = 16;
//---------------------------------------------------------------------------
// Actual RAM cells
//---------------------------------------------------------------------------
reg [7:0] mem_ub [0:1<<adr_width];
reg [7:0] mem_lb [0:1<<adr_width];
//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
wire [15:0] mem = { mem_ub[adr], mem_lb[adr] };
wire [15:0] zzz = 16'bz;
// Drive output
assign dat = (!cs_n && !oe_n) ? mem : zzz;
// Write to UB
always @(*)
if (!cs_n && !we_n && !ub_n)
mem_ub[adr] = dat[15:8];
// Write to LB
always @(*)
if (!cs_n && !we_n && !lb_n)
mem_lb[adr] = dat[7:0];
always @(*)
if (!we_n && !oe_n)
$display("Operational error in RamChip: OE and WE both active");
endmodule

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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5.158.1 2007/03/09 18:13:02 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Global Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// End Revision
`timescale 100 ps / 10 ps
module BUFG (O, I);
output O;
input I;
buf B1 (O, I);
endmodule

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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.27)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
// /___/ /\ Filename : FDDRRSE.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678)
// 10/20/05 - Add set & reset check to main block. (CR219794)
// 10/28/05 - combine strobe block and data block. (CR220298).
// 2/07/06 - Remove set & reset from main block and add specify block (CR225119)
// 2/10/06 - Change Q from reg to wire (CR 225613)
// End Revision
`timescale 1 ps / 1 ps
module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
parameter INIT = 1'h0;
output Q;
input C0, C1, CE, D0, D1, R, S;
wire Q;
reg q_out;
reg q0_out, q1_out;
reg C0_tmp, C1_tmp;
initial begin
q_out = INIT;
q0_out = INIT;
q1_out = INIT;
C0_tmp = 0;
C1_tmp = 0;
end
assign Q = q_out;
always @(posedge C0)
if (CE == 1 || R == 1 || S == 1) begin
C0_tmp <= 1;
C0_tmp <= #100 0;
end
always @(posedge C1)
if (CE == 1 || R == 1 || S == 1) begin
C1_tmp <= 1;
C1_tmp <= #100 0;
end
always @(posedge C0)
if (R)
q0_out <= 0;
else if (S)
q0_out <= 1;
else if (CE)
q0_out <= D0;
always @(posedge C1)
if (R)
q1_out <= 0;
else if (S)
q1_out <= 1;
else if (CE)
q1_out <= D1;
always @(posedge C0_tmp or posedge C1_tmp )
if (C1_tmp)
q_out = q1_out;
else
q_out = q0_out;
specify
if (R)
(posedge C0 => (Q +: 1'b0)) = (100, 100);
if (!R && S)
(posedge C0 => (Q +: 1'b1)) = (100, 100);
if (!R && !S && CE)
(posedge C0 => (Q +: D0)) = (100, 100);
if (R)
(posedge C1 => (Q +: 1'b0)) = (100, 100);
if (!R && S)
(posedge C1 => (Q +: 1'b1)) = (100, 100);
if (!R && !S && CE)
(posedge C1 => (Q +: D1)) = (100, 100);
endspecify
endmodule

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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
// /___/ /\ Filename : RAMB16_S2.v
// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// End Revision
`ifdef legacy_model
`timescale 1 ps / 1 ps
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
parameter INIT = 2'h0;
parameter SRVAL = 2'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DO;
reg do0_out, do1_out;
input [12:0] ADDR;
input [1:0] DI;
input EN, CLK, WE, SSR;
reg [18431:0] mem;
reg [8:0] count;
reg [1:0] wr_mode;
wire [12:0] addr_int;
wire [1:0] di_int;
wire en_int, clk_int, we_int, ssr_int;
tri0 GSR = glbl.GSR;
always @(GSR)
if (GSR) begin
assign do0_out = INIT[0];
assign do1_out = INIT[1];
end
else begin
deassign do0_out;
deassign do1_out;
end
buf b_do_out0 (DO[0], do0_out);
buf b_do_out1 (DO[1], do1_out);
buf b_addr_0 (addr_int[0], ADDR[0]);
buf b_addr_1 (addr_int[1], ADDR[1]);
buf b_addr_2 (addr_int[2], ADDR[2]);
buf b_addr_3 (addr_int[3], ADDR[3]);
buf b_addr_4 (addr_int[4], ADDR[4]);
buf b_addr_5 (addr_int[5], ADDR[5]);
buf b_addr_6 (addr_int[6], ADDR[6]);
buf b_addr_7 (addr_int[7], ADDR[7]);
buf b_addr_8 (addr_int[8], ADDR[8]);
buf b_addr_9 (addr_int[9], ADDR[9]);
buf b_addr_10 (addr_int[10], ADDR[10]);
buf b_addr_11 (addr_int[11], ADDR[11]);
buf b_addr_12 (addr_int[12], ADDR[12]);
buf b_di_0 (di_int[0], DI[0]);
buf b_di_1 (di_int[1], DI[1]);
buf b_en (en_int, EN);
buf b_clk (clk_int, CLK);
buf b_we (we_int, WE);
buf b_ssr (ssr_int, SSR);
initial begin
for (count = 0; count < 256; count = count + 1) begin
mem[count] <= INIT_00[count];
mem[256 * 1 + count] <= INIT_01[count];
mem[256 * 2 + count] <= INIT_02[count];
mem[256 * 3 + count] <= INIT_03[count];
mem[256 * 4 + count] <= INIT_04[count];
mem[256 * 5 + count] <= INIT_05[count];
mem[256 * 6 + count] <= INIT_06[count];
mem[256 * 7 + count] <= INIT_07[count];
mem[256 * 8 + count] <= INIT_08[count];
mem[256 * 9 + count] <= INIT_09[count];
mem[256 * 10 + count] <= INIT_0A[count];
mem[256 * 11 + count] <= INIT_0B[count];
mem[256 * 12 + count] <= INIT_0C[count];
mem[256 * 13 + count] <= INIT_0D[count];
mem[256 * 14 + count] <= INIT_0E[count];
mem[256 * 15 + count] <= INIT_0F[count];
mem[256 * 16 + count] <= INIT_10[count];
mem[256 * 17 + count] <= INIT_11[count];
mem[256 * 18 + count] <= INIT_12[count];
mem[256 * 19 + count] <= INIT_13[count];
mem[256 * 20 + count] <= INIT_14[count];
mem[256 * 21 + count] <= INIT_15[count];
mem[256 * 22 + count] <= INIT_16[count];
mem[256 * 23 + count] <= INIT_17[count];
mem[256 * 24 + count] <= INIT_18[count];
mem[256 * 25 + count] <= INIT_19[count];
mem[256 * 26 + count] <= INIT_1A[count];
mem[256 * 27 + count] <= INIT_1B[count];
mem[256 * 28 + count] <= INIT_1C[count];
mem[256 * 29 + count] <= INIT_1D[count];
mem[256 * 30 + count] <= INIT_1E[count];
mem[256 * 31 + count] <= INIT_1F[count];
mem[256 * 32 + count] <= INIT_20[count];
mem[256 * 33 + count] <= INIT_21[count];
mem[256 * 34 + count] <= INIT_22[count];
mem[256 * 35 + count] <= INIT_23[count];
mem[256 * 36 + count] <= INIT_24[count];
mem[256 * 37 + count] <= INIT_25[count];
mem[256 * 38 + count] <= INIT_26[count];
mem[256 * 39 + count] <= INIT_27[count];
mem[256 * 40 + count] <= INIT_28[count];
mem[256 * 41 + count] <= INIT_29[count];
mem[256 * 42 + count] <= INIT_2A[count];
mem[256 * 43 + count] <= INIT_2B[count];
mem[256 * 44 + count] <= INIT_2C[count];
mem[256 * 45 + count] <= INIT_2D[count];
mem[256 * 46 + count] <= INIT_2E[count];
mem[256 * 47 + count] <= INIT_2F[count];
mem[256 * 48 + count] <= INIT_30[count];
mem[256 * 49 + count] <= INIT_31[count];
mem[256 * 50 + count] <= INIT_32[count];
mem[256 * 51 + count] <= INIT_33[count];
mem[256 * 52 + count] <= INIT_34[count];
mem[256 * 53 + count] <= INIT_35[count];
mem[256 * 54 + count] <= INIT_36[count];
mem[256 * 55 + count] <= INIT_37[count];
mem[256 * 56 + count] <= INIT_38[count];
mem[256 * 57 + count] <= INIT_39[count];
mem[256 * 58 + count] <= INIT_3A[count];
mem[256 * 59 + count] <= INIT_3B[count];
mem[256 * 60 + count] <= INIT_3C[count];
mem[256 * 61 + count] <= INIT_3D[count];
mem[256 * 62 + count] <= INIT_3E[count];
mem[256 * 63 + count] <= INIT_3F[count];
end
end
initial begin
case (WRITE_MODE)
"WRITE_FIRST" : wr_mode <= 2'b00;
"READ_FIRST" : wr_mode <= 2'b01;
"NO_CHANGE" : wr_mode <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
$finish;
end
endcase
end
always @(posedge clk_int) begin
if (en_int == 1'b1) begin
if (ssr_int == 1'b1) begin
do0_out <= SRVAL[0];
do1_out <= SRVAL[1];
end
else begin
if (we_int == 1'b1) begin
if (wr_mode == 2'b00) begin
do0_out <= di_int[0];
do1_out <= di_int[1];
end
else if (wr_mode == 2'b01) begin
do0_out <= mem[addr_int * 2 + 0];
do1_out <= mem[addr_int * 2 + 1];
end
else begin
do0_out <= do0_out;
do1_out <= do1_out;
end
end
else begin
do0_out <= mem[addr_int * 2 + 0];
do1_out <= mem[addr_int * 2 + 1];
end
end
end
end
always @(posedge clk_int) begin
if (en_int == 1'b1 && we_int == 1'b1) begin
mem[addr_int * 2 + 0] <= di_int[0];
mem[addr_int * 2 + 1] <= di_int[1];
end
end
specify
(CLK *> DO) = (100, 100);
endspecify
endmodule
`else
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
// /___/ /\ Filename : RAMB16_S2.v
// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/10/05 - Initialized outputs.
// End Revision
`timescale 1 ps/1 ps
module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
parameter INIT = 2'h0;
parameter SRVAL = 2'h0;
parameter WRITE_MODE = "WRITE_FIRST";
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DO;
input [12:0] ADDR;
input [1:0] DI;
input EN, CLK, WE, SSR;
reg [1:0] do_out = INIT[1:0];
reg [1:0] mem [8191:0];
reg [8:0] count, countp;
reg [1:0] wr_mode;
wire [12:0] addr_int;
wire [1:0] di_int;
wire en_int, clk_int, we_int, ssr_int;
wire di_enable = en_int && we_int;
tri0 GSR = glbl.GSR;
wire gsr_int;
buf b_gsr (gsr_int, GSR);
buf b_do [1:0] (DO, do_out);
buf b_addr [12:0] (addr_int, ADDR);
buf b_di [1:0] (di_int, DI);
buf b_en (en_int, EN);
buf b_clk (clk_int, CLK);
buf b_ssr (ssr_int, SSR);
buf b_we (we_int, WE);
always @(gsr_int)
if (gsr_int) begin
assign {do_out} = INIT;
end
else begin
deassign do_out;
end
initial begin
for (count = 0; count < 128; count = count + 1) begin
mem[count] = INIT_00[(count * 2) +: 2];
mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
end
end // initial begin
initial begin
case (WRITE_MODE)
"WRITE_FIRST" : wr_mode <= 2'b00;
"READ_FIRST" : wr_mode <= 2'b01;
"NO_CHANGE" : wr_mode <= 2'b10;
default : begin
$display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
$finish;
end
endcase
end
always @(posedge clk_int) begin
if (en_int == 1'b1) begin
if (ssr_int == 1'b1) begin
{do_out} <= #100 SRVAL;
end
else begin
if (we_int == 1'b1) begin
if (wr_mode == 2'b00) begin
do_out <= #100 di_int;
end
else if (wr_mode == 2'b01) begin
do_out <= #100 mem[addr_int];
end
end
else begin
do_out <= #100 mem[addr_int];
end
end
// memory
if (we_int == 1'b1) begin
mem[addr_int] <= di_int;
end
end
end
endmodule
`endif

1710
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S18.v Normal file
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1536
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S2.v Normal file
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1835
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S36.v Normal file
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1555
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S4.v Normal file
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1648
Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S9.v Normal file
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File diff suppressed because it is too large Load Diff

0
Examples/sram/logic/simulation/glbl.v → Examples/sram_gpio/logic/simulation/glbl.v
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0
Examples/sram/logic/simulation/sram_bus_TB.do → Examples/sram_gpio/logic/simulation/sram_bus_TB.do
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0
Examples/sram/logic/simulation/sram_bus_TIMING_TB.do → Examples/sram_gpio/logic/simulation/sram_bus_TIMING_TB.do
View File

0
Examples/sram/logic/simulation/transcript → Examples/sram_gpio/logic/simulation/transcript
View File

0
Examples/sram/logic/simulation/vsim.wlf → Examples/sram_gpio/logic/simulation/vsim.wlf
View File

0
Examples/sram/logic/simulation/wave.do → Examples/sram_gpio/logic/simulation/wave.do
View File

0
Examples/sram/logic/sram_bus.ucf → Examples/sram_gpio/logic/sram_bus.ucf
View File

0
Examples/sram/logic/sram_bus.v → Examples/sram_gpio/logic/sram_bus.v
View File

0
Examples/sram/logic/sram_bus_TB.v → Examples/sram_gpio/logic/sram_bus_TB.v
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0
Examples/sram/src/Makefile → Examples/sram_gpio/src/Makefile
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40
Examples/sram_gpio/src/enable_irq.c Normal file
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@ -0,0 +1,40 @@
/*
JZ47xx test gpio
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
Carlos Camargo cicamargoba@unal.edu.co
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include <stdio.h>
#include <unistd.h>
#include "jz47xx_gpio.h"
#define IRQ_PORT JZ_GPIO_PORT_C
#define IRQ_PIN 15
int
main ()
{
JZ_PIO *pio = jz_gpio_map (IRQ_PORT);
if (!pio)
return -1;
jz_gpio_as_irq (pio, IRQ_PIN);
return 0;
}

0
Examples/sram/src/enable_rx.c → Examples/sram_gpio/src/enable_rx.c
View File

0
Examples/sram/src/jz47xx_gpio.c → Examples/sram_gpio/src/jz47xx_gpio.c
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0
Examples/sram/src/jz47xx_gpio.h → Examples/sram_gpio/src/jz47xx_gpio.h
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0
Examples/sram/src/jz47xx_mmap.c → Examples/sram_gpio/src/jz47xx_mmap.c
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0
Examples/sram/src/jz47xx_mmap.h → Examples/sram_gpio/src/jz47xx_mmap.h
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0
Examples/sram/src/jz_init_sram.c → Examples/sram_gpio/src/jz_init_sram.c
View File

15
Examples/sram/src/jz_test_gpio.c → Examples/sram_gpio/src/jz_test_gpio.c
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@ -23,12 +23,21 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
#include "jz47xx_gpio.h"
#define TEST_PORT JZ_GPIO_PORT_C
#define TEST_PIN 17
//#define TEST_PORT JZ_GPIO_PORT_C
//#define TEST_PIN 17
int
main ()
main (int argc,char *argv[])
{
int TEST_PORT, TEST_PIN;
if(argc != 3){
fprintf(stderr,"\nUsage: %s TEST_PIN_PORT(A=0, B=1, C=2, D=3) TEST_PIN \n",argv[0]);
}
TEST_PORT = ;
TEST_PIN = ;
JZ_PIO *pio = jz_gpio_map (TEST_PORT);
if (!pio)

2
binaries/sie_rootfs_files/etc/init.d/start
View File

@ -2,4 +2,4 @@
/usr/bin/xc3sprog /root/binaries/ADC.bit
/usr/bin/sgen -f 1000 &
/root/binaries/ADC -qws -nomouse &
/root/binaries/enable_rx

44
lm32/logic/sakc/firmware/boot0-serial/image.bin
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@ -1,44 +0,0 @@
S00C0000696D6167652E62696E89
S113000098000000D00000007801000038210000B2
S1130010D0E10000F80000033400000034000000C8
S1130020781C00003B9C0FFC781A00003B5A02A08D
S11300307801000038210298780300003863029C9C
S1130040442300045820000034210004E3FFFFFD92
S1130050340100003402000034030000F800001DE5
S113006034010001D0010000C3A000003401000FDE
S1130070D0210000C3A0000034010000D001000022
S1130080C3A00000C0200000E0000000379CFFF87F
S11300905B8B00085B9D0004F80000573C2B0008B4
S11300A0F8000055B56108003C2B0008F800005228
S11300B0B56108003C2B0008F800004FB56108004A
S11300C02B9D00042B8B0008379C0008C3A0000064
S11300D0379CFFE45B8B001C5B8C00185B8D001469
S11300E05B8E00105B8F000C5B9000085B9D00042E
S11300F0F8000040340D00673401002A340E007506
S1130100340F006478100000442D0008442E0016BB
S1130110442F000ABA00080038210270F800004891
S1130120F80000355C2DFFFAFBFFFFD9FBFFFFD67B
S1130130F8000031E3FFFFFCFBFFFFD5B8205800B7
S1130140FBFFFFD3B5616000516CFFF64161000015
S1130150356B0001F8000031558BFFFDF8000026D7
S1130160E3FFFFF1FBFFFFCAB8205800FBFFFFC805
S1130170B5616000516CFFEBF800001F31610000B5
S1130180356B0001558BFFFDF800001BE3FFFFE614
S113019078020000384202903803C350284200001D
S11301A0882308005841001034010000584100140D
S11301B03401000A5841000C2841000C20210001A0
S11301C04420FFFEC3A00000780100003821029003
S11301D0282100003802C3505822000434020000D1
S11301E0582200083402000E58220000C3A0000068
S11301F0C3A00000780100003821028C28220000EE
S113020028410000202100014420FFFE2841000471
S1130210202100FFC3A00000780200003842028CB5
S113022028430000202100FF286200002042001023
S11302305C40FFFE58610004C3A00000402400009D
S11302404480000B780200003842028C28430000EE
S113025028620000204200105C40FFFE5864000445
S113026034210001402400005C82FFFAC3A0000096
S11302702A2A53414B432F626F6F746C6F6164651C
S10F0280722A2A203E200D0A0000000013
S10F028CF0000000F0010000F00200008F
S9030000FC

42
plasma/gpio/gpio.c
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@ -3,9 +3,6 @@
#define MemoryRead(A) (*(volatile unsigned long*)(A))
#define MemoryWrite(A,V) *(volatile unsigned long*)(A)=(V)
typedef unsigned long uint32;
typedef unsigned short uint16;
int main(void)
{
@ -13,23 +10,29 @@ int main(void)
volatile unsigned short *data16;
volatile unsigned int *data32;
volatile unsigned char test8;
volatile unsigned short test16;
volatile unsigned int test32, tmp;
volatile unsigned long test64;
/*
Operaciones de acceso a memoria
*/
data8 = (unsigned char *)(0x20000410);
data16 = (unsigned short *)(0x20000210);
data32 = (unsigned int *)(0x20000330);
*data8 = 0x10;
*data8 = 0x44;
data8++;
*data8 = 0x66;
data8++;
*data8 = 0x55;
data8++;
*data8 = 0x22;
data8++;
*data8 = 0x11;
data8++;
*data8 = 0x12;
data8++;
*data8 = 0x13;
data8++;
*data8 = 0x14;
*data16 = 0x2020;
data16++;
@ -60,6 +63,25 @@ int main(void)
data32 = (unsigned int *)(0x20000020);
test32 = *data32;
/*
Operaciones aritméticas
*/
test32 = test32 + test8;
test32 = 0x11111111 + test32;
test32 = 0x1111 + test32;
test32 = test32 + *data32;
test64 = test32 * test8;
test64 = 0x11111111 * test32;
test64 = 0x1111 * test32;
test64 = test32 * *data32;
while(1){
}

4
plasma/logic/Makefile
View File

@ -1,3 +1,7 @@
##########################################################
### WARNING YOU MUST SET THE VARIABLE XILINX FIRST ##
### /install_dir/Xilinx/10.1/ISE/
##########################################################
DESIGN = plasma
PINS = $(DESIGN).ucf
DEVICE = xc3s500e-VQ100-4

60
plasma/logic/ram_image.vhd
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@ -47,12 +47,12 @@ INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"3c34ac343c34a42434a42434a42434a02434a02434a02434a02434a024343c27",
INIT_05 => X"8cac343caf008c34a730009434a330009034af008ca730009434a3300090ac34",
INIT_06 => X"82240c00142400100080afafaf270003ac3c1030008c343c0008af008c34af00",
INIT_07 => X"26240c2608240c00102c3002242400afafafaf2727038f8f8f0000140082260c",
INIT_08 => X"2703008f8c3c10000caf2730038c343c2703008f240caf2727038f8f8f8f0216",
INIT_09 => X"000000000000000000000000000000000024038c001424ac00008c243c3c243c",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"008f300093af00008f8caf24008faf00343c8faf00008f300093af008c34af00",
INIT_07 => X"30008c343c0008af0000008f8caf00000000008faf000000000000008faf0000",
INIT_08 => X"2727038f8f8f0000140082260c82240c00142400100080afafaf270003ac3c10",
INIT_09 => X"8f240caf2727038f8f8f8f021626240c2608240c00102c3002242400afafafaf",
INIT_0A => X"8c001424ac00008c243c3c243c2703008f8c3c10000caf2730038c343c270300",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000002403",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -122,14 +122,14 @@ INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"026482420264820264820264820264a2026582026482026482026482026403bd",
INIT_05 => X"62624202a2004262a242004262a242004262a20082a242004262a24200a28242",
INIT_06 => X"04040000511180400082b0b1bfbd00e044024042006243020000a2006263a200",
INIT_07 => X"108400100084000040824412111080b0b1b2bfbdbde0b0b1bf00004000021000",
INIT_08 => X"bde000bf4202400000bfbd42e0424202bde000bf0400bfbdbde0b0b1b2bf1211",
INIT_09 => X"000000000000000000040000802400800042e0a2006463404500624402054302",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"028362420283620283620283620283a2028562028362028362028362028304bd",
INIT_05 => X"82824202a2004282a242004282a242004282a20062a242004282a24200a26242",
INIT_06 => X"00a34200a2a24300a382a24200a2a3624202a3a24300a34200a2a2008284a200",
INIT_07 => X"42006243020000a2004300a382a24302430300a3a243024302430300a3a20043",
INIT_08 => X"bdbde0b0b1bf0000400002100004040000511180400082b0b1bfbd00e0440240",
INIT_09 => X"bf0400bfbdbde0b0b1b2bf1211108400100084000040824412111080b0b1b2bf",
INIT_0A => X"a2006463404500624402054302bde000bf4202400000bfbd42e0424202bde000",
INIT_0B => X"00000000000000000000000000000000000000000000040000802400800042e0",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -195,18 +195,18 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000600060004008400",
INIT_00 => X"00000000000000000000000000000000ff00000000ff18000700070005008500",
INIT_01 => X"000000000000000000000000000000000000012000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"31030030300300220200210200200200000400000400000400000400000420ff",
INIT_05 => X"000055550000000300ff000002000000000400000000ff000002000000000031",
INIT_06 => X"00000000000080000000000000ff10000020ff00000000200000000000000000",
INIT_07 => X"ff0000ff0100000000000010ff009000000000ff00000000001000ff00000000",
INIT_08 => X"000000000020ff000100ff000000002000000000000000ff00000000000010ff",
INIT_09 => X"000000000000000000200000002028000000000000ff00001000000400100400",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000001000000000110000001811110000100000000000000000000000",
INIT_07 => X"0000000020000000100000000000101a1011000000101c101a10110000001000",
INIT_08 => X"ff00000000001000ff0000000000000000000080000000000000ff10000020ff",
INIT_09 => X"00000000ff00000000000010ffff0000ff0100000000000010ff009000000000",
INIT_0A => X"0000ff00001000000500100500000000000020ff000100ff0000000020000000",
INIT_0B => X"0000000000000000000000000000000000000000000020000000202800000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
@ -272,18 +272,18 @@ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a00c800e000dc00d001",
INIT_01 => X"504c4844403c3834302c2824201c18141000082410200060125c1058fc005450",
INIT_00 => X"4c4844403c3834302c2824201c181410980e008004fd2a009800b000a800a001",
INIT_01 => X"504c4844403c3834302c2824201c181410003b2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"31340030303000221400211200201000141400131300121200111100101000f8",
INIT_04 => X"31340030303000221400211200201000111400221300551200661100441000f0",
INIT_05 => X"000055550400003802ff00001800ff00001804000002ff00001600ff00000031",
INIT_06 => X"000dc800030a210d0000101418e021080000fc020000200000c6040000200400",
INIT_07 => X"fc57c8fc0030c800050a0f06fc1c211014181ce020081014182100f6000001c8",
INIT_08 => X"180800100000fd001010e801080020001808001049c810e820081014181c06f4",
INIT_09 => X"000000000000000000001010200000207084080000fa0400210000dc0000bc00",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0004ff0000042100040004110004042111110404210004ff0000040000200400",
INIT_07 => X"020000200000f908121800040008210021000004082100210021000004081218",
INIT_08 => X"e020081014182100f6000001fb000dfb00030a210d0000101418e021080000fc",
INIT_09 => X"1049fb10e820081014181c06f4fc57fbfc3330fb00050a0f06fc1c211014181c",
INIT_0A => X"0000fa0400210000a800008800180800100000fd004310e80108002000180800",
INIT_0B => X"0000000000000000000000000000000000000000000000101020000020708408",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",

6
plasma/logic/simulation/plasma_TB.do
View File

@ -18,9 +18,9 @@ vcom -93 -work work ../uart.vhd
vcom -93 -work work ../ram_image.vhd
vcom -93 -work work ../plasma_TB.vhd
vsim -t 1ps tbench
view wave
#add wave *
vsim -t 1ps plasma_tb
#view wave
add wave *
do wave.do
view structure

51
xilinx_lib/xilinx_ghdl_simprim Executable file
View File

@ -0,0 +1,51 @@
#!/bin/sh
# $Id: xilinx_ghdl_simprim 88 2007-10-12 20:37:45Z mueller $
#
if [ -z "$XILINX" ]
then
echo "XILINX not defined"
exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl SIMPRIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d simprim ]
then
mkdir simprim
fi
#
cd $XILINX/ghdl/simprim
cp $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd .
cp $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd .
#
if [ ! -d simprim_vital_chop ]
then
mkdir simprim_vital_chop
fi
cd simprim_vital_chop
xilinx_vhdl_chop $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
#
cd ..
echo "# ghdl ... simprim_Vcomponents.vhd"
ghdl -a --ieee=synopsys --work=simprim simprim_Vcomponents.vhd
echo "# ghdl ... simprim_Vpackage.vhd"
ghdl -a --ieee=synopsys --work=simprim simprim_Vpackage.vhd
for file in `find simprim_vital_chop -name "*.vhd"`
do
echo "# ghdl ... $file"
ghdl -a -fexplicit --ieee=synopsys --work=simprim 2>&1 $file |\
tee $file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find

52
xilinx_lib/xilinx_ghdl_unisim Executable file
View File

@ -0,0 +1,52 @@
#!/bin/sh
# $Id: xilinx_ghdl_unisim 88 2007-10-12 20:37:45Z mueller $
#
if [ -z "$XILINX" ]
then
echo "XILINX not defined"
exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl UNISIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d unisim ]
then
mkdir unisim
fi
#
cd $XILINX/ghdl/unisim
cp $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd .
cp $XILINX/vhdl/src/unisims/unisim_VPKG.vhd .
#
if [ ! -d unisim_vital_chop ]
then
mkdir unisim_vital_chop
fi
cd unisim_vital_chop
xilinx_vhdl_chop $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
#
cd ..
echo "# ghdl ... unisim_VCOMP.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd
echo "# ghdl ... unisim_VPKG.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd
for file in `find unisim_vital_chop -name "*.vhd"`
do
echo "# ghdl ... $file"
ghdl -a -fexplicit --ieee=synopsys --work=unisim 2>&1 $file |\
tee $file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find unisim_vital_chop -name "*.ghdl.log" | xargs grep error
#

38
xilinx_lib/xilinx_vhdl_chop Executable file
View File

@ -0,0 +1,38 @@
#!/usr/bin/perl -w
# $Id: xilinx_vhdl_chop 87 2007-10-06 15:21:26Z mueller $
#
# Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@xxxxxx>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License Version 2 as published by the
# Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
#
# splits a xilinx unisim_VITAL.vhd file along separators looking like:
#
# -- $Header: <path>/and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
#
use 5.003; # require Perl 5.003 or higher
use strict; # require strict checking
while (<>) {
chomp;
my @line = split;
if (/^-- \$Header/) {
my @file = split(/\//,$line[2]);
my $name = $file[$#file];
$name =~ s/,v//;
print "writing $name \n";
close(OFILE);
open(OFILE, "> $name") or die "Couldn't open output file: $!\n";
}
print OFILE $_,"\n";
}
close(OFILE);